Merge branch 'for-v6.16/dt-bindings-clk-samsung' into next/clk

This commit is contained in:
Krzysztof Kozlowski 2025-04-27 21:21:53 +02:00
commit ab525e7336
2 changed files with 44 additions and 0 deletions

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@ -8,6 +8,7 @@ title: Samsung ExynosAuto v920 SoC clock controller
maintainers:
- Sunyeal Hong <sunyeal.hong@samsung.com>
- Shin Son <shin.son@samsung.com>
- Chanwoo Choi <cw00.choi@samsung.com>
- Krzysztof Kozlowski <krzk@kernel.org>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
@ -32,6 +33,7 @@ properties:
compatible:
enum:
- samsung,exynosautov920-cmu-top
- samsung,exynosautov920-cmu-cpucl0
- samsung,exynosautov920-cmu-peric0
- samsung,exynosautov920-cmu-peric1
- samsung,exynosautov920-cmu-misc
@ -69,6 +71,29 @@ allOf:
items:
- const: oscclk
- if:
properties:
compatible:
contains:
enum:
- samsung,exynosautov920-cmu-cpucl0
then:
properties:
clocks:
items:
- description: External reference clock (38.4 MHz)
- description: CMU_CPUCL0 SWITCH clock (from CMU_TOP)
- description: CMU_CPUCL0 CLUSTER clock (from CMU_TOP)
- description: CMU_CPUCL0 DBG clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: switch
- const: cluster
- const: dbg
- if:
properties:
compatible:

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@ -162,6 +162,25 @@
#define DOUT_CLKCMU_TAA_NOC 146
#define DOUT_TCXO_DIV2 147
/* CMU_CPUCL0 */
#define CLK_FOUT_CPUCL0_PLL 1
#define CLK_MOUT_PLL_CPUCL0 2
#define CLK_MOUT_CPUCL0_CLUSTER_USER 3
#define CLK_MOUT_CPUCL0_DBG_USER 4
#define CLK_MOUT_CPUCL0_SWITCH_USER 5
#define CLK_MOUT_CPUCL0_CLUSTER 6
#define CLK_MOUT_CPUCL0_CORE 7
#define CLK_DOUT_CLUSTER0_ACLK 8
#define CLK_DOUT_CLUSTER0_ATCLK 9
#define CLK_DOUT_CLUSTER0_MPCLK 10
#define CLK_DOUT_CLUSTER0_PCLK 11
#define CLK_DOUT_CLUSTER0_PERIPHCLK 12
#define CLK_DOUT_CPUCL0_DBG_NOC 13
#define CLK_DOUT_CPUCL0_DBG_PCLKDBG 14
#define CLK_DOUT_CPUCL0_NOCP 15
/* CMU_PERIC0 */
#define CLK_MOUT_PERIC0_IP_USER 1
#define CLK_MOUT_PERIC0_NOC_USER 2