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ARM: dts: microchip: sama5d2: Update the cache configuration for CPU

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Add the memory size properties for L1 and L2 according with block
diagram from datasheet:

- L1 cache configuration with 32 KB for both data and instruction cache.
- L2 cache configuration with 128 KB unified cache.

[root@sama5d2 ~]$ lscpu
Architecture:             armv7l
  Byte Order:             Little Endian
CPU(s):                   1
  On-line CPU(s) list:    0
Vendor ID:                ARM
  Model name:             Cortex-A5
Caches (sum of all):
  L1d:                    32 KiB (1 instance)
  L1i:                    32 KiB (1 instance)
  L2:                     128 KiB (1 instance)

Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
Link: https://lore.kernel.org/r/20250625064934.4828-2-mihai.sain@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
This commit is contained in:
Mihai Sain 2025-06-25 09:49:32 +03:00 committed by Claudiu Beznea
parent 7360dab3be
commit ab435d1265
1 changed files with 3 additions and 0 deletions
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3
arch/arm/boot/dts/microchip/sama5d2.dtsi
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@ -32,6 +32,8 @@ cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a5";
reg = <0>;
d-cache-size = <0x8000>; // L1, 32 KB
i-cache-size = <0x8000>; // L1, 32 KB
next-level-cache = <&L2>;
};
};
@ -160,6 +162,7 @@ L2: cache-controller@a00000 {
interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>;
cache-unified;
cache-level = <2>;
cache-size = <0x20000>; // L2, 128 KB
};
ebi: ebi@10000000 {