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drm/i915/vrr: Fix intel_vrr_always_use_vrr_tg()==true on TGL

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On TGL the hardware always needs TRANS_VBLANK.VBLANK_START
to be programemd with VACTIVE+SCL. Make it so.

The current way of programming it with crtc_vblank_start only
works for the legacy timing generator, as there the delayed
vblank does happen exactly at VACTIVE+SCL.

But if one tries to change intel_vrr_always_use_vrr_tg() to
always use the VRR timing generator on TGL, crtc_vblank_start
will point to the VRR timing generator's delayed vblank,
which may not match VACTIVE+SCL.

Fortunately the state checker caught the issue right away
when I tried intel_vrr_always_use_vrr_tg()==true on TGL.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20251020185038.4272-2-ville.syrjala@linux.intel.com
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
This commit is contained in:
Ville Syrjälä 2025-10-20 21:50:17 +03:00
parent 0790925dad
commit aa88371928
1 changed files with 6 additions and 0 deletions
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6
drivers/gpu/drm/i915/display/intel_display.c
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@ -2631,6 +2631,9 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
* to make it stand out in register dumps.
*/
crtc_vblank_start = 1;
} else if (DISPLAY_VER(display) == 12) {
/* VBLANK_START - VACTIVE defines SCL on TGL */
crtc_vblank_start = crtc_vdisplay + crtc_state->set_context_latency;
}
if (DISPLAY_VER(display) >= 4)
@ -2721,6 +2724,9 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
* to make it stand out in register dumps.
*/
crtc_vblank_start = 1;
} else if (DISPLAY_VER(display) == 12) {
/* VBLANK_START - VACTIVE defines SCL on TGL */
crtc_vblank_start = crtc_vdisplay + crtc_state->set_context_latency;
}
/*