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rtw-next patches for -next

Browse Source 
Improve MLO and some random fixes. Notable changes are:
 
  * drop usb device reference across drivers
 
 rtw89:
 
  * add RTL8922DE but not enabled yet, because BT coexistence is still
    cooking.
 
  * add USB RX aggregation to improve performance.
 
  * add USB TX flow control by tracking in-flight URBs.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEuyEnvMdOsBl1WjpdjlvZYmhshd8FAmnOCGAACgkQjlvZYmhs
 hd8RERAA2aJqVP5zQ1JaO5BjYktx3XfmGbW+fEQ8SEkWTO9xzJ7xMUByueQ3KtfE
 aoylfohWpRA+v29IV+VnrGZRZ3xvdddV5oIF8WFEbpSOSy4R/zl2c6qQMKdgvFe9
 zcsWkm0A8rQWx/kfof43vHdPLKtLsbItnIzsqwG/Vwd+MO2iqAZXPyl+ra9mTxai
 Glv1RYjvy7s1ZmkSfxIkyo+0DxZWYiwQuacWwYGEB3CF76jue4BpQJGwPPn3kR8F
 lfnLLIS9/k4gAnMtww4Iy5fgj4op/Osf150jisraLhqW4GaYemsLN/5/bocQlGBM
 Nwejaq1j2sSvzbJJGZBRFZ0kcQtdsb8JHF1uTBGvVdgzzk1+a/otN2So3jB3EQOp
 rDZPdGWmErN+RR2miIwUjyULMdFO5aTDB59LYuVe4co0ImWECi/WO86icCLqQHdz
 Ciwu0eKeljtHT9F1lbnvgJM0lGXCLdIwT4Veg7+zy25b51lMYf+OtRW497Lemyj6
 WtRJiJ+WCzWnGXUozAJPtDzUXtb5SnT3djF4vYa4pv1I4SP4TkN9DPVbFXT6nWEv
 6IgGZbA7hGqfvrPW9Ds2UypQ4i1hndlMVqe+alVeb07LHYa0p5d0lITgYZn/82o1
 XuXCBU9JOMO2LlH4WbGp0z2zV2aQfJQUX1nZvx3cmBXN4cBqsjI=
 =WvxS
 -----END PGP SIGNATURE-----

Merge tag 'rtw-next-2026-04-02' of https://github.com/pkshih/rtw into wireless-next

Ping-Ke Shih says:
==================
rtw-next patches for -next

Improve MLO and some random fixes. Notable changes are:

 * drop usb device reference across drivers

rtw89:

 * add RTL8922DE but not enabled yet, because BT coexistence is still
   cooking.

 * add USB RX aggregation to improve performance.

 * add USB TX flow control by tracking in-flight URBs.
==================

Signed-off-by: Johannes Berg <johannes.berg@intel.com>
This commit is contained in:
Johannes Berg 2026-04-07 16:20:39 +02:00
commit aa5e9884a2
59 changed files with 5192 additions and 415 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c
View File

@ -1475,8 +1475,6 @@ static int rtl8187_probe(struct usb_interface *intf,
usb_set_intfdata(intf, dev);
priv->udev = udev;
usb_get_dev(udev);
skb_queue_head_init(&priv->rx_queue);
BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
@ -1663,7 +1661,6 @@ static int rtl8187_probe(struct usb_interface *intf,
err_free_dmabuf:
kfree(priv->io_dmabuf);
usb_set_intfdata(intf, NULL);
usb_put_dev(udev);
err_free_dev:
ieee80211_free_hw(dev);
return err;
@ -1685,7 +1682,6 @@ static void rtl8187_disconnect(struct usb_interface *intf)
priv = dev->priv;
usb_reset_device(priv->udev);
usb_put_dev(interface_to_usbdev(intf));
kfree(priv->io_dmabuf);
ieee80211_free_hw(dev);
}

40
drivers/net/wireless/realtek/rtl8xxxu/core.c
View File

@ -4697,20 +4697,6 @@ static const struct ieee80211_rate rtl8xxxu_legacy_ratetable[] = {
{.bitrate = 540, .hw_value = 0x0b,},
};
static void rtl8xxxu_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss)
{
if (rate <= DESC_RATE_54M)
return;
if (rate >= DESC_RATE_MCS0 && rate <= DESC_RATE_MCS15) {
if (rate < DESC_RATE_MCS8)
*nss = 1;
else
*nss = 2;
*mcs = rate - DESC_RATE_MCS0;
}
}
static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
{
struct ieee80211_hw *hw = priv->hw;
@ -4820,23 +4806,25 @@ static void rtl8xxxu_set_aifs(struct rtl8xxxu_priv *priv, u8 slot_time)
void rtl8xxxu_update_ra_report(struct rtl8xxxu_ra_report *rarpt,
u8 rate, u8 sgi, u8 bw)
{
u8 mcs, nss;
rarpt->txrate.flags = 0;
if (rate <= DESC_RATE_54M) {
rarpt->txrate.legacy = rtl8xxxu_legacy_ratetable[rate].bitrate;
} else {
rtl8xxxu_desc_to_mcsrate(rate, &mcs, &nss);
} else if (rate >= DESC_RATE_MCS0 && rate <= DESC_RATE_MCS15) {
rarpt->txrate.flags |= RATE_INFO_FLAGS_MCS;
if (rate < DESC_RATE_MCS8)
rarpt->txrate.nss = 1;
else
rarpt->txrate.nss = 2;
rarpt->txrate.mcs = mcs;
rarpt->txrate.nss = nss;
rarpt->txrate.mcs = rate - DESC_RATE_MCS0;
if (sgi)
rarpt->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
rarpt->txrate.bw = bw;
} else {
return;
}
rarpt->bit_rate = cfg80211_calculate_bitrate(&rarpt->txrate);
@ -7698,11 +7686,12 @@ static int rtl8xxxu_probe(struct usb_interface *interface,
int ret;
int untested = 1;
udev = usb_get_dev(interface_to_usbdev(interface));
udev = interface_to_usbdev(interface);
switch (id->idVendor) {
case USB_VENDOR_ID_REALTEK:
switch(id->idProduct) {
case 0x0179:
case 0x1724:
case 0x8176:
case 0x8178:
@ -7756,10 +7745,8 @@ static int rtl8xxxu_probe(struct usb_interface *interface,
}
hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
if (!hw) {
ret = -ENOMEM;
goto err_put_dev;
}
if (!hw)
return -ENOMEM;
priv = hw->priv;
priv->hw = hw;
@ -7901,8 +7888,6 @@ static int rtl8xxxu_probe(struct usb_interface *interface,
mutex_destroy(&priv->h2c_mutex);
ieee80211_free_hw(hw);
err_put_dev:
usb_put_dev(udev);
return ret;
}
@ -7935,7 +7920,6 @@ static void rtl8xxxu_disconnect(struct usb_interface *interface)
"Device still attached, trying to reset\n");
usb_reset_device(priv->udev);
}
usb_put_dev(priv->udev);
ieee80211_free_hw(hw);
}

1
drivers/net/wireless/realtek/rtlwifi/pci.c
View File

@ -1674,6 +1674,7 @@ static void rtl_pci_deinit(struct ieee80211_hw *hw)
synchronize_irq(rtlpci->pdev->irq);
tasklet_kill(&rtlpriv->works.irq_tasklet);
tasklet_kill(&rtlpriv->works.irq_prepare_bcn_tasklet);
cancel_work_sync(&rtlpriv->works.lps_change_work);
}

12
drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.c
View File

@ -212,9 +212,9 @@ void rtl92d_fill_h2c_cmd(struct ieee80211_hw *hw,
struct rtl_priv *rtlpriv = rtl_priv(hw);
u8 boxcontent[4], boxextcontent[2];
u16 box_reg = 0, box_extreg = 0;
u8 wait_writeh2c_limmit = 100;
u8 wait_writeh2c_limit = 100;
bool bwrite_success = false;
u8 wait_h2c_limmit = 100;
u8 wait_h2c_limit = 100;
u32 h2c_waitcounter = 0;
bool isfw_read = false;
unsigned long flag;
@ -261,8 +261,8 @@ void rtl92d_fill_h2c_cmd(struct ieee80211_hw *hw,
}
while (!bwrite_success) {
wait_writeh2c_limmit--;
if (wait_writeh2c_limmit == 0) {
wait_writeh2c_limit--;
if (wait_writeh2c_limit == 0) {
pr_err("Write H2C fail because no trigger for FW INT!\n");
break;
}
@ -278,8 +278,8 @@ void rtl92d_fill_h2c_cmd(struct ieee80211_hw *hw,
isfw_read = _rtl92d_check_fw_read_last_h2c(hw, boxnum);
while (!isfw_read) {
wait_h2c_limmit--;
if (wait_h2c_limmit == 0) {
wait_h2c_limit--;
if (wait_h2c_limit == 0) {
rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
"Waiting too long for FW read clear HMEBox(%d)!\n",
boxnum);

4
drivers/net/wireless/realtek/rtlwifi/usb.c
View File

@ -986,7 +986,6 @@ int rtl_usb_probe(struct usb_interface *intf,
init_completion(&rtlpriv->firmware_loading_complete);
SET_IEEE80211_DEV(hw, &intf->dev);
udev = interface_to_usbdev(intf);
usb_get_dev(udev);
usb_priv = rtl_usbpriv(hw);
memset(usb_priv, 0, sizeof(*usb_priv));
usb_priv->dev.intf = intf;
@ -1038,7 +1037,6 @@ int rtl_usb_probe(struct usb_interface *intf,
rtl_deinit_core(hw);
error_out2:
_rtl_usb_io_handler_release(hw);
usb_put_dev(udev);
kfree(rtlpriv->usb_data);
ieee80211_free_hw(hw);
return -ENODEV;
@ -1050,7 +1048,6 @@ void rtl_usb_disconnect(struct usb_interface *intf)
struct ieee80211_hw *hw = usb_get_intfdata(intf);
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw));
struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
if (unlikely(!rtlpriv))
return;
@ -1072,7 +1069,6 @@ void rtl_usb_disconnect(struct usb_interface *intf)
kfree(rtlpriv->usb_data);
rtlpriv->cfg->ops->deinit_sw_vars(hw);
_rtl_usb_io_handler_release(hw);
usb_put_dev(rtlusb->udev);
usb_set_intfdata(intf, NULL);
ieee80211_free_hw(hw);
}

47
drivers/net/wireless/realtek/rtw88/coex.c
View File

@ -485,6 +485,13 @@ static void rtw_coex_monitor_bt_ctr(struct rtw_dev *rtwdev)
"[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n",
coex_stat->hi_pri_rx, coex_stat->hi_pri_tx,
coex_stat->lo_pri_rx, coex_stat->lo_pri_tx);
if (coex_stat->wl_under_lps || coex_stat->wl_under_ips ||
(coex_stat->hi_pri_rx > 60000 && coex_stat->hi_pri_tx == 60000 &&
coex_stat->lo_pri_rx > 60000 && coex_stat->lo_pri_tx == 60000))
coex_stat->bt_ctr_ok = false;
else
coex_stat->bt_ctr_ok = true;
}
static void rtw_coex_monitor_bt_enable(struct rtw_dev *rtwdev)
@ -1959,14 +1966,18 @@ static void rtw_coex_action_bt_hid(struct rtw_dev *rtwdev)
struct rtw_coex *coex = &rtwdev->coex;
struct rtw_coex_stat *coex_stat = &coex->stat;
struct rtw_efuse *efuse = &rtwdev->efuse;
bool is_bt_ctr_hi = false, is_toggle_table = false;
u8 table_case, tdma_case;
u32 slot_type = 0;
bool bt_multi_link_remain = false, is_toggle_table = false;
rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], %s()\n", __func__);
rtw_coex_set_ant_path(rtwdev, false, COEX_SET_ANT_2G);
rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
if (coex_stat->bt_ctr_ok &&
coex_stat->lo_pri_rx + coex_stat->lo_pri_tx > 360)
is_bt_ctr_hi = true;
if (efuse->share_ant) {
/* Shared-Ant */
if (coex_stat->bt_ble_exist) {
@ -1980,28 +1991,31 @@ static void rtw_coex_action_bt_hid(struct rtw_dev *rtwdev)
}
} else {
/* Legacy HID */
if (coex_stat->bt_profile_num == 1 &&
(coex_stat->bt_multi_link ||
(coex_stat->lo_pri_rx +
coex_stat->lo_pri_tx > 360) ||
coex_stat->bt_slave ||
bt_multi_link_remain)) {
slot_type = TDMA_4SLOT;
table_case = 12;
tdma_case = 20;
} else if (coex_stat->bt_a2dp_active) {
if (coex_stat->bt_a2dp_active) {
table_case = 9;
tdma_case = 18;
} else if (coex_stat->bt_profile_num == 1 &&
(coex_stat->bt_multi_link &&
(is_bt_ctr_hi || coex_stat->bt_slave ||
coex_stat->bt_multi_link_remain))) {
if (coex_stat->wl_gl_busy &&
(coex_stat->wl_rx_rate <= 3 ||
coex_stat->wl_rts_rx_rate <= 3))
table_case = 13;
else
table_case = 12;
tdma_case = 26;
} else if (coex_stat->bt_418_hid_exist &&
coex_stat->wl_gl_busy) {
is_toggle_table = true;
slot_type = TDMA_4SLOT;
table_case = 9;
tdma_case = 24;
table_case = 32;
tdma_case = 27;
} else if (coex_stat->bt_ble_hid_exist &&
coex_stat->wl_gl_busy) {
table_case = 32;
tdma_case = 9;
table_case = 36;
tdma_case = 0;
} else {
table_case = 9;
tdma_case = 9;
@ -3095,6 +3109,9 @@ void rtw_coex_bt_info_notify(struct rtw_dev *rtwdev, u8 *buf, u8 length)
for (i = 0; i < COEX_BTINFO_LENGTH; i++)
coex_stat->bt_info_c2h[rsp_source][i] = buf[i];
if (rtwdev->chip->id == RTW_CHIP_TYPE_8821A)
coex_stat->bt_info_c2h[rsp_source][5] = 0;
/* get the same info from bt, skip it */
if (coex_stat->bt_info_c2h[rsp_source][1] == coex_stat->bt_info_lb2 &&
coex_stat->bt_info_c2h[rsp_source][2] == coex_stat->bt_info_lb3 &&

6
drivers/net/wireless/realtek/rtw88/main.c
View File

@ -1805,6 +1805,7 @@ static void rtw_load_firmware_cb(const struct firmware *firmware, void *context)
{
struct rtw_fw_state *fw = context;
struct rtw_dev *rtwdev = fw->rtwdev;
struct wiphy *wiphy = rtwdev->hw->wiphy;
if (!firmware || !firmware->data) {
rtw_err(rtwdev, "failed to request firmware\n");
@ -1819,6 +1820,11 @@ static void rtw_load_firmware_cb(const struct firmware *firmware, void *context)
rtw_info(rtwdev, "%sFirmware version %u.%u.%u, H2C version %u\n",
fw->type == RTW_WOWLAN_FW ? "WOW " : "",
fw->version, fw->sub_version, fw->sub_index, fw->h2c_version);
if (fw->type == RTW_NORMAL_FW)
snprintf(wiphy->fw_version, sizeof(wiphy->fw_version),
"%u.%u.%u",
fw->version, fw->sub_version, fw->sub_index);
}
static int rtw_load_firmware(struct rtw_dev *rtwdev, enum rtw_fw_type type)

6
drivers/net/wireless/realtek/rtw88/main.h
View File

@ -432,6 +432,11 @@ enum rtw_wow_flags {
RTW_WOW_FLAG_MAX,
};
enum rtw_quirk_dis_caps {
QUIRK_DIS_CAP_PCI_ASPM,
QUIRK_DIS_CAP_LPS_DEEP,
};
/* the power index is represented by differences, which cck-1s & ht40-1s are
* the base values, so for 1s's differences, there are only ht20 & ofdm
*/
@ -1475,6 +1480,7 @@ struct rtw_coex_stat {
bool bt_game_hid_exist;
bool bt_hid_handle_cnt;
bool bt_mailbox_reply;
bool bt_ctr_ok;
bool wl_under_lps;
bool wl_under_ips;

34
drivers/net/wireless/realtek/rtw88/pci.c
View File

@ -2,6 +2,7 @@
/* Copyright(c) 2018-2019 Realtek Corporation
*/
#include <linux/dmi.h>
#include <linux/module.h>
#include <linux/pci.h>
#include "main.h"
@ -1744,6 +1745,34 @@ const struct pci_error_handlers rtw_pci_err_handler = {
};
EXPORT_SYMBOL(rtw_pci_err_handler);
static int rtw_pci_disable_caps(const struct dmi_system_id *dmi)
{
uintptr_t dis_caps = (uintptr_t)dmi->driver_data;
if (dis_caps & BIT(QUIRK_DIS_CAP_PCI_ASPM))
rtw_pci_disable_aspm = true;
if (dis_caps & BIT(QUIRK_DIS_CAP_LPS_DEEP))
rtw_disable_lps_deep_mode = true;
return 1;
}
static const struct dmi_system_id rtw_pci_quirks[] = {
{
.callback = rtw_pci_disable_caps,
.ident = "HP Notebook - P3S95EA#ACB",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "HP"),
DMI_MATCH(DMI_PRODUCT_NAME, "HP Notebook"),
DMI_MATCH(DMI_PRODUCT_SKU, "P3S95EA#ACB"),
},
.driver_data = (void *)(BIT(QUIRK_DIS_CAP_PCI_ASPM) |
BIT(QUIRK_DIS_CAP_LPS_DEEP)),
},
{}
};
int rtw_pci_probe(struct pci_dev *pdev,
const struct pci_device_id *id)
{
@ -1771,6 +1800,8 @@ int rtw_pci_probe(struct pci_dev *pdev,
rtwpci = (struct rtw_pci *)rtwdev->priv;
atomic_set(&rtwpci->link_usage, 1);
dmi_check_system(rtw_pci_quirks);
ret = rtw_core_init(rtwdev);
if (ret)
goto err_release_hw;
@ -1804,7 +1835,8 @@ int rtw_pci_probe(struct pci_dev *pdev,
}
/* Disable PCIe ASPM L1 while doing NAPI poll for 8821CE */
if (rtwdev->chip->id == RTW_CHIP_TYPE_8821C && bridge->vendor == PCI_VENDOR_ID_INTEL)
if (rtwdev->chip->id == RTW_CHIP_TYPE_8821C &&
bridge && bridge->vendor == PCI_VENDOR_ID_INTEL)
rtwpci->rx_no_aspm = true;
rtw_pci_phy_cfg(rtwdev);

5
drivers/net/wireless/realtek/rtw88/rtw8703b.c
View File

@ -1794,6 +1794,11 @@ static const struct coex_table_para table_sant_8703b[] = {
{0x66556aaa, 0x6a5a6aaa}, /* case-30 */
{0xffffffff, 0x5aaa5aaa},
{0x56555555, 0x5a5a5aaa},
{0xdaffdaff, 0xdaffdaff},
{0xddffddff, 0xddffddff},
{0xe5555555, 0xe5555555}, /* case-35 */
{0xea5a5a5a, 0xea5a5a5a},
{0xea6a6a6a, 0xea6a6a6a},
};
/* Shared-Antenna TDMA */

5
drivers/net/wireless/realtek/rtw88/rtw8723d.c
View File

@ -1459,6 +1459,11 @@ static const struct coex_table_para table_sant_8723d[] = {
{0x66556aaa, 0x6a5a6aaa}, /* case-30 */
{0xffffffff, 0x5aaa5aaa},
{0x56555555, 0x5a5a5aaa},
{0xdaffdaff, 0xdaffdaff},
{0xddffddff, 0xddffddff},
{0xe5555555, 0xe5555555}, /* case-35 */
{0xea5a5a5a, 0xea5a5a5a},
{0xea6a6a6a, 0xea6a6a6a},
};
/* Non-Shared-Antenna Coex Table */

7
drivers/net/wireless/realtek/rtw88/rtw8821a.c
View File

@ -998,7 +998,12 @@ static const struct coex_table_para table_sant_8821a[] = {
{0x66556655, 0x66556655},
{0x66556aaa, 0x6a5a6aaa}, /* case-30 */
{0xffffffff, 0x5aaa5aaa},
{0x56555555, 0x5a5a5aaa}
{0x56555555, 0x5a5a5aaa},
{0xdaffdaff, 0xdaffdaff},
{0xddffddff, 0xddffddff},
{0xe5555555, 0xe5555555}, /* case-35 */
{0xea5a5a5a, 0xea5a5a5a},
{0xea6a6a6a, 0xea6a6a6a},
};
/* Non-Shared-Antenna Coex Table */

7
drivers/net/wireless/realtek/rtw88/rtw8821c.c
View File

@ -1727,7 +1727,12 @@ static const struct coex_table_para table_sant_8821c[] = {
{0x66556655, 0x66556655},
{0x66556aaa, 0x6a5a6aaa}, /* case-30 */
{0xffffffff, 0x5aaa5aaa},
{0x56555555, 0x5a5a5aaa}
{0x56555555, 0x5a5a5aaa},
{0xdaffdaff, 0xdaffdaff},
{0xddffddff, 0xddffddff},
{0xe5555555, 0xe5555555}, /* case-35 */
{0xea5a5a5a, 0xea5a5a5a},
{0xea6a6a6a, 0xea6a6a6a},
};
/* Non-Shared-Antenna Coex Table */

5
drivers/net/wireless/realtek/rtw88/rtw8822b.c
View File

@ -2217,6 +2217,11 @@ static const struct coex_table_para table_sant_8822b[] = {
{0x66556aaa, 0x6a5a6aaa}, /* case-30 */
{0xffffffff, 0x5aaa5aaa},
{0x56555555, 0x5a5a5aaa},
{0xdaffdaff, 0xdaffdaff},
{0xddffddff, 0xddffddff},
{0xe5555555, 0xe5555555}, /* case-35 */
{0xea5a5a5a, 0xea5a5a5a},
{0xea6a6a6a, 0xea6a6a6a},
};
/* Non-Shared-Antenna Coex Table */

5
drivers/net/wireless/realtek/rtw88/rtw8822c.c
View File

@ -5035,6 +5035,9 @@ static const struct coex_table_para table_sant_8822c[] = {
{0x56555555, 0x5a5a5aaa},
{0xdaffdaff, 0xdaffdaff},
{0xddffddff, 0xddffddff},
{0xe5555555, 0xe5555555}, /* case-35 */
{0xea5a5a5a, 0xea5a5a5a},
{0xea6a6a6a, 0xea6a6a6a},
};
/* Non-Shared-Antenna Coex Table */
@ -5401,7 +5404,7 @@ const struct rtw_chip_info rtw8822c_hw_spec = {
.max_sched_scan_ssids = 4,
#endif
.max_scan_ie_len = (RTW_PROBE_PG_CNT - 1) * TX_PAGE_SIZE,
.coex_para_ver = 0x22020720,
.coex_para_ver = 0x26020420,
.bt_desired_ver = 0x20,
.scbd_support = true,
.new_scbd10_def = true,

8
drivers/net/wireless/realtek/rtw88/rx.c
View File

@ -295,6 +295,14 @@ void rtw_rx_query_rx_desc(struct rtw_dev *rtwdev, void *rx_desc8,
pkt_stat->tsf_low = le32_get_bits(rx_desc->w5, RTW_RX_DESC_W5_TSFL);
if (unlikely(pkt_stat->rate >= DESC_RATE_MAX)) {
rtw_dbg(rtwdev, RTW_DBG_UNEXP,
"unexpected RX rate=0x%x\n", pkt_stat->rate);
pkt_stat->rate = DESC_RATE1M;
pkt_stat->bw = RTW_CHANNEL_WIDTH_20;
}
/* drv_info_sz is in unit of 8-bytes */
pkt_stat->drv_info_sz *= 8;

2
drivers/net/wireless/realtek/rtw88/tx.c
View File

@ -421,7 +421,7 @@ void rtw_tx_pkt_info_update(struct rtw_dev *rtwdev,
pkt_info->mac_id = rtwvif->mac_id;
}
if (ieee80211_is_mgmt(fc) || ieee80211_is_nullfunc(fc))
if (ieee80211_is_mgmt(fc) || ieee80211_is_any_nullfunc(fc))
rtw_tx_mgmt_pkt_info_update(rtwdev, pkt_info, sta, skb);
else if (ieee80211_is_data(fc))
rtw_tx_data_pkt_info_update(rtwdev, pkt_info, sta, skb);

3
drivers/net/wireless/realtek/rtw88/usb.c
View File

@ -1041,7 +1041,7 @@ static int rtw_usb_intf_init(struct rtw_dev *rtwdev,
struct usb_interface *intf)
{
struct rtw_usb *rtwusb = rtw_get_usb_priv(rtwdev);
struct usb_device *udev = usb_get_dev(interface_to_usbdev(intf));
struct usb_device *udev = interface_to_usbdev(intf);
int ret;
rtwusb->udev = udev;
@ -1067,7 +1067,6 @@ static void rtw_usb_intf_deinit(struct rtw_dev *rtwdev,
{
struct rtw_usb *rtwusb = rtw_get_usb_priv(rtwdev);
usb_put_dev(rtwusb->udev);
kfree(rtwusb->usb_data);
usb_set_intfdata(intf, NULL);
}

72
drivers/net/wireless/realtek/rtw89/chan.c
View File

@ -276,7 +276,6 @@ void rtw89_config_roc_chandef(struct rtw89_dev *rtwdev,
}
hal->roc_chandef = *chandef;
hal->roc_link_index = rtw89_vif_link_inst_get_index(rtwvif_link);
} else {
cur = atomic_cmpxchg(&hal->roc_chanctx_idx, idx,
RTW89_CHANCTX_IDLE);
@ -382,6 +381,23 @@ static void rtw89_normalize_link_chanctx(struct rtw89_dev *rtwdev,
rtw89_swap_chanctx(rtwdev, rtwvif_link->chanctx_idx, cur->chanctx_idx);
}
static u8 rtw89_entity_role_get_index(struct rtw89_dev *rtwdev)
{
enum rtw89_entity_mode mode;
mode = rtw89_get_entity_mode(rtwdev);
switch (mode) {
default:
WARN(1, "Invalid ent mode: %d\n", mode);
fallthrough;
case RTW89_ENTITY_MODE_SCC_OR_SMLD:
case RTW89_ENTITY_MODE_MCC:
return 0;
case RTW89_ENTITY_MODE_MCC_PREPARE:
return 1;
}
}
const struct rtw89_chan *__rtw89_mgnt_chan_get(struct rtw89_dev *rtwdev,
const char *caller_message,
u8 link_index, bool nullchk)
@ -389,8 +405,6 @@ const struct rtw89_chan *__rtw89_mgnt_chan_get(struct rtw89_dev *rtwdev,
struct rtw89_hal *hal = &rtwdev->hal;
struct rtw89_entity_mgnt *mgnt = &hal->entity_mgnt;
enum rtw89_chanctx_idx chanctx_idx;
enum rtw89_chanctx_idx roc_idx;
enum rtw89_entity_mode mode;
u8 role_index;
lockdep_assert_wiphy(rtwdev->hw->wiphy);
@ -401,33 +415,12 @@ const struct rtw89_chan *__rtw89_mgnt_chan_get(struct rtw89_dev *rtwdev,
goto dflt;
}
mode = rtw89_get_entity_mode(rtwdev);
switch (mode) {
case RTW89_ENTITY_MODE_SCC_OR_SMLD:
case RTW89_ENTITY_MODE_MCC:
role_index = 0;
break;
case RTW89_ENTITY_MODE_MCC_PREPARE:
role_index = 1;
break;
default:
WARN(1, "Invalid ent mode: %d\n", mode);
goto dflt;
}
role_index = rtw89_entity_role_get_index(rtwdev);
chanctx_idx = mgnt->chanctx_tbl[role_index][link_index];
if (chanctx_idx == RTW89_CHANCTX_IDLE)
goto dflt;
roc_idx = atomic_read(&hal->roc_chanctx_idx);
if (roc_idx != RTW89_CHANCTX_IDLE) {
/* ROC is ongoing (given ROC runs on @hal->roc_link_index).
* If @link_index is the same, get the ongoing ROC chanctx.
*/
if (link_index == hal->roc_link_index)
chanctx_idx = roc_idx;
}
return rtw89_chan_get(rtwdev, chanctx_idx);
dflt:
@ -490,10 +483,28 @@ rtw89_entity_sel_mlo_dbcc_mode(struct rtw89_dev *rtwdev, u8 active_hws)
}
}
static
void rtw89_entity_recalc_mlo_dbcc_mode(struct rtw89_dev *rtwdev, u8 active_hws)
static void rtw89_entity_recalc_mlo_dbcc_mode(struct rtw89_dev *rtwdev)
{
struct rtw89_entity_mgnt *mgnt = &rtwdev->hal.entity_mgnt;
enum rtw89_mlo_dbcc_mode mode;
struct rtw89_vif *role;
u8 active_hws = 0;
u8 ridx;
ridx = rtw89_entity_role_get_index(rtwdev);
role = mgnt->active_roles[ridx];
if (role) {
struct rtw89_vif_link *link;
int i;
for (i = 0; i < role->links_inst_valid_num; i++) {
link = rtw89_vif_get_link_inst(role, i);
if (!link || !link->chanctx_assigned)
continue;
active_hws |= BIT(i);
}
}
mode = rtw89_entity_sel_mlo_dbcc_mode(rtwdev, active_hws);
rtwdev->mlo_dbcc_mode = mode;
@ -507,7 +518,6 @@ static void rtw89_entity_recalc_mgnt_roles(struct rtw89_dev *rtwdev)
struct rtw89_entity_mgnt *mgnt = &hal->entity_mgnt;
struct rtw89_vif_link *link;
struct rtw89_vif *role;
u8 active_hws = 0;
u8 pos = 0;
int i, j;
@ -556,13 +566,10 @@ static void rtw89_entity_recalc_mgnt_roles(struct rtw89_dev *rtwdev)
continue;
mgnt->chanctx_tbl[pos][i] = link->chanctx_idx;
active_hws |= BIT(i);
}
mgnt->active_roles[pos++] = role;
}
rtw89_entity_recalc_mlo_dbcc_mode(rtwdev, active_hws);
}
enum rtw89_entity_mode rtw89_entity_recalc(struct rtw89_dev *rtwdev)
@ -632,6 +639,9 @@ enum rtw89_entity_mode rtw89_entity_recalc(struct rtw89_dev *rtwdev)
return rtw89_get_entity_mode(rtwdev);
rtw89_set_entity_mode(rtwdev, mode);
rtw89_entity_recalc_mlo_dbcc_mode(rtwdev);
return mode;
}

155
drivers/net/wireless/realtek/rtw89/core.c
View File

@ -463,7 +463,7 @@ void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev)
chan = rtw89_mgnt_chan_get(rtwdev, 0);
__rtw89_core_set_chip_txpwr(rtwdev, chan, RTW89_PHY_0);
if (!rtwdev->support_mlo)
if (rtwdev->chip->chip_gen == RTW89_CHIP_AX)
return;
chan = rtw89_mgnt_chan_get(rtwdev, 1);
@ -558,7 +558,7 @@ int rtw89_set_channel(struct rtw89_dev *rtwdev)
chan = rtw89_mgnt_chan_get(rtwdev, 0);
__rtw89_set_channel(rtwdev, chan, RTW89_MAC_0, RTW89_PHY_0);
if (!rtwdev->support_mlo)
if (rtwdev->chip->chip_gen == RTW89_CHIP_AX)
return 0;
chan = rtw89_mgnt_chan_get(rtwdev, 1);
@ -3203,7 +3203,7 @@ static void rtw89_core_update_rx_freq_from_ie(struct rtw89_dev *rtwdev,
u8 *variable;
int chan;
if (!rtwdev->chip->rx_freq_frome_ie)
if (!rtwdev->chip->rx_freq_from_ie)
return;
if (!rtwdev->scanning)
@ -3272,6 +3272,114 @@ static void rtw89_core_correct_mcc_chan(struct rtw89_dev *rtwdev,
rcu_read_unlock();
}
static void __rtw89_core_tid_rx_stats_reset(struct rtw89_tid_stats *tid_stats)
{
tid_stats->last_pn = -1LL;
tid_stats->last_sn = IEEE80211_SN_MASK;
}
void rtw89_core_tid_rx_stats_ctrl(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
struct ieee80211_ampdu_params *params, bool enable)
{
struct rtw89_tid_stats *tid_stats;
u16 tid = params->tid;
tid_stats = &rtwsta->tid_rx_stats[tid];
if (enable) {
__rtw89_core_tid_rx_stats_reset(tid_stats);
tid_stats->started = true;
} else {
tid_stats->started = false;
}
}
void rtw89_core_tid_rx_stats_reset(struct rtw89_dev *rtwdev)
{
struct rtw89_tid_stats *tid_stats;
struct ieee80211_sta *sta;
struct rtw89_sta *rtwsta;
u16 tid;
for_each_station(sta, rtwdev->hw) {
rtwsta = sta_to_rtwsta(sta);
for (tid = 0; tid < IEEE80211_NUM_TIDS; tid++) {
tid_stats = &rtwsta->tid_rx_stats[tid];
if (!tid_stats->started)
continue;
__rtw89_core_tid_rx_stats_reset(tid_stats);
}
}
}
static bool rtw89_core_skb_pn_valid(struct rtw89_dev *rtwdev,
struct rtw89_rx_desc_info *desc_info,
struct sk_buff *skb)
{
struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
const struct rtw89_chip_info *chip = rtwdev->chip;
struct rtw89_sta_link *rtwsta_link;
struct rtw89_tid_stats *tid_stats;
struct rtw89_sta *rtwsta;
u8 tid, *ccmp_hdr_ptr;
s64 pn, last_pn;
u16 mpdu_sn;
int hdrlen;
if (chip->chip_gen != RTW89_CHIP_AX)
return true;
if (!ieee80211_is_data_qos(hdr->frame_control))
return true;
if (!desc_info->hw_dec || !desc_info->addr1_match)
return true;
guard(rcu)();
rtwsta_link = rtw89_assoc_link_rcu_dereference(rtwdev, desc_info->mac_id);
if (!rtwsta_link)
return true;
rtwsta = rtwsta_link->rtwsta;
tid = ieee80211_get_tid(hdr);
tid_stats = &rtwsta->tid_rx_stats[tid];
if (!tid_stats->started)
return true;
switch (desc_info->sec_type) {
case RTW89_SEC_KEY_TYPE_CCMP128:
case RTW89_SEC_KEY_TYPE_CCMP256:
case RTW89_SEC_KEY_TYPE_GCMP128:
case RTW89_SEC_KEY_TYPE_GCMP256:
mpdu_sn = ieee80211_get_sn(hdr);
hdrlen = ieee80211_hdrlen(hdr->frame_control);
ccmp_hdr_ptr = skb->data + hdrlen;
ccmp_hdr2pn(&pn, ccmp_hdr_ptr);
last_pn = tid_stats->last_pn;
if (pn > last_pn) {
if (ieee80211_sn_less(mpdu_sn, tid_stats->last_sn)) {
dev_kfree_skb_any(skb);
return false;
}
tid_stats->last_sn = mpdu_sn;
tid_stats->last_pn = pn;
}
break;
default:
break;
}
return true;
}
static void rtw89_core_rx_to_mac80211(struct rtw89_dev *rtwdev,
struct rtw89_rx_phy_ppdu *phy_ppdu,
struct rtw89_rx_desc_info *desc_info,
@ -3421,6 +3529,7 @@ void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev,
desc_info->sec_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_SEC_CAM_IDX_MASK);
desc_info->mac_id = le32_get_bits(rxd_l->dword5, AX_RXD_MAC_ID_MASK);
desc_info->rx_pl_id = le32_get_bits(rxd_l->dword5, AX_RXD_RX_PL_ID_MASK);
desc_info->sec_type = le32_get_bits(rxd_l->dword7, AX_RXD_SEC_TYPE_MASK);
}
EXPORT_SYMBOL(rtw89_core_query_rxdesc);
@ -3450,6 +3559,7 @@ void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev,
desc_info->mac_id = le32_get_bits(rxd_s->dword2, BE_RXD_MAC_ID_MASK);
desc_info->addr_cam_valid = le32_get_bits(rxd_s->dword2, BE_RXD_ADDR_CAM_VLD);
desc_info->sec_type = le32_get_bits(rxd_s->dword3, BE_RXD_SEC_TYPE_MASK);
desc_info->icv_err = le32_get_bits(rxd_s->dword3, BE_RXD_ICV_ERR);
desc_info->crc32_err = le32_get_bits(rxd_s->dword3, BE_RXD_CRC32_ERR);
desc_info->hw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_HW_DEC);
@ -3523,6 +3633,7 @@ void rtw89_core_query_rxdesc_v3(struct rtw89_dev *rtwdev,
desc_info->mac_id = le32_get_bits(rxd_s->dword2, BE_RXD_MAC_ID_V1);
desc_info->addr_cam_valid = le32_get_bits(rxd_s->dword2, BE_RXD_ADDR_CAM_VLD);
desc_info->sec_type = le32_get_bits(rxd_s->dword3, BE_RXD_SEC_TYPE_MASK);
desc_info->icv_err = le32_get_bits(rxd_s->dword3, BE_RXD_ICV_ERR);
desc_info->crc32_err = le32_get_bits(rxd_s->dword3, BE_RXD_CRC32_ERR);
desc_info->hw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_HW_DEC);
@ -3802,6 +3913,10 @@ void rtw89_core_rx(struct rtw89_dev *rtwdev,
memset(rx_status, 0, sizeof(*rx_status));
rtw89_core_update_rx_status(rtwdev, skb, desc_info, rx_status);
rtw89_core_rx_pkt_hdl(rtwdev, skb, desc_info);
if (!rtw89_core_skb_pn_valid(rtwdev, desc_info, skb))
return;
if (desc_info->long_rxdesc &&
BIT(desc_info->frame_type) & PPDU_FILTER_BITMAP)
skb_queue_tail(&ppdu_sts->rx_queue[band], skb);
@ -4713,6 +4828,35 @@ static void rtw89_track_work(struct wiphy *wiphy, struct wiphy_work *work)
rtw89_enter_lps_track(rtwdev);
}
void rtw89_core_dm_disable_cfg(struct rtw89_dev *rtwdev, u32 new)
{
struct rtw89_hal *hal = &rtwdev->hal;
u32 old = hal->disabled_dm_bitmap;
if (new == old)
return;
hal->disabled_dm_bitmap = new;
rtw89_debug(rtwdev, RTW89_DBG_STATE, "Disable DM: 0x%x -> 0x%x\n", old, new);
}
void rtw89_core_dm_disable_set(struct rtw89_dev *rtwdev, enum rtw89_dm_type type)
{
struct rtw89_hal *hal = &rtwdev->hal;
u32 cur = hal->disabled_dm_bitmap;
rtw89_core_dm_disable_cfg(rtwdev, cur | BIT(type));
}
void rtw89_core_dm_disable_clr(struct rtw89_dev *rtwdev, enum rtw89_dm_type type)
{
struct rtw89_hal *hal = &rtwdev->hal;
u32 cur = hal->disabled_dm_bitmap;
rtw89_core_dm_disable_cfg(rtwdev, cur & ~BIT(type));
}
u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size)
{
unsigned long bit;
@ -6118,7 +6262,6 @@ int rtw89_core_init(struct rtw89_dev *rtwdev)
return -ENOMEM;
spin_lock_init(&rtwdev->ba_lock);
spin_lock_init(&rtwdev->rpwm_lock);
mutex_init(&rtwdev->rf_mutex);
rtwdev->total_sta_assoc = 0;
rtw89_init_wait(&rtwdev->mcc.wait);
@ -6177,7 +6320,6 @@ void rtw89_core_deinit(struct rtw89_dev *rtwdev)
__rtw89_fw_free_all_early_h2c(rtwdev);
destroy_workqueue(rtwdev->txq_wq);
mutex_destroy(&rtwdev->rf_mutex);
}
EXPORT_SYMBOL(rtw89_core_deinit);
@ -6753,7 +6895,8 @@ struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device,
bool support_mlo;
bool no_chanctx;
firmware = rtw89_early_fw_feature_recognize(device, chip, &early_fw, &fw_format);
firmware = rtw89_early_fw_feature_recognize(device, chip, variant,
&early_fw, &fw_format);
ops = kmemdup(&rtw89_ops, sizeof(rtw89_ops), GFP_KERNEL);
if (!ops)

105
drivers/net/wireless/realtek/rtw89/core.h
View File

@ -873,6 +873,14 @@ enum rtw89_phy_idx {
RTW89_PHY_NUM,
};
enum rtw89_fbtc_bt_index {
BTC_BT_1ST = 0x0,
BTC_BT_2ND = 0x1,
BTC_BT_EXT = 0x2,
BTC_ALL_BT = 0x2,
BTC_ALL_BT_EZL = 0x3 /* BT0+BT1+Ext-ZB(or Thread, or LTE) */
};
#define __RTW89_MLD_MAX_LINK_NUM 2
#define RTW89_MLD_NON_STA_LINK_NUM 1
@ -1126,6 +1134,7 @@ struct rtw89_rx_desc_info {
bool addr_cam_valid;
u8 addr_cam_id;
u8 sec_cam_id;
u8 sec_type;
u8 mac_id;
u16 offset;
u16 rxd_len;
@ -2196,6 +2205,15 @@ struct rtw89_btc_bt_info {
u32 rsvd: 17;
};
struct rtw89_btc_rf_trx_para_v9 {
u32 wl_tx_power[RTW89_PHY_NUM]; /* absolute Tx power (dBm), 1's complement -5->0x85 */
u32 wl_rx_gain[RTW89_PHY_NUM]; /* rx gain table index (TBD.) */
u32 bt_tx_power[BTC_ALL_BT]; /* decrease Tx power (dB) */
u32 bt_rx_gain[BTC_ALL_BT]; /* LNA constrain level */
u32 zb_tx_power[BTC_ALL_BT]; /* 15.4 devrease Tx power (dB) */
u32 zb_rx_gain[BTC_ALL_BT]; /* 15.4 constrain level */
};
struct rtw89_btc_cx {
struct rtw89_btc_wl_info wl;
struct rtw89_btc_bt_info bt;
@ -3561,6 +3579,8 @@ struct rtw89_efuse {
u8 rfe_type;
char country_code[2];
u8 adc_td;
u8 bt_setting_2;
u8 bt_setting_3;
};
struct rtw89_phy_rate_pattern {
@ -4152,6 +4172,21 @@ struct rtw89_reg_imr {
u32 set;
};
#define RTW89_MODULE_FWNAME_PLACEHOLDER_0 0,
#define __RTW89_GEN_MODULE_FWNAME_FMT(placeholder_or_ignored, strfmt) \
__take_second_arg(placeholder_or_ignored, strfmt)
#define RTW89_GEN_MODULE_FWNAME_FMT(maxfmt) \
__RTW89_GEN_MODULE_FWNAME_FMT(RTW89_MODULE_FWNAME_PLACEHOLDER_ ## maxfmt, \
"-" __stringify(maxfmt))
#define RTW89_GEN_MODULE_FWNAME(basename, maxformat) \
basename RTW89_GEN_MODULE_FWNAME_FMT(maxformat) ".bin"
struct rtw89_fw_def {
const char *fw_basename;
u8 fw_format_max;
u16 fw_b_aid;
};
struct rtw89_phy_table {
const struct rtw89_reg2_def *regs;
u32 n_regs;
@ -4494,8 +4529,7 @@ struct rtw89_chip_info {
const struct rtw89_chip_ops *ops;
const struct rtw89_mac_gen_def *mac_def;
const struct rtw89_phy_gen_def *phy_def;
const char *fw_basename;
u8 fw_format_max;
struct rtw89_fw_def fw_def;
bool try_ce_fw;
u8 bbmcu_nr;
u32 needed_fw_elms;
@ -4529,7 +4563,7 @@ struct rtw89_chip_info {
bool support_noise;
bool ul_tb_waveform_ctrl;
bool ul_tb_pwr_diff;
bool rx_freq_frome_ie;
bool rx_freq_from_ie;
bool hw_sec_hdr;
bool hw_mgmt_tx_encrypt;
bool hw_tkip_crypto;
@ -4592,6 +4626,10 @@ struct rtw89_chip_info {
const struct rtw89_btc_rf_trx_para *rf_para_ulink;
u8 rf_para_dlink_num;
const struct rtw89_btc_rf_trx_para *rf_para_dlink;
const struct rtw89_btc_rf_trx_para_v9 *rf_para_ulink_v9;
const struct rtw89_btc_rf_trx_para_v9 *rf_para_dlink_v9;
u8 rf_para_ulink_num_v9;
u8 rf_para_dlink_num_v9;
u8 ps_mode_supported;
u8 low_power_hci_modes;
@ -4633,6 +4671,7 @@ struct rtw89_chip_info {
struct rtw89_chip_variant {
bool no_mcs_12_13: 1;
u32 fw_min_ver_code;
const struct rtw89_fw_def *fw_def_override;
};
union rtw89_bus_info {
@ -4724,6 +4763,8 @@ enum rtw89_fw_type {
RTW89_FW_NORMAL = 1,
RTW89_FW_WOWLAN = 3,
RTW89_FW_NORMAL_CE = 5,
RTW89_FW_NORMAL_B = 14,
RTW89_FW_WOWLAN_B = 15,
RTW89_FW_BBMCU0 = 64,
RTW89_FW_BBMCU1 = 65,
RTW89_FW_LOGFMT = 255,
@ -4779,6 +4820,7 @@ enum rtw89_fw_feature {
RTW89_FW_FEATURE_SER_L1_BY_EVENT,
RTW89_FW_FEATURE_SIM_SER_L0L1_BY_HALT_H2C,
RTW89_FW_FEATURE_LPS_ML_INFO_V1,
RTW89_FW_FEATURE_SER_POST_RECOVER_DMAC,
NUM_OF_RTW89_FW_FEATURES,
};
@ -5152,7 +5194,6 @@ struct rtw89_hal {
bool no_eht;
atomic_t roc_chanctx_idx;
u8 roc_link_index;
DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES);
DECLARE_BITMAP(entity_map, NUM_OF_RTW89_CHANCTX);
@ -5575,9 +5616,11 @@ struct rtw89_tssi_info {
struct rtw89_power_trim_info {
bool pg_thermal_trim;
bool pg_pa_bias_trim;
bool pg_vco_trim;
u8 thermal_trim[RF_PATH_MAX];
u8 pa_bias_trim[RF_PATH_MAX];
u8 pad_bias_trim[RF_PATH_MAX];
u8 vco_trim[RF_PATH_MAX];
};
enum rtw89_regd_func {
@ -5736,11 +5779,18 @@ enum rtw89_ser_rcvy_step {
RTW89_NUM_OF_SER_FLAGS
};
struct rtw89_ser_count {
unsigned int l1;
unsigned int l2;
};
struct rtw89_ser {
u8 state;
u8 alarm_event;
bool prehandle_l1;
struct rtw89_ser_count sw_cnt;
struct work_struct ser_hdl_work;
struct delayed_work ser_alarm_work;
const struct state_ent *st_tbl;
@ -5901,8 +5951,11 @@ struct rtw89_phy_efuse_gain {
bool offset_valid;
bool comp_valid;
s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */
s8 offset2[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */
s8 offset_base[RTW89_PHY_NUM]; /* S(8, 4) */
s8 rssi_base[RTW89_PHY_NUM]; /* S(8, 4) */
s8 ref_gain_base[RTW89_PHY_NUM]; /* S(8, 2) */
s8 cck_rpl_base[RTW89_PHY_NUM]; /* S(8, 0) */
s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */
};
@ -6129,6 +6182,12 @@ struct rtw89_beacon_track_info {
u32 tbtt_diff_th;
};
struct rtw89_tid_stats {
s64 last_pn;
u16 last_sn;
bool started;
};
struct rtw89_dev {
struct ieee80211_hw *hw;
struct device *dev;
@ -6158,8 +6217,6 @@ struct rtw89_dev {
refcount_t refcount_ap_info;
struct list_head rtwvifs_list;
/* used to protect rf read write */
struct mutex rf_mutex;
struct workqueue_struct *txq_wq;
struct work_struct txq_work;
struct delayed_work txq_reinvoke_work;
@ -6337,6 +6394,7 @@ struct rtw89_sta {
struct sk_buff_head roc_queue;
struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS];
struct rtw89_tid_stats tid_rx_stats[IEEE80211_NUM_TIDS];
DECLARE_BITMAP(ampdu_map, IEEE80211_NUM_TIDS);
DECLARE_BITMAP(pairwise_sec_cam_map, RTW89_MAX_SEC_CAM_NUM);
@ -6784,22 +6842,18 @@ static inline u32
rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
u32 addr, u32 mask)
{
u32 val;
lockdep_assert_wiphy(rtwdev->hw->wiphy);
mutex_lock(&rtwdev->rf_mutex);
val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask);
mutex_unlock(&rtwdev->rf_mutex);
return val;
return rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask);
}
static inline void
rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
u32 addr, u32 mask, u32 data)
{
mutex_lock(&rtwdev->rf_mutex);
lockdep_assert_wiphy(rtwdev->hw->wiphy);
rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data);
mutex_unlock(&rtwdev->rf_mutex);
}
static inline u32 rtw89_read32_pci_cfg(struct rtw89_dev *rtwdev, u32 addr)
@ -7379,6 +7433,22 @@ void rtw89_chip_calc_rx_gain_normal(struct rtw89_dev *rtwdev,
chip->ops->calc_rx_gain_normal(rtwdev, chan, path, phy_idx, calc);
}
static inline const struct rtw89_fw_def *
__rtw89_chip_get_fw_def(const struct rtw89_chip_info *chip,
const struct rtw89_chip_variant *variant)
{
if (variant && variant->fw_def_override)
return variant->fw_def_override;
return &chip->fw_def;
}
static inline
const struct rtw89_fw_def *rtw89_chip_get_fw_def(struct rtw89_dev *rtwdev)
{
return __rtw89_chip_get_fw_def(rtwdev->chip, rtwdev->variant);
}
static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev,
const struct rtw89_txpwr_table *tbl)
{
@ -7541,6 +7611,7 @@ static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev,
switch (type) {
case RTW89_FW_WOWLAN:
case RTW89_FW_WOWLAN_B:
return &fw_info->wowlan;
case RTW89_FW_LOGFMT:
return &fw_info->log.suit;
@ -7734,6 +7805,9 @@ int rtw89_core_sta_link_remove(struct rtw89_dev *rtwdev,
void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev,
struct ieee80211_sta *sta,
struct cfg80211_tid_config *tid_config);
void rtw89_core_tid_rx_stats_ctrl(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
struct ieee80211_ampdu_params *params, bool enable);
void rtw89_core_tid_rx_stats_reset(struct rtw89_dev *rtwdev);
void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force);
void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks);
int rtw89_core_init(struct rtw89_dev *rtwdev);
@ -7820,5 +7894,8 @@ void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev,
void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event);
int rtw89_core_mlsr_switch(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
unsigned int link_id);
void rtw89_core_dm_disable_cfg(struct rtw89_dev *rtwdev, u32 new);
void rtw89_core_dm_disable_set(struct rtw89_dev *rtwdev, enum rtw89_dm_type type);
void rtw89_core_dm_disable_clr(struct rtw89_dev *rtwdev, enum rtw89_dm_type type);
#endif

53
drivers/net/wireless/realtek/rtw89/debug.c
View File

@ -1129,7 +1129,7 @@ static int rtw89_debug_dump_mac_mem(struct rtw89_dev *rtwdev,
pages = len / mem_page_size + 1;
start_page = start_addr / mem_page_size;
residue = start_addr % mem_page_size;
base_addr = mac->mem_base_addrs[sel];
base_addr = rtw89_mac_mem_base_addrs(rtwdev, sel);
base_addr += start_page * mem_page_size;
for (pp = 0; pp < pages; pp++) {
@ -3552,6 +3552,8 @@ static int rtw89_dbg_trigger_l1_error_by_halt_h2c_be(struct rtw89_dev *rtwdev)
if (!test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags))
return -EBUSY;
rtw89_leave_ps_mode(rtwdev);
rtw89_write32_set(rtwdev, R_BE_FW_TRIGGER_IDCT_ISR,
B_BE_DMAC_FW_TRIG_IDCT | B_BE_DMAC_FW_ERR_IDCT_IMR);
@ -3654,6 +3656,8 @@ static int rtw89_dbg_trigger_l0_error_by_halt_h2c_be(struct rtw89_dev *rtwdev)
if (!test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags))
return -EBUSY;
rtw89_leave_ps_mode(rtwdev);
rtw89_write32_set(rtwdev, R_BE_CMAC_FW_TRIGGER_IDCT_ISR,
B_BE_CMAC_FW_TRIG_IDCT | B_BE_CMAC_FW_ERR_IDCT_IMR);
@ -3781,6 +3785,7 @@ static ssize_t rtw89_debug_priv_ser_counters_get(struct rtw89_dev *rtwdev,
struct rtw89_debugfs_priv *debugfs_priv,
char *buf, size_t bufsz)
{
const struct rtw89_ser_count *sw_cnt = &rtwdev->ser.sw_cnt;
const struct rtw89_chip_info *chip = rtwdev->chip;
struct rtw89_dbg_ser_counters cnt = {};
char *p = buf, *end = buf + bufsz;
@ -3798,6 +3803,11 @@ static ssize_t rtw89_debug_priv_ser_counters_get(struct rtw89_dev *rtwdev,
return -EOPNOTSUPP;
}
p += scnprintf(p, end - p, "SER L1 SW Count: %u\n", sw_cnt->l1);
p += scnprintf(p, end - p, "SER L2 SW Count: %u\n", sw_cnt->l2);
/* Some chipsets won't record SER simulation in HW cnt. */
p += scnprintf(p, end - p, "---\n");
p += scnprintf(p, end - p, "SER L0 Count: %d\n", cnt.l0);
p += scnprintf(p, end - p, "SER L1 Count: %d\n", cnt.l1);
p += scnprintf(p, end - p, "SER L0 promote event: %d\n", cnt.l0_to_l1);
@ -4327,35 +4337,6 @@ static ssize_t rtw89_debug_priv_stations_get(struct rtw89_dev *rtwdev,
return p - buf;
}
static void rtw89_debug_disable_dm_cfg_bmap(struct rtw89_dev *rtwdev, u32 new)
{
struct rtw89_hal *hal = &rtwdev->hal;
u32 old = hal->disabled_dm_bitmap;
if (new == old)
return;
hal->disabled_dm_bitmap = new;
rtw89_debug(rtwdev, RTW89_DBG_STATE, "Disable DM: 0x%x -> 0x%x\n", old, new);
}
static void rtw89_debug_disable_dm_set_flag(struct rtw89_dev *rtwdev, u8 flag)
{
struct rtw89_hal *hal = &rtwdev->hal;
u32 cur = hal->disabled_dm_bitmap;
rtw89_debug_disable_dm_cfg_bmap(rtwdev, cur | BIT(flag));
}
static void rtw89_debug_disable_dm_clr_flag(struct rtw89_dev *rtwdev, u8 flag)
{
struct rtw89_hal *hal = &rtwdev->hal;
u32 cur = hal->disabled_dm_bitmap;
rtw89_debug_disable_dm_cfg_bmap(rtwdev, cur & ~BIT(flag));
}
#define DM_INFO(type) {RTW89_DM_ ## type, #type}
static const struct rtw89_disabled_dm_info {
@ -4406,7 +4387,7 @@ rtw89_debug_priv_disable_dm_set(struct rtw89_dev *rtwdev,
if (ret)
return -EINVAL;
rtw89_debug_disable_dm_cfg_bmap(rtwdev, conf);
rtw89_core_dm_disable_cfg(rtwdev, conf);
return count;
}
@ -4469,7 +4450,7 @@ rtw89_debug_priv_mlo_mode_set(struct rtw89_dev *rtwdev,
if (num != 2)
return -EINVAL;
rtw89_debug_disable_dm_set_flag(rtwdev, RTW89_DM_MLO);
rtw89_core_dm_disable_set(rtwdev, RTW89_DM_MLO);
rtw89_debug(rtwdev, RTW89_DBG_STATE, "Set MLO mode to %x\n", mlo_mode);
@ -4479,7 +4460,7 @@ rtw89_debug_priv_mlo_mode_set(struct rtw89_dev *rtwdev,
break;
default:
rtw89_debug(rtwdev, RTW89_DBG_STATE, "Unsupported MLO mode\n");
rtw89_debug_disable_dm_clr_flag(rtwdev, RTW89_DM_MLO);
rtw89_core_dm_disable_clr(rtwdev, RTW89_DM_MLO);
return -EOPNOTSUPP;
}
@ -4882,9 +4863,9 @@ rtw89_debug_priv_beacon_info_get(struct rtw89_dev *rtwdev,
static const struct rtw89_debugfs rtw89_debugfs_templ = {
.read_reg = rtw89_debug_priv_select_and_get(read_reg),
.write_reg = rtw89_debug_priv_set(write_reg),
.read_rf = rtw89_debug_priv_select_and_get(read_rf),
.write_rf = rtw89_debug_priv_set(write_rf),
.rf_reg_dump = rtw89_debug_priv_get(rf_reg_dump, RSIZE_8K),
.read_rf = rtw89_debug_priv_select_and_get(read_rf, RLOCK),
.write_rf = rtw89_debug_priv_set(write_rf, WLOCK),
.rf_reg_dump = rtw89_debug_priv_get(rf_reg_dump, RSIZE_8K, RLOCK),
.txpwr_table = rtw89_debug_priv_get(txpwr_table, RSIZE_20K, RLOCK),
.mac_reg_dump = rtw89_debug_priv_select_and_get(mac_reg_dump, RSIZE_128K),
.mac_mem_dump = rtw89_debug_priv_select_and_get(mac_mem_dump, RSIZE_16K, RLOCK),

23
drivers/net/wireless/realtek/rtw89/efuse.c
View File

@ -185,8 +185,8 @@ static int rtw89_dump_physical_efuse_map_dav(struct rtw89_dev *rtwdev, u8 *map,
return 0;
}
static int rtw89_dump_physical_efuse_map(struct rtw89_dev *rtwdev, u8 *map,
u32 dump_addr, u32 dump_size, bool dav)
static int __rtw89_dump_physical_efuse_map(struct rtw89_dev *rtwdev, u8 *map,
u32 dump_addr, u32 dump_size, bool dav)
{
int ret;
@ -208,6 +208,25 @@ static int rtw89_dump_physical_efuse_map(struct rtw89_dev *rtwdev, u8 *map,
return 0;
}
static int rtw89_dump_physical_efuse_map(struct rtw89_dev *rtwdev, u8 *map,
u32 dump_addr, u32 dump_size, bool dav)
{
int retry;
int ret;
for (retry = 0; retry < 5; retry++) {
ret = __rtw89_dump_physical_efuse_map(rtwdev, map, dump_addr,
dump_size, dav);
if (!ret)
return 0;
rtw89_warn(rtwdev, "efuse dump (dav=%d) failed, retrying (%d)\n",
dav, retry);
}
return ret;
}
#define invalid_efuse_header(hdr1, hdr2) \
((hdr1) == 0xff || (hdr2) == 0xff)
#define invalid_efuse_content(word_en, i) \

161
drivers/net/wireless/realtek/rtw89/fw.c
View File

@ -730,6 +730,7 @@ static int rtw89_fw_update_ver(struct rtw89_dev *rtwdev,
{
const struct rtw89_fw_hdr *v0 = (const struct rtw89_fw_hdr *)fw_suit->data;
const struct rtw89_fw_hdr_v1 *v1 = (const struct rtw89_fw_hdr_v1 *)fw_suit->data;
struct wiphy *wiphy = rtwdev->hw->wiphy;
if (type == RTW89_FW_LOGFMT)
return 0;
@ -755,6 +756,13 @@ static int rtw89_fw_update_ver(struct rtw89_dev *rtwdev,
fw_suit->major_ver, fw_suit->minor_ver, fw_suit->sub_ver,
fw_suit->sub_idex, fw_suit->commitid, fw_suit->cmd_ver, type);
if (type == RTW89_FW_NORMAL || type == RTW89_FW_NORMAL_CE ||
type == RTW89_FW_NORMAL_B)
snprintf(wiphy->fw_version, sizeof(wiphy->fw_version),
"%u.%u.%u.%u",
fw_suit->major_ver, fw_suit->minor_ver,
fw_suit->sub_ver, fw_suit->sub_idex);
return 0;
}
@ -923,6 +931,7 @@ static const struct __fw_feat_cfg fw_feat_tbl[] = {
__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 84, 0, RFK_PRE_NOTIFY_MCC_V1),
__CFG_FW_FEAT(RTL8922A, lt, 0, 35, 84, 0, ADDR_CAM_V0),
__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 97, 0, SIM_SER_L0L1_BY_HALT_H2C),
__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 100, 0, SER_POST_RECOVER_DMAC),
};
static void rtw89_fw_iterate_feature_cfg(struct rtw89_fw_info *fw,
@ -965,18 +974,20 @@ static void rtw89_fw_recognize_features(struct rtw89_dev *rtwdev)
const struct firmware *
rtw89_early_fw_feature_recognize(struct device *device,
const struct rtw89_chip_info *chip,
const struct rtw89_chip_variant *variant,
struct rtw89_fw_info *early_fw,
int *used_fw_format)
{
const struct rtw89_fw_def *fw_def = __rtw89_chip_get_fw_def(chip, variant);
const struct firmware *firmware;
char fw_name[64];
int fw_format;
u32 ver_code;
int ret;
for (fw_format = chip->fw_format_max; fw_format >= 0; fw_format--) {
for (fw_format = fw_def->fw_format_max; fw_format >= 0; fw_format--) {
rtw89_fw_get_filename(fw_name, sizeof(fw_name),
chip->fw_basename, fw_format);
fw_def->fw_basename, fw_format);
ret = request_firmware(&firmware, fw_name, device);
if (!ret) {
@ -1025,16 +1036,25 @@ static int rtw89_fw_validate_ver_required(struct rtw89_dev *rtwdev)
int rtw89_fw_recognize(struct rtw89_dev *rtwdev)
{
const struct rtw89_fw_def *fw_def = rtw89_chip_get_fw_def(rtwdev);
const struct rtw89_chip_info *chip = rtwdev->chip;
const struct rtw89_hal *hal = &rtwdev->hal;
enum rtw89_fw_type normal_fw_type = RTW89_FW_NORMAL;
enum rtw89_fw_type wowlan_fw_type = RTW89_FW_WOWLAN;
int ret;
if (fw_def->fw_b_aid && fw_def->fw_b_aid == hal->aid) {
normal_fw_type = RTW89_FW_NORMAL_B;
wowlan_fw_type = RTW89_FW_WOWLAN_B;
}
if (chip->try_ce_fw) {
ret = __rtw89_fw_recognize(rtwdev, RTW89_FW_NORMAL_CE, true);
if (!ret)
goto normal_done;
}
ret = __rtw89_fw_recognize(rtwdev, RTW89_FW_NORMAL, false);
ret = __rtw89_fw_recognize(rtwdev, normal_fw_type, false);
if (ret)
return ret;
@ -1044,7 +1064,7 @@ int rtw89_fw_recognize(struct rtw89_dev *rtwdev)
return ret;
/* It still works if wowlan firmware isn't existing. */
__rtw89_fw_recognize(rtwdev, RTW89_FW_WOWLAN, false);
__rtw89_fw_recognize(rtwdev, wowlan_fw_type, false);
/* It still works if log format file isn't existing. */
__rtw89_fw_recognize(rtwdev, RTW89_FW_LOGFMT, true);
@ -1062,6 +1082,7 @@ int rtw89_build_phy_tbl_from_elm(struct rtw89_dev *rtwdev,
const union rtw89_fw_element_arg arg)
{
struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
const struct rtw89_chip_info *chip = rtwdev->chip;
struct rtw89_hal *hal = &rtwdev->hal;
struct rtw89_phy_table *tbl, **pp;
struct rtw89_reg2_def *regs;
@ -1118,7 +1139,9 @@ int rtw89_build_phy_tbl_from_elm(struct rtw89_dev *rtwdev,
if (radio) {
tbl->rf_path = arg.rf_path;
tbl->config = rtw89_phy_config_rf_reg_v1;
tbl->config = chip->chip_id == RTL8852A ?
rtw89_phy_config_rf_reg :
rtw89_phy_config_rf_reg_v1;
}
*pp = tbl;
@ -1138,8 +1161,13 @@ int rtw89_fw_recognize_txpwr_from_elm(struct rtw89_dev *rtwdev,
const struct __rtw89_fw_txpwr_element *txpwr_elm = &elm->u.txpwr;
const unsigned long offset = arg.offset;
struct rtw89_efuse *efuse = &rtwdev->efuse;
struct rtw89_hal *hal = &rtwdev->hal;
u16 aid = le16_to_cpu(elm->aid);
struct rtw89_txpwr_conf *conf;
if (aid && aid != hal->aid)
return 1;
if (!rtwdev->rfe_data) {
rtwdev->rfe_data = kzalloc_obj(*rtwdev->rfe_data);
if (!rtwdev->rfe_data)
@ -2024,11 +2052,11 @@ void rtw89_load_firmware_work(struct work_struct *work)
{
struct rtw89_dev *rtwdev =
container_of(work, struct rtw89_dev, load_firmware_work);
const struct rtw89_chip_info *chip = rtwdev->chip;
const struct rtw89_fw_def *fw_def = rtw89_chip_get_fw_def(rtwdev);
char fw_name[64];
rtw89_fw_get_filename(fw_name, sizeof(fw_name),
chip->fw_basename, rtwdev->fw.fw_format);
fw_def->fw_basename, rtwdev->fw.fw_format);
rtw89_load_firmware_req(rtwdev, &rtwdev->fw.req, fw_name, false);
}
@ -6857,6 +6885,93 @@ int rtw89_fw_h2c_scan_offload_be(struct rtw89_dev *rtwdev,
return 0;
}
int rtw89_fw_h2c_trx_protect(struct rtw89_dev *rtwdev,
enum rtw89_phy_idx phy_idx, bool enable)
{
struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait;
const struct rtw89_chip_info *chip = rtwdev->chip;
struct rtw89_h2c_trx_protect *h2c;
u32 len = sizeof(*h2c);
struct sk_buff *skb;
int ret;
if (chip->chip_gen != RTW89_CHIP_BE)
return 0;
skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len);
if (!skb) {
rtw89_err(rtwdev, "failed to alloc skb for h2c trx protect\n");
return -ENOMEM;
}
skb_put(skb, len);
h2c = (struct rtw89_h2c_trx_protect *)skb->data;
h2c->c0 = le32_encode_bits(BIT(phy_idx), RTW89_H2C_TRX_PROTECT_C0_BAND_BITMAP) |
le32_encode_bits(0, RTW89_H2C_TRX_PROTECT_C0_OP_MODE);
h2c->c1 = le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_C1_RX_IN) |
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_C1_PPDU_STS) |
le32_encode_bits(1, RTW89_H2C_TRX_PROTECT_C1_MSK_RX_IN) |
le32_encode_bits(1, RTW89_H2C_TRX_PROTECT_C1_MSK_PPDU_STS);
h2c->w0 = le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_BE0) |
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_BK0) |
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_VI0) |
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_VO0) |
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_BE1) |
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_BK1) |
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_VI1) |
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_VO1) |
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_MG0) |
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_MG1) |
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_MG2) |
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_HI) |
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_BCN) |
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_UL) |
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_TWT0) |
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_TWT1) |
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_TWT2) |
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_TWT3) |
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_SPEQ0) |
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W0_TXEN_SPEQ1);
h2c->m0 = cpu_to_le32(RTW89_H2C_TRX_PROTECT_W0_TXEN_BE0 |
RTW89_H2C_TRX_PROTECT_W0_TXEN_BK0 |
RTW89_H2C_TRX_PROTECT_W0_TXEN_VI0 |
RTW89_H2C_TRX_PROTECT_W0_TXEN_VO0 |
RTW89_H2C_TRX_PROTECT_W0_TXEN_BE1 |
RTW89_H2C_TRX_PROTECT_W0_TXEN_BK1 |
RTW89_H2C_TRX_PROTECT_W0_TXEN_VI1 |
RTW89_H2C_TRX_PROTECT_W0_TXEN_VO1 |
RTW89_H2C_TRX_PROTECT_W0_TXEN_MG0 |
RTW89_H2C_TRX_PROTECT_W0_TXEN_MG1 |
RTW89_H2C_TRX_PROTECT_W0_TXEN_MG2 |
RTW89_H2C_TRX_PROTECT_W0_TXEN_HI |
RTW89_H2C_TRX_PROTECT_W0_TXEN_BCN |
RTW89_H2C_TRX_PROTECT_W0_TXEN_UL |
RTW89_H2C_TRX_PROTECT_W0_TXEN_TWT0 |
RTW89_H2C_TRX_PROTECT_W0_TXEN_TWT1 |
RTW89_H2C_TRX_PROTECT_W0_TXEN_TWT2 |
RTW89_H2C_TRX_PROTECT_W0_TXEN_TWT3 |
RTW89_H2C_TRX_PROTECT_W0_TXEN_SPEQ0 |
RTW89_H2C_TRX_PROTECT_W0_TXEN_SPEQ1);
h2c->w1 = le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W1_CHINFO_EN) |
le32_encode_bits(enable, RTW89_H2C_TRX_PROTECT_W1_DFS_EN);
h2c->m1 = cpu_to_le32(RTW89_H2C_TRX_PROTECT_W1_CHINFO_EN |
RTW89_H2C_TRX_PROTECT_W1_DFS_EN);
rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
H2C_CAT_MAC, H2C_CL_MAC_FW_OFLD,
H2C_FUNC_TRX_PROTECT, 0, 1, len);
ret = rtw89_h2c_tx_and_wait(rtwdev, skb, wait,
RTW89_FW_OFLD_WAIT_COND_TRX_PROTECT);
if (ret) {
rtw89_debug(rtwdev, RTW89_DBG_FW, "failed to trx protect\n");
return ret;
}
return 0;
}
int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev,
struct rtw89_fw_h2c_rf_reg_info *info,
u16 len, u8 page)
@ -7270,6 +7385,7 @@ int rtw89_fw_h2c_rf_pre_ntfy_mcc(struct rtw89_dev *rtwdev, enum rtw89_phy_idx ph
h2c = (struct rtw89_fw_h2c_rfk_pre_info_mcc *)skb->data;
h2c->aid = cpu_to_le32(hal->aid);
h2c->acv = hal->acv;
done:
rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
@ -9602,38 +9718,49 @@ int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtw
return ret;
}
#define H2C_WAKEUP_CTRL_LEN 4
int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
struct rtw89_vif_link *rtwvif_link,
bool enable)
{
struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
struct rtw89_h2c_wow_wakeup_ctrl *h2c;
struct sk_buff *skb;
u32 len = sizeof(*h2c);
u8 macid = rtwvif_link->mac_id;
int ret;
skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_WAKEUP_CTRL_LEN);
skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len);
if (!skb) {
rtw89_err(rtwdev, "failed to alloc skb for wakeup ctrl\n");
return -ENOMEM;
}
skb_put(skb, H2C_WAKEUP_CTRL_LEN);
skb_put(skb, len);
h2c = (struct rtw89_h2c_wow_wakeup_ctrl *)skb->data;
if (rtw_wow->pattern_cnt)
RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(skb->data, enable);
if (test_bit(RTW89_WOW_FLAG_EN_MAGIC_PKT, rtw_wow->flags))
RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(skb->data, enable);
if (test_bit(RTW89_WOW_FLAG_EN_DISCONNECT, rtw_wow->flags))
RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(skb->data, enable);
h2c->w0 |= le32_encode_bits(enable,
RTW89_H2C_WOW_WAKEUP_CTRL_W0_PATTERN_MATCH_ENABLE);
if (test_bit(RTW89_WOW_FLAG_EN_MAGIC_PKT, rtw_wow->flags)) {
h2c->w0 |= le32_encode_bits(enable,
RTW89_H2C_WOW_WAKEUP_CTRL_W0_MAGIC_ENABLE);
if (ieee80211_vif_is_mld(vif))
h2c->w0 |= le32_encode_bits(enable,
RTW89_H2C_WOW_WAKEUP_CTRL_W0_MAGIC_MLD_ENABLE);
}
RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(skb->data, macid);
if (test_bit(RTW89_WOW_FLAG_EN_DISCONNECT, rtw_wow->flags))
h2c->w0 |= le32_encode_bits(enable,
RTW89_H2C_WOW_WAKEUP_CTRL_W0_DEAUTH_ENABLE);
h2c->w0 |= le32_encode_bits(macid, RTW89_H2C_WOW_WAKEUP_CTRL_W0_MAC_ID);
rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
H2C_CAT_MAC,
H2C_CL_MAC_WOW,
H2C_FUNC_WAKEUP_CTRL, 0, 1,
H2C_WAKEUP_CTRL_LEN);
len);
ret = rtw89_h2c_tx(rtwdev, skb, false);
if (ret) {

134
drivers/net/wireless/realtek/rtw89/fw.h
View File

@ -2219,50 +2219,21 @@ struct rtw89_h2c_cfg_nlo {
#define RTW89_H2C_NLO_W0_IGNORE_CIPHER BIT(2)
#define RTW89_H2C_NLO_W0_MACID GENMASK(31, 24)
static inline void RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(void *h2c, u32 val)
{
le32p_replace_bits((__le32 *)h2c, val, BIT(0));
}
struct rtw89_h2c_wow_wakeup_ctrl {
__le32 w0;
} __packed;
static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(void *h2c, u32 val)
{
le32p_replace_bits((__le32 *)h2c, val, BIT(1));
}
static inline void RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE(void *h2c, u32 val)
{
le32p_replace_bits((__le32 *)h2c, val, BIT(2));
}
static inline void RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE(void *h2c, u32 val)
{
le32p_replace_bits((__le32 *)h2c, val, BIT(3));
}
static inline void RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(void *h2c, u32 val)
{
le32p_replace_bits((__le32 *)h2c, val, BIT(4));
}
static inline void RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE(void *h2c, u32 val)
{
le32p_replace_bits((__le32 *)h2c, val, BIT(5));
}
static inline void RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE(void *h2c, u32 val)
{
le32p_replace_bits((__le32 *)h2c, val, BIT(6));
}
static inline void RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE(void *h2c, u32 val)
{
le32p_replace_bits((__le32 *)h2c, val, BIT(7));
}
static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(void *h2c, u32 val)
{
le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
}
#define RTW89_H2C_WOW_WAKEUP_CTRL_W0_PATTERN_MATCH_ENABLE BIT(0)
#define RTW89_H2C_WOW_WAKEUP_CTRL_W0_MAGIC_ENABLE BIT(1)
#define RTW89_H2C_WOW_WAKEUP_CTRL_W0_HW_UNICAST_ENABLE BIT(2)
#define RTW89_H2C_WOW_WAKEUP_CTRL_W0_FW_UNICAST_ENABLE BIT(3)
#define RTW89_H2C_WOW_WAKEUP_CTRL_W0_DEAUTH_ENABLE BIT(4)
#define RTW89_H2C_WOW_WAKEUP_CTRL_W0_REKEYP_ENABLE BIT(5)
#define RTW89_H2C_WOW_WAKEUP_CTRL_W0_EAP_ENABLE BIT(6)
#define RTW89_H2C_WOW_WAKEUP_CTRL_W0_ALL_DATA_ENABLE BIT(7)
#define RTW89_H2C_WOW_WAKEUP_CTRL_W0_MAGIC_MLD_ENABLE BIT(8)
#define RTW89_H2C_WOW_WAKEUP_CTRL_W0_MAC_ID_EXT GENMASK(23, 16)
#define RTW89_H2C_WOW_WAKEUP_CTRL_W0_MAC_ID GENMASK(31, 24)
struct rtw89_h2c_wow_cam_update {
__le32 w0;
@ -3106,6 +3077,44 @@ struct rtw89_h2c_scanofld_be {
#define RTW89_H2C_SCANOFLD_BE_W9_SIZE_MACC GENMASK(15, 8)
#define RTW89_H2C_SCANOFLD_BE_W9_SIZE_OP GENMASK(23, 16)
struct rtw89_h2c_trx_protect {
__le32 c0;
__le32 c1;
__le32 w0;
__le32 m0;
__le32 w1;
__le32 m1;
} __packed;
#define RTW89_H2C_TRX_PROTECT_C0_BAND_BITMAP GENMASK(2, 0)
#define RTW89_H2C_TRX_PROTECT_C0_OP_MODE GENMASK(4, 3)
#define RTW89_H2C_TRX_PROTECT_C1_RX_IN BIT(0)
#define RTW89_H2C_TRX_PROTECT_C1_PPDU_STS BIT(4)
#define RTW89_H2C_TRX_PROTECT_C1_MSK_RX_IN BIT(16)
#define RTW89_H2C_TRX_PROTECT_C1_MSK_PPDU_STS BIT(20)
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_BE0 BIT(0)
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_BK0 BIT(1)
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_VI0 BIT(2)
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_VO0 BIT(3)
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_BE1 BIT(4)
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_BK1 BIT(5)
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_VI1 BIT(6)
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_VO1 BIT(7)
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_MG0 BIT(8)
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_MG1 BIT(9)
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_MG2 BIT(10)
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_HI BIT(11)
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_BCN BIT(12)
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_UL BIT(13)
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_TWT0 BIT(14)
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_TWT1 BIT(15)
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_TWT2 BIT(16)
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_TWT3 BIT(17)
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_SPEQ0 BIT(18)
#define RTW89_H2C_TRX_PROTECT_W0_TXEN_SPEQ1 BIT(19)
#define RTW89_H2C_TRX_PROTECT_W1_CHINFO_EN BIT(0)
#define RTW89_H2C_TRX_PROTECT_W1_DFS_EN BIT(1)
struct rtw89_h2c_fwips {
__le32 w0;
} __packed;
@ -4289,13 +4298,22 @@ enum rtw89_fw_element_id {
BIT(RTW89_FW_ELEMENT_ID_TXPWR_TRK) | \
BITS_OF_RTW89_TXPWR_FW_ELEMENTS_NO_6GHZ)
#define RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS (BIT(RTW89_FW_ELEMENT_ID_BBMCU0) | \
BIT(RTW89_FW_ELEMENT_ID_BB_REG) | \
BIT(RTW89_FW_ELEMENT_ID_RADIO_A) | \
BIT(RTW89_FW_ELEMENT_ID_RADIO_B) | \
BIT(RTW89_FW_ELEMENT_ID_RF_NCTL) | \
BIT(RTW89_FW_ELEMENT_ID_TXPWR_TRK) | \
BITS_OF_RTW89_TXPWR_FW_ELEMENTS)
#define RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS_BASE \
(BIT(RTW89_FW_ELEMENT_ID_BB_REG) | \
BIT(RTW89_FW_ELEMENT_ID_RADIO_A) | \
BIT(RTW89_FW_ELEMENT_ID_RADIO_B) | \
BIT(RTW89_FW_ELEMENT_ID_RF_NCTL) | \
BIT(RTW89_FW_ELEMENT_ID_TXPWR_TRK) | \
BITS_OF_RTW89_TXPWR_FW_ELEMENTS)
#define RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS \
(RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS_BASE | \
BIT(RTW89_FW_ELEMENT_ID_BBMCU0))
#define RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS_V1 \
(RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS_BASE | \
BIT(RTW89_FW_ELEMENT_ID_AFE_PWR_SEQ) | \
BIT(RTW89_FW_ELEMENT_ID_TX_COMP))
struct __rtw89_fw_txpwr_element {
u8 rsvd0;
@ -4598,6 +4616,7 @@ enum rtw89_fw_ofld_h2c_func {
H2C_FUNC_OFLD_TP = 0x20,
H2C_FUNC_MAC_MACID_PAUSE_SLEEP = 0x28,
H2C_FUNC_SCANOFLD_BE = 0x2c,
H2C_FUNC_TRX_PROTECT = 0x34,
NUM_OF_RTW89_FW_OFLD_H2C_FUNC,
};
@ -4608,6 +4627,7 @@ enum rtw89_fw_ofld_h2c_func {
#define RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op) \
RTW89_FW_OFLD_WAIT_COND(RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op), \
H2C_FUNC_PACKET_OFLD)
#define RTW89_FW_OFLD_WAIT_COND_TRX_PROTECT RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_TRX_PROTECT)
#define RTW89_SCANOFLD_WAIT_COND_ADD_CH RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_ADD_SCANOFLD_CH)
@ -4841,6 +4861,8 @@ struct rtw89_fw_h2c_rfk_pre_info_mcc {
struct rtw89_fw_h2c_rfk_pre_info_mcc_v1 base;
u8 rsvd[2];
__le32 aid;
u8 acv;
u8 rsvd2[3];
} __packed;
struct rtw89_h2c_rf_tssi {
@ -5171,6 +5193,7 @@ int rtw89_fw_recognize_elements(struct rtw89_dev *rtwdev);
const struct firmware *
rtw89_early_fw_feature_recognize(struct device *device,
const struct rtw89_chip_info *chip,
const struct rtw89_chip_variant *variant,
struct rtw89_fw_info *early_fw,
int *used_fw_format);
int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type,
@ -5293,6 +5316,8 @@ int rtw89_fw_h2c_scan_offload_be(struct rtw89_dev *rtwdev,
struct rtw89_scan_option *opt,
struct rtw89_vif_link *vif,
bool wowlan);
int rtw89_fw_h2c_trx_protect(struct rtw89_dev *rtwdev,
enum rtw89_phy_idx phy_idx, bool enable);
int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev,
struct rtw89_fw_h2c_rf_reg_info *info,
u16 len, u8 page);
@ -5468,6 +5493,15 @@ static inline void rtw89_fw_h2c_init_ba_cam(struct rtw89_dev *rtwdev)
rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(rtwdev);
}
static inline void rtw89_fw_h2c_init_trx_protect(struct rtw89_dev *rtwdev)
{
u8 active_bands = rtw89_get_active_phy_bitmap(rtwdev);
int i;
for (i = 0; i < RTW89_PHY_NUM; i++)
rtw89_fw_h2c_trx_protect(rtwdev, i, active_bands & BIT(i));
}
static inline int rtw89_chip_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev,
struct rtw89_vif_link *rtwvif_link,
struct rtw89_sta_link *rtwsta_link)

69
drivers/net/wireless/realtek/rtw89/mac.c
View File

@ -43,7 +43,7 @@ static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset,
u32 val, enum rtw89_mac_mem_sel sel)
{
const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
u32 addr = mac->mem_base_addrs[sel] + offset;
u32 addr = rtw89_mac_mem_base_addrs(rtwdev, sel) + offset;
rtw89_write32(rtwdev, mac->filter_model_addr, addr);
rtw89_write32(rtwdev, mac->indir_access_addr, val);
@ -53,7 +53,7 @@ static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset,
enum rtw89_mac_mem_sel sel)
{
const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
u32 addr = mac->mem_base_addrs[sel] + offset;
u32 addr = rtw89_mac_mem_base_addrs(rtwdev, sel) + offset;
rtw89_write32(rtwdev, mac->filter_model_addr, addr);
return rtw89_read32(rtwdev, mac->indir_access_addr);
@ -814,6 +814,7 @@ static bool rtw89_mac_suppress_log(struct rtw89_dev *rtwdev, u32 err)
u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev)
{
const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
const struct rtw89_chip_info *chip = rtwdev->chip;
u32 err, err_scnr;
int ret;
@ -825,7 +826,9 @@ u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev)
}
err = rtw89_read32(rtwdev, R_AX_HALT_C2H);
rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0);
if (!RTW89_CHK_FW_FEATURE(SER_POST_RECOVER_DMAC, &rtwdev->fw))
rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0);
err_scnr = RTW89_ERROR_SCENARIO(err);
if (err_scnr == RTW89_WCPU_CPU_EXCEPTION)
@ -836,11 +839,18 @@ u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev)
err = MAC_AX_ERR_RXI300;
if (rtw89_mac_suppress_log(rtwdev, err))
return err;
goto bottom;
rtw89_fw_st_dbg_dump(rtwdev);
mac->dump_err_status(rtwdev, err);
bottom:
if (chip->chip_gen != RTW89_CHIP_AX)
rtw89_write32(rtwdev, R_AX_HALT_C2H, 0);
if (RTW89_CHK_FW_FEATURE(SER_POST_RECOVER_DMAC, &rtwdev->fw))
rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0);
return err;
}
EXPORT_SYMBOL(rtw89_mac_get_err_status);
@ -1729,8 +1739,8 @@ const struct rtw89_mac_size_set rtw89_mac_size = {
/* 8852C PCIE SCC */
.wde_size19 = {RTW89_WDE_PG_64, 3328, 0,},
.wde_size23 = {RTW89_WDE_PG_64, 1022, 2,},
/* 8852B USB2.0/USB3.0 SCC */
.wde_size25 = {RTW89_WDE_PG_64, 162, 94,},
/* 8852B USB2.0/USB3.0 SCC turbo */
.wde_size30 = {RTW89_WDE_PG_64, 220, 36,},
/* 8852C USB2.0 */
.wde_size31 = {RTW89_WDE_PG_64, 384, 0,},
/* PCIE */
@ -1754,10 +1764,10 @@ const struct rtw89_mac_size_set rtw89_mac_size = {
.ple_size19 = {RTW89_PLE_PG_128, 1904, 16,},
.ple_size20_v1 = {RTW89_PLE_PG_128, 2554, 182, 40960,},
.ple_size22_v1 = {RTW89_PLE_PG_128, 2736, 0, 40960,},
/* 8852B USB2.0 SCC */
.ple_size32 = {RTW89_PLE_PG_128, 620, 20,},
/* 8852B USB3.0 SCC */
.ple_size33 = {RTW89_PLE_PG_128, 632, 8,},
/* 8851B USB2.0 SCC turbo */
.ple_size27 = {RTW89_PLE_PG_128, 1396, 12,},
/* 8852B USB3.0 SCC turbo */
.ple_size31 = {RTW89_PLE_PG_128, 1392, 16,},
/* 8852C USB2.0 */
.ple_size34 = {RTW89_PLE_PG_128, 3374, 18,},
/* PCIE 64 */
@ -1780,8 +1790,8 @@ const struct rtw89_mac_size_set rtw89_mac_size = {
.wde_qt18 = {3228, 60, 0, 40,},
.wde_qt19_v1 = {613, 6, 0, 20,},
.wde_qt23 = {958, 48, 0, 16,},
/* 8852B USB2.0/USB3.0 SCC */
.wde_qt25 = {152, 2, 0, 8,},
/* 8852B USB2.0/USB3.0 SCC turbo */
.wde_qt30 = {210, 2, 0, 8,},
/* 8852C USB2.0 */
.wde_qt31 = {338, 6, 0, 40,},
.ple_qt0 = {320, 320, 32, 16, 13, 13, 292, 292, 64, 18, 1, 4, 0,},
@ -1799,6 +1809,9 @@ const struct rtw89_mac_size_set rtw89_mac_size = {
/* 8852A USB SCC */
.ple_qt25 = {1536, 0, 16, 48, 13, 13, 360, 0, 32, 40, 8, 0,},
.ple_qt26 = {2654, 0, 1134, 48, 64, 13, 1478, 0, 64, 128, 120, 0,},
/* 8852B USB3.0 SCC turbo */
.ple_qt27 = {1040, 0, 16, 48, 13, 13, 178, 0, 32, 14, 8, 0,},
.ple_qt28 = {1040, 0, 32, 48, 43, 13, 208, 0, 62, 14, 24, 0,},
/* USB 52C USB3.0 */
.ple_qt42 = {1068, 0, 16, 48, 4, 13, 178, 0, 16, 1, 8, 16, 0,},
.ple_qt42_v2 = {91, 91, 32, 16, 19, 13, 91, 91, 44, 18, 1, 4, 0, 0,},
@ -1817,13 +1830,9 @@ const struct rtw89_mac_size_set rtw89_mac_size = {
/* PCIE 64 */
.ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,},
.ple_qt59 = {147, 0, 32, 20, 1860, 13, 2025, 0, 1879, 14, 24, 0,},
/* USB2.0 52B SCC */
.ple_qt72 = {130, 0, 16, 48, 4, 13, 322, 0, 32, 14, 8, 0, 0,},
/* USB2.0 52B 92K */
.ple_qt73 = {130, 0, 32, 48, 37, 13, 355, 0, 65, 14, 24, 0, 0,},
/* USB3.0 52B 92K */
.ple_qt74 = {286, 0, 16, 48, 4, 13, 178, 0, 32, 14, 8, 0, 0,},
.ple_qt75 = {286, 0, 32, 48, 37, 13, 211, 0, 65, 14, 24, 0, 0,},
/* 8851B USB2.0 SCC turbo */
.ple_qt61 = {858, 0, 16, 48, 4, 13, 370, 0, 32, 14, 8, 0, 0,},
.ple_qt62 = {858, 0, 32, 48, 37, 13, 403, 0, 65, 14, 24, 0, 0,},
/* USB2.0 52C */
.ple_qt78 = {1560, 0, 16, 48, 13, 13, 390, 0, 32, 38, 8, 16, 0,},
/* USB2.0 52C */
@ -2004,7 +2013,7 @@ static u32 dle_expected_used_size(struct rtw89_dev *rtwdev,
{
u32 size = rtwdev->chip->fifo_size;
if (mode == RTW89_QTA_SCC)
if (mode == RTW89_QTA_SCC && rtwdev->hci.type != RTW89_HCI_TYPE_USB)
size -= rtwdev->chip->dle_scc_rsvd_size;
return size;
@ -5412,6 +5421,9 @@ rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 le
cond = RTW89_SCANOFLD_BE_WAIT_COND_START;
h2c_return &= RTW89_C2H_SCAN_DONE_ACK_RETURN;
break;
case H2C_FUNC_TRX_PROTECT:
cond = RTW89_FW_OFLD_WAIT_COND_TRX_PROTECT;
break;
}
data.err = !!h2c_return;
@ -7171,7 +7183,7 @@ int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev,
return ret;
}
int rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable)
static int _rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable)
{
struct rtw89_mac_h2c_info h2c_info = {};
struct rtw89_mac_c2h_info c2h_info = {};
@ -7194,6 +7206,19 @@ int rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable)
return ret;
}
int rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable)
{
int i, ret;
for (i = 0; i < CPU_IO_RX_RETRY_CNT; i++) {
ret = _rtw89_mac_cpu_io_rx(rtwdev, wow_enable);
if (!ret)
return 0;
}
return ret;
}
static int rtw89_wow_config_mac_ax(struct rtw89_dev *rtwdev, bool enable_wow)
{
const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
@ -7307,6 +7332,8 @@ const struct rtw89_mac_gen_def rtw89_mac_gen_ax = {
},
.wow_ctrl = {.addr = R_AX_WOW_CTRL, .mask = B_AX_WOW_WOWEN,},
.agg_limit = {.addr = R_AX_AMPDU_AGG_LIMIT, .mask = B_AX_AMPDU_MAX_TIME_MASK,},
.ra_agg_limit = {.addr = R_AX_AMPDU_AGG_LIMIT,
.mask = B_AX_RA_TRY_RATE_AGG_LMT_MASK,},
.txcnt_limit = {.addr = R_AX_TXCNT, .mask = B_AX_L_TXCNT_LMT_MASK,},
.check_mac_en = rtw89_mac_check_mac_en_ax,

34
drivers/net/wireless/realtek/rtw89/mac.h
View File

@ -17,6 +17,7 @@
#define BSSID_CAM_ENT_SIZE 0x08
#define HFC_PAGE_UNIT 64
#define RPWM_TRY_CNT 3
#define CPU_IO_RX_RETRY_CNT 3
enum rtw89_mac_hwmod_sel {
RTW89_DMAC_SEL = 0,
@ -333,6 +334,7 @@ enum rtw89_mac_dbg_port_sel {
#define NAT25_CAM_BASE_ADDR_BE 0x18820000
#define RXPLD_FLTR_CAM_BASE_ADDR_BE 0x18823000
#define SEC_CAM_BASE_ADDR_BE 0x18824000
#define SEC_CAM_BASE_ADDR_BE_8922D 0x1882C000
#define WOW_CAM_BASE_ADDR_BE 0x18828000
#define MLD_TBL_BASE_ADDR_BE 0x18829000
#define RX_CLSF_CAM_BASE_ADDR_BE 0x1882A000
@ -938,7 +940,7 @@ struct rtw89_mac_size_set {
const struct rtw89_dle_size wde_size18_v1;
const struct rtw89_dle_size wde_size19;
const struct rtw89_dle_size wde_size23;
const struct rtw89_dle_size wde_size25;
const struct rtw89_dle_size wde_size30;
const struct rtw89_dle_size wde_size31;
const struct rtw89_dle_size ple_size0;
const struct rtw89_dle_size ple_size1;
@ -953,8 +955,8 @@ struct rtw89_mac_size_set {
const struct rtw89_dle_size ple_size19;
const struct rtw89_dle_size ple_size20_v1;
const struct rtw89_dle_size ple_size22_v1;
const struct rtw89_dle_size ple_size32;
const struct rtw89_dle_size ple_size33;
const struct rtw89_dle_size ple_size27;
const struct rtw89_dle_size ple_size31;
const struct rtw89_dle_size ple_size34;
const struct rtw89_wde_quota wde_qt0;
const struct rtw89_wde_quota wde_qt1;
@ -968,7 +970,7 @@ struct rtw89_mac_size_set {
const struct rtw89_wde_quota wde_qt18;
const struct rtw89_wde_quota wde_qt19_v1;
const struct rtw89_wde_quota wde_qt23;
const struct rtw89_wde_quota wde_qt25;
const struct rtw89_wde_quota wde_qt30;
const struct rtw89_wde_quota wde_qt31;
const struct rtw89_ple_quota ple_qt0;
const struct rtw89_ple_quota ple_qt1;
@ -980,6 +982,8 @@ struct rtw89_mac_size_set {
const struct rtw89_ple_quota ple_qt18;
const struct rtw89_ple_quota ple_qt25;
const struct rtw89_ple_quota ple_qt26;
const struct rtw89_ple_quota ple_qt27;
const struct rtw89_ple_quota ple_qt28;
const struct rtw89_ple_quota ple_qt42;
const struct rtw89_ple_quota ple_qt42_v2;
const struct rtw89_ple_quota ple_qt43;
@ -991,10 +995,8 @@ struct rtw89_mac_size_set {
const struct rtw89_ple_quota ple_qt57;
const struct rtw89_ple_quota ple_qt58;
const struct rtw89_ple_quota ple_qt59;
const struct rtw89_ple_quota ple_qt72;
const struct rtw89_ple_quota ple_qt73;
const struct rtw89_ple_quota ple_qt74;
const struct rtw89_ple_quota ple_qt75;
const struct rtw89_ple_quota ple_qt61;
const struct rtw89_ple_quota ple_qt62;
const struct rtw89_ple_quota ple_qt78;
const struct rtw89_ple_quota ple_qt79;
const struct rtw89_ple_quota ple_qt_52a_wow;
@ -1037,6 +1039,7 @@ struct rtw89_mac_gen_def {
struct rtw89_reg_def narrow_bw_ru_dis;
struct rtw89_reg_def wow_ctrl;
struct rtw89_reg_def agg_limit;
struct rtw89_reg_def ra_agg_limit;
struct rtw89_reg_def txcnt_limit;
int (*check_mac_en)(struct rtw89_dev *rtwdev, u8 band,
@ -1129,6 +1132,18 @@ struct rtw89_mac_gen_def {
extern const struct rtw89_mac_gen_def rtw89_mac_gen_ax;
extern const struct rtw89_mac_gen_def rtw89_mac_gen_be;
static inline
u32 rtw89_mac_mem_base_addrs(struct rtw89_dev *rtwdev, u8 sel)
{
const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
if (rtwdev->chip->chip_id == RTL8922D &&
sel == RTW89_MAC_MEM_SECURITY_CAM)
return SEC_CAM_BASE_ADDR_BE_8922D;
return mac->mem_base_addrs[sel];
}
static inline
u32 rtw89_mac_reg_by_idx(struct rtw89_dev *rtwdev, u32 reg_base, u8 band)
{
@ -1813,8 +1828,7 @@ static inline bool rtw89_mac_chk_preload_allow(struct rtw89_dev *rtwdev)
if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE)
return false;
if (rtwdev->chip->chip_id == RTL8922D && rtwdev->hal.cid == RTL8922D_CID7090)
return true;
/* The RTL8922DE will re-enable pre-load function after verification. */
return false;
}

11
drivers/net/wireless/realtek/rtw89/mac80211.c
View File

@ -528,6 +528,8 @@ static int __rtw89_ops_sta_add(struct rtw89_dev *rtwdev,
if (vif->type == NL80211_IFTYPE_AP || sta->tdls)
rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_REMOTE_STA_CHANGE);
rtw89_fw_h2c_init_trx_protect(rtwdev);
return 0;
unset_link:
@ -962,6 +964,7 @@ static int rtw89_ops_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
rtw89_err(rtwdev, "failed to add key to sec cam\n");
return ret;
}
rtw89_core_tid_rx_stats_reset(rtwdev);
break;
case DISABLE_KEY:
flush_work(&rtwdev->txq_work);
@ -1003,6 +1006,8 @@ static int rtw89_ops_ampdu_action(struct ieee80211_hw *hw,
clear_bit(tid, rtwsta->ampdu_map);
rtw89_chip_h2c_ampdu_cmac_tbl(rtwdev, rtwvif, rtwsta);
ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
rtw89_leave_ps_mode(rtwdev);
rtw89_phy_ra_recalc_agg_limit(rtwdev);
break;
case IEEE80211_AMPDU_TX_OPERATIONAL:
set_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags);
@ -1011,11 +1016,14 @@ static int rtw89_ops_ampdu_action(struct ieee80211_hw *hw,
set_bit(tid, rtwsta->ampdu_map);
rtw89_leave_ps_mode(rtwdev);
rtw89_chip_h2c_ampdu_cmac_tbl(rtwdev, rtwvif, rtwsta);
rtw89_phy_ra_recalc_agg_limit(rtwdev);
break;
case IEEE80211_AMPDU_RX_START:
rtw89_core_tid_rx_stats_ctrl(rtwdev, rtwsta, params, true);
rtw89_chip_h2c_ba_cam(rtwdev, rtwsta, true, params);
break;
case IEEE80211_AMPDU_RX_STOP:
rtw89_core_tid_rx_stats_ctrl(rtwdev, rtwsta, params, false);
rtw89_chip_h2c_ba_cam(rtwdev, rtwsta, false, params);
break;
default:
@ -1584,6 +1592,8 @@ static void __rtw89_ops_clr_vif_links(struct rtw89_dev *rtwdev,
if (unlikely(!rtwvif_link))
continue;
rtw89_fw_h2c_trx_protect(rtwdev, rtwvif_link->phy_idx, false);
__rtw89_ops_remove_iface_link(rtwdev, rtwvif_link);
rtw89_vif_unset_link(rtwvif, link_id);
@ -1609,6 +1619,7 @@ static int __rtw89_ops_set_vif_links(struct rtw89_dev *rtwdev,
__func__, link_id);
return ret;
}
rtw89_fw_h2c_trx_protect(rtwdev, rtwvif_link->phy_idx, true);
}
return 0;

2
drivers/net/wireless/realtek/rtw89/mac_be.c
View File

@ -3193,6 +3193,8 @@ const struct rtw89_mac_gen_def rtw89_mac_gen_be = {
},
.wow_ctrl = {.addr = R_BE_WOW_CTRL, .mask = B_BE_WOW_WOWEN,},
.agg_limit = {.addr = R_BE_AMPDU_AGG_LIMIT, .mask = B_BE_AMPDU_MAX_TIME_MASK,},
.ra_agg_limit = {.addr = R_BE_AMPDU_AGG_LIMIT,
.mask = B_BE_RA_TRY_RATE_AGG_LMT_MASK,},
.txcnt_limit = {.addr = R_BE_TXCNT, .mask = B_BE_L_TXCNT_LMT_MASK,},
.check_mac_en = rtw89_mac_check_mac_en_be,

7
drivers/net/wireless/realtek/rtw89/pci.h
View File

@ -55,6 +55,8 @@
#define B_AX_CALIB_EN BIT(13)
#define B_AX_DIV GENMASK(15, 14)
#define RAC_SET_PPR_V1 0x31
#define RAC_ANA40 0x40
#define PHY_ERR_IMR_DIS (BIT(9) | BIT(0))
#define RAC_ANA41 0x41
#define PHY_ERR_FLAG_EN BIT(6)
@ -1016,6 +1018,7 @@
#define B_BE_PL1_IGNORE_HOT_RST BIT(30)
#define B_BE_PL1_TIMER_UNIT_MASK GENMASK(19, 17)
#define PCIE_SER_TIMER_UNIT 0x2
#define PCIE_SER_WOW_TIMER_UNIT 0x4
#define B_BE_PL1_TIMER_CLEAR BIT(0)
#define R_BE_REG_PL1_MASK 0x34B0
@ -1028,6 +1031,7 @@
#define B_BE_SER_PMU_IMR BIT(0)
#define R_BE_REG_PL1_ISR 0x34B4
#define B_PCIE_SER_ALL_ISR 0x7F
#define R_BE_RX_APPEND_MODE 0x8920
#define B_BE_APPEND_OFFSET_MASK GENMASK(23, 16)
@ -1101,6 +1105,9 @@
B_BE_CH6_BUSY | B_BE_CH7_BUSY | B_BE_CH8_BUSY | \
B_BE_CH9_BUSY | B_BE_CH10_BUSY | B_BE_CH11_BUSY | \
B_BE_CH12_BUSY | B_BE_CH13_BUSY | B_BE_CH14_BUSY)
#define DMA_BUSY1_CHECK_BE_V1 (B_BE_CH0_BUSY | B_BE_CH2_BUSY | B_BE_CH4_BUSY | \
B_BE_CH6_BUSY | B_BE_CH8_BUSY | B_BE_CH10_BUSY | \
B_BE_CH12_BUSY)
#define R_BE_HAXI_EXP_CTRL_V1 0xB020
#define B_BE_R_NO_SEC_ACCESS BIT(31)

104
drivers/net/wireless/realtek/rtw89/pci_be.c
View File

@ -351,14 +351,41 @@ static void rtw89_pci_ser_setting_be(struct rtw89_dev *rtwdev)
return;
rtw89_write32(rtwdev, R_BE_PL1_DBG_INFO, 0x0);
rtw89_write32_set(rtwdev, R_BE_FWS1IMR, B_BE_PCIE_SER_TIMEOUT_INDIC_EN);
rtw89_write32_set(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_SER_PL1_EN);
rtw89_write32_mask(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_TIMER_UNIT_MASK, 1);
val32 = rtw89_read32(rtwdev, R_BE_REG_PL1_MASK);
val32 |= B_BE_SER_PMU_IMR | B_BE_SER_L1SUB_IMR | B_BE_SER_PM_MASTER_IMR |
B_BE_SER_LTSSM_IMR | B_BE_SER_PM_CLK_MASK | B_BE_SER_PCLKREQ_ACK_MASK;
rtw89_write32(rtwdev, R_BE_REG_PL1_MASK, val32);
switch (hal->cv) {
case CHIP_CAV:
case CHIP_CBV:
rtw89_write32_clr(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_SER_PL1_EN);
rtw89_write32_mask(rtwdev, R_BE_SER_PL1_CTRL,
B_BE_PL1_TIMER_UNIT_MASK, PCIE_SER_TIMER_UNIT);
val32 = rtw89_read32(rtwdev, R_BE_REG_PL1_MASK);
val32 &= ~(B_BE_SER_PMU_IMR | B_BE_SER_L1SUB_IMR |
B_BE_SER_PM_MASTER_IMR | B_BE_SER_LTSSM_IMR |
B_BE_SER_PM_CLK_MASK | B_BE_SER_PCLKREQ_ACK_MASK);
rtw89_write32(rtwdev, R_BE_REG_PL1_MASK, val32);
break;
case CHIP_CCV:
default:
rtw89_write32_clr(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_SER_PL1_EN);
ret = read_poll_timeout_atomic(rtw89_read32, val32, !val32,
1, 1000, false, rtwdev, R_BE_REG_PL1_ISR);
if (ret)
rtw89_warn(rtwdev, "[ERR] PCIE SER clear poll fail\n");
rtw89_write32_mask(rtwdev, R_BE_SER_PL1_CTRL,
B_BE_PL1_TIMER_UNIT_MASK, PCIE_SER_TIMER_UNIT);
rtw89_write32_set(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_SER_PL1_EN);
val32 = rtw89_read32(rtwdev, R_BE_REG_PL1_MASK);
val32 |= (B_BE_SER_PMU_IMR | B_BE_SER_PM_MASTER_IMR |
B_BE_SER_LTSSM_IMR | B_BE_SER_PM_CLK_MASK |
B_BE_SER_PCLKREQ_ACK_MASK);
val32 &= ~B_BE_SER_L1SUB_IMR;
rtw89_write32(rtwdev, R_BE_REG_PL1_MASK, val32);
break;
}
return;
@ -366,6 +393,11 @@ static void rtw89_pci_ser_setting_be(struct rtw89_dev *rtwdev)
rtw89_write32_clr(rtwdev, R_BE_PCIE_SER_DBG, B_BE_PCIE_SER_FLUSH_RSTB);
rtw89_write32_set(rtwdev, R_BE_PCIE_SER_DBG, B_BE_PCIE_SER_FLUSH_RSTB);
rtw89_write16_clr(rtwdev, RAC_DIRECT_OFFESET_L0_G1 +
RAC_ANA40 * RAC_MULT, PHY_ERR_IMR_DIS);
rtw89_write16_clr(rtwdev, RAC_DIRECT_OFFESET_L0_G2 +
RAC_ANA40 * RAC_MULT, PHY_ERR_IMR_DIS);
rtw89_write16_clr(rtwdev, RAC_DIRECT_OFFESET_L0_G1 +
RAC_ANA41 * RAC_MULT, PHY_ERR_FLAG_EN);
rtw89_write16_clr(rtwdev, RAC_DIRECT_OFFESET_L0_G2 +
@ -378,6 +410,7 @@ static void rtw89_pci_ser_setting_be(struct rtw89_dev *rtwdev)
val32 = rtw89_read32(rtwdev, R_BE_SER_PL1_CTRL);
val32 &= ~B_BE_PL1_SER_PL1_EN;
rtw89_write32(rtwdev, R_BE_SER_PL1_CTRL, val32);
rtw89_write32(rtwdev, R_BE_REG_PL1_ISR, B_PCIE_SER_ALL_ISR);
ret = read_poll_timeout_atomic(rtw89_read32, val32, !val32,
1, 1000, false, rtwdev, R_BE_REG_PL1_ISR);
@ -385,9 +418,10 @@ static void rtw89_pci_ser_setting_be(struct rtw89_dev *rtwdev)
rtw89_warn(rtwdev, "[ERR] PCIE SER clear poll fail\n");
val32 = rtw89_read32(rtwdev, R_BE_REG_PL1_MASK);
val32 |= B_BE_SER_PMU_IMR | B_BE_SER_L1SUB_IMR | B_BE_SER_PM_MASTER_IMR |
val32 |= B_BE_SER_PMU_IMR | B_BE_SER_PM_MASTER_IMR |
B_BE_SER_LTSSM_IMR | B_BE_SER_PM_CLK_MASK | B_BE_SER_PCLKREQ_ACK_MASK |
B_BE_SER_LTSSM_UNSTABLE_MASK;
val32 &= ~B_BE_SER_L1SUB_IMR;
rtw89_write32(rtwdev, R_BE_REG_PL1_MASK, val32);
rtw89_write32_mask(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_TIMER_UNIT_MASK,
@ -721,12 +755,24 @@ static int __maybe_unused rtw89_pci_suspend_be(struct device *dev)
{
struct ieee80211_hw *hw = dev_get_drvdata(dev);
struct rtw89_dev *rtwdev = hw->priv;
u32 val32;
rtw89_write32_set(rtwdev, R_BE_RSV_CTRL, B_BE_WLOCK_1C_BIT6);
rtw89_write32_set(rtwdev, R_BE_RSV_CTRL, B_BE_R_DIS_PRST);
rtw89_write32_clr(rtwdev, R_BE_RSV_CTRL, B_BE_WLOCK_1C_BIT6);
rtw89_write32_set(rtwdev, R_BE_PCIE_FRZ_CLK, B_BE_PCIE_FRZ_REG_RST);
rtw89_write32_clr(rtwdev, R_BE_REG_PL1_MASK, B_BE_SER_PM_MASTER_IMR);
val32 = rtw89_read32(rtwdev, R_BE_SER_PL1_CTRL);
if (val32 & B_BE_PL1_SER_PL1_EN) {
val32 = u32_replace_bits(val32, PCIE_SER_WOW_TIMER_UNIT,
B_BE_PL1_TIMER_UNIT_MASK);
rtw89_write32(rtwdev, R_BE_SER_PL1_CTRL, val32);
if (rtwdev->chip->chip_id == RTL8922A)
rtw89_write32_clr(rtwdev, R_BE_REG_PL1_MASK,
B_BE_SER_PM_MASTER_IMR);
}
return 0;
}
@ -735,21 +781,57 @@ static int __maybe_unused rtw89_pci_resume_be(struct device *dev)
struct ieee80211_hw *hw = dev_get_drvdata(dev);
struct rtw89_dev *rtwdev = hw->priv;
u32 polling;
u32 val32;
u16 val16;
int ret;
rtw89_write32_set(rtwdev, R_BE_RSV_CTRL, B_BE_WLOCK_1C_BIT6);
rtw89_write32_clr(rtwdev, R_BE_RSV_CTRL, B_BE_R_DIS_PRST);
rtw89_write32_clr(rtwdev, R_BE_RSV_CTRL, B_BE_WLOCK_1C_BIT6);
rtw89_write32_clr(rtwdev, R_BE_PCIE_FRZ_CLK, B_BE_PCIE_FRZ_REG_RST);
val32 = rtw89_read32(rtwdev, R_BE_SER_PL1_CTRL);
if (!(val32 & B_BE_PL1_SER_PL1_EN))
goto clear_phy_isr;
rtw89_write32_clr(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_SER_PL1_EN);
if (rtwdev->chip->chip_id == RTL8922D)
rtw89_write32(rtwdev, R_BE_REG_PL1_ISR, B_PCIE_SER_ALL_ISR);
ret = read_poll_timeout_atomic(rtw89_read32, polling, !polling, 1, 1000,
false, rtwdev, R_BE_REG_PL1_ISR);
if (ret)
rtw89_warn(rtwdev, "[ERR] PCIE SER clear polling fail\n");
rtw89_write32_set(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_SER_PL1_EN);
rtw89_write32_set(rtwdev, R_BE_REG_PL1_MASK, B_BE_SER_PM_MASTER_IMR);
if (rtwdev->chip->chip_id == RTL8922A)
rtw89_write32_set(rtwdev, R_BE_REG_PL1_MASK,
B_BE_SER_PM_MASTER_IMR | B_BE_SER_PCLKREQ_ACK_MASK);
val32 = rtw89_read32(rtwdev, R_BE_SER_PL1_CTRL);
val32 = u32_replace_bits(val32, PCIE_SER_TIMER_UNIT, B_BE_PL1_TIMER_UNIT_MASK);
val32 |= B_BE_PL1_SER_PL1_EN;
rtw89_write32(rtwdev, R_BE_SER_PL1_CTRL, val32);
clear_phy_isr:
if (rtwdev->chip->chip_id == RTL8922D) {
val16 = rtw89_read16(rtwdev, RAC_DIRECT_OFFESET_L0_G2 +
RAC_ANA41 * RAC_MULT);
if (val16 & PHY_ERR_FLAG_EN) {
rtw89_write16_clr(rtwdev, RAC_DIRECT_OFFESET_L0_G2 +
RAC_ANA41 * RAC_MULT, PHY_ERR_FLAG_EN);
rtw89_write16_set(rtwdev, RAC_DIRECT_OFFESET_L0_G2 +
RAC_ANA41 * RAC_MULT, PHY_ERR_FLAG_EN);
}
val16 = rtw89_read16(rtwdev, RAC_DIRECT_OFFESET_L0_G1 +
RAC_ANA41 * RAC_MULT);
if (val16 & PHY_ERR_FLAG_EN) {
rtw89_write16_clr(rtwdev, RAC_DIRECT_OFFESET_L0_G1 +
RAC_ANA41 * RAC_MULT, PHY_ERR_FLAG_EN);
rtw89_write16_set(rtwdev, RAC_DIRECT_OFFESET_L0_G1 +
RAC_ANA41 * RAC_MULT, PHY_ERR_FLAG_EN);
}
}
rtw89_pci_basic_cfg(rtwdev, true);

71
drivers/net/wireless/realtek/rtw89/phy.c
View File

@ -775,6 +775,33 @@ void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_
rtw89_fw_h2c_ra(rtwdev, ra, csi);
}
void rtw89_phy_ra_recalc_agg_limit(struct rtw89_dev *rtwdev)
{
const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
const struct rtw89_reg_def *ra_limit = &mac->ra_agg_limit;
struct ieee80211_sta *sta;
struct rtw89_sta *rtwsta;
u16 agg_num = U16_MAX;
u8 tid;
for_each_station(sta, rtwdev->hw) {
rtwsta = sta_to_rtwsta(sta);
for_each_set_bit(tid, rtwsta->ampdu_map, IEEE80211_NUM_TIDS)
agg_num = min(agg_num, rtwsta->ampdu_params[tid].agg_num);
}
if (agg_num == U16_MAX)
agg_num = 0x3F;
else
agg_num = clamp(agg_num, 1, 256) - 1;
rtw89_write32_idx(rtwdev, ra_limit->addr, ra_limit->mask, agg_num, RTW89_MAC_0);
if (!rtwdev->dbcc_en)
return;
rtw89_write32_idx(rtwdev, ra_limit->addr, ra_limit->mask, agg_num, RTW89_MAC_1);
}
u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan,
enum rtw89_bandwidth dbw)
@ -1659,10 +1686,10 @@ static void rtw89_phy_config_rf_reg_noio(struct rtw89_dev *rtwdev,
(struct rtw89_fw_h2c_rf_reg_info *)extra_data);
}
static void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev,
const struct rtw89_reg2_def *reg,
enum rtw89_rf_path rf_path,
void *extra_data)
void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev,
const struct rtw89_reg2_def *reg,
enum rtw89_rf_path rf_path,
void *extra_data)
{
if (reg->addr == 0xfe) {
mdelay(50);
@ -1781,7 +1808,7 @@ static int rtw89_phy_sel_headline(struct rtw89_dev *rtwdev,
}
static void rtw89_phy_init_reg(struct rtw89_dev *rtwdev,
const struct rtw89_phy_table *table,
const struct rtw89_phy_table *table, bool by_acv,
void (*config)(struct rtw89_dev *rtwdev,
const struct rtw89_reg2_def *reg,
enum rtw89_rf_path rf_path,
@ -1790,8 +1817,8 @@ static void rtw89_phy_init_reg(struct rtw89_dev *rtwdev,
{
const struct rtw89_reg2_def *reg;
enum rtw89_rf_path rf_path = table->rf_path;
u8 cv = by_acv ? rtwdev->hal.acv : rtwdev->hal.cv;
u8 rfe = rtwdev->efuse.rfe_type;
u8 cv = rtwdev->hal.cv;
u32 i;
u32 headline_size = 0, headline_idx = 0;
u32 target = 0, cfg_target;
@ -1858,16 +1885,16 @@ void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev)
const struct rtw89_phy_table *bb_gain_table;
bb_table = elm_info->bb_tbl ? elm_info->bb_tbl : chip->bb_table;
rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, NULL);
rtw89_phy_init_reg(rtwdev, bb_table, false, rtw89_phy_config_bb_reg, NULL);
if (rtwdev->dbcc_en)
rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg,
rtw89_phy_init_reg(rtwdev, bb_table, false, rtw89_phy_config_bb_reg,
(void *)RTW89_PHY_1);
rtw89_chip_init_txpwr_unit(rtwdev);
bb_gain_table = elm_info->bb_gain ? elm_info->bb_gain : chip->bb_gain_table;
if (bb_gain_table)
rtw89_phy_init_reg(rtwdev, bb_gain_table,
rtw89_phy_init_reg(rtwdev, bb_gain_table, false,
chip->phy_def->config_bb_gain, NULL);
rtw89_phy_bb_reset(rtwdev);
@ -1973,6 +2000,7 @@ void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio)
const struct rtw89_chip_info *chip = rtwdev->chip;
const struct rtw89_phy_table *rf_table;
struct rtw89_fw_h2c_rf_reg_info *rf_reg_info;
bool by_acv = chip->chip_id == RTL8922D;
u8 path;
rf_reg_info = kzalloc_obj(*rf_reg_info);
@ -1988,7 +2016,7 @@ void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio)
else
config = rf_table->config ? rf_table->config :
rtw89_phy_config_rf_reg;
rtw89_phy_init_reg(rtwdev, rf_table, config, (void *)rf_reg_info);
rtw89_phy_init_reg(rtwdev, rf_table, by_acv, config, (void *)rf_reg_info);
if (rtw89_phy_config_rf_reg_fw(rtwdev, rf_reg_info))
rtw89_warn(rtwdev, "rf path %d reg h2c config failed\n",
rf_reg_info->rf_path);
@ -2029,7 +2057,7 @@ static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev)
rtw89_phy_preinit_rf_nctl(rtwdev);
nctl_table = elm_info->rf_nctl ? elm_info->rf_nctl : chip->nctl_table;
rtw89_phy_init_reg(rtwdev, nctl_table, rtw89_phy_config_bb_reg, NULL);
rtw89_phy_init_reg(rtwdev, nctl_table, false, rtw89_phy_config_bb_reg, NULL);
if (chip->nctl_post_table)
rtw89_rfk_parser(rtwdev, chip->nctl_post_table);
@ -3186,7 +3214,8 @@ struct rtw89_phy_iter_ra_data {
static void __rtw89_phy_c2h_ra_rpt_iter(struct rtw89_sta_link *rtwsta_link,
struct ieee80211_link_sta *link_sta,
struct rtw89_phy_iter_ra_data *ra_data)
struct rtw89_phy_iter_ra_data *ra_data,
bool *changed)
{
struct rtw89_dev *rtwdev = ra_data->rtwdev;
const struct rtw89_c2h_ra_rpt *c2h =
@ -3195,7 +3224,7 @@ static void __rtw89_phy_c2h_ra_rpt_iter(struct rtw89_sta_link *rtwsta_link,
const struct rtw89_chip_info *chip = rtwdev->chip;
bool format_v1 = chip->chip_gen == RTW89_CHIP_BE;
u8 mode, rate, bw, giltf, mac_id;
u16 legacy_bitrate;
u16 legacy_bitrate, amsdu_len;
bool valid;
u8 mcs = 0;
u8 t;
@ -3292,7 +3321,13 @@ static void __rtw89_phy_c2h_ra_rpt_iter(struct rtw89_sta_link *rtwsta_link,
u16_encode_bits(mode, RTW89_HW_RATE_MASK_MOD) |
u16_encode_bits(rate, RTW89_HW_RATE_MASK_VAL);
ra_report->might_fallback_legacy = mcs <= 2;
link_sta->agg.max_rc_amsdu_len = get_max_amsdu_len(rtwdev, ra_report);
amsdu_len = get_max_amsdu_len(rtwdev, ra_report);
if (link_sta->agg.max_rc_amsdu_len != amsdu_len) {
link_sta->agg.max_rc_amsdu_len = amsdu_len;
*changed = true;
}
rtwsta_link->max_agg_wait = link_sta->agg.max_rc_amsdu_len / 1500 - 1;
}
@ -3303,14 +3338,18 @@ static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta)
struct rtw89_sta_link *rtwsta_link;
struct ieee80211_link_sta *link_sta;
unsigned int link_id;
bool changed = false;
rcu_read_lock();
rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) {
link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false);
__rtw89_phy_c2h_ra_rpt_iter(rtwsta_link, link_sta, ra_data);
__rtw89_phy_c2h_ra_rpt_iter(rtwsta_link, link_sta, ra_data, &changed);
}
if (changed)
ieee80211_sta_recalc_aggregates(sta);
rcu_read_unlock();
}
@ -4860,7 +4899,7 @@ static void rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev *rtwdev,
{
struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
const struct rtw89_chip_info *chip = rtwdev->chip;
u8 sc_xi_val, sc_xo_val;
u8 sc_xi_val = 0, sc_xo_val = 0;
if (!force && cfo->crystal_cap == crystal_cap)
return;

5
drivers/net/wireless/realtek/rtw89/phy.h
View File

@ -852,6 +852,10 @@ bool rtw89_phy_write_rf_v3(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev);
void rtw89_phy_init_bb_afe(struct rtw89_dev *rtwdev);
void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio);
void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev,
const struct rtw89_reg2_def *reg,
enum rtw89_rf_path rf_path,
void *extra_data);
void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev,
const struct rtw89_reg2_def *reg,
enum rtw89_rf_path rf_path,
@ -1002,6 +1006,7 @@ void rtw89_phy_ra_update_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta
void rtw89_phy_ra_update_sta_link(struct rtw89_dev *rtwdev,
struct rtw89_sta_link *rtwsta_link,
u32 changed);
void rtw89_phy_ra_recalc_agg_limit(struct rtw89_dev *rtwdev);
void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev,
struct ieee80211_vif *vif,
const struct cfg80211_bitrate_mask *mask);

2
drivers/net/wireless/realtek/rtw89/phy_be.c
View File

@ -199,7 +199,7 @@ static u32 rtw89_phy0_phy1_offset_be_v1(struct rtw89_dev *rtwdev, u32 addr)
(phy_page >= 0x240 && phy_page <= 0x24f) ||
(phy_page >= 0x260 && phy_page <= 0x26f) ||
(phy_page >= 0x2C0 && phy_page <= 0x2C9) ||
(phy_page >= 0x2E4 && phy_page <= 0x2E8) ||
(phy_page >= 0x2E0 && phy_page <= 0x2E8) ||
phy_page == 0x2EE)
ofst = 0x1000;
else

2
drivers/net/wireless/realtek/rtw89/ps.c
View File

@ -226,6 +226,8 @@ void rtw89_leave_lps(struct rtw89_dev *rtwdev)
rtw89_for_each_rtwvif(rtwdev, rtwvif)
rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id)
rtw89_leave_lps_vif(rtwdev, rtwvif_link);
rtw89_fw_h2c_init_trx_protect(rtwdev);
}
void rtw89_enter_ips(struct rtw89_dev *rtwdev)

285
drivers/net/wireless/realtek/rtw89/reg.h
View File

@ -4291,6 +4291,20 @@
#define B_BE_VERIFY_ENV_MASK GENMASK(9, 8)
#define B_BE_HW_ID_MASK GENMASK(7, 0)
#define R_BE_SCOREBOARD_0 0x0110
#define B_BE_SB0_TOGGLE BIT(31)
#define B_BE_SB0_WL_DATA_LINE_MASK GENMASK(30, 0)
#define R_BE_SCOREBOARD_0_BT_DATA 0x0114
#define B_BE_SB0_BT_DATA_LINE_MASK GENMASK(30, 0)
#define R_BE_SCOREBOARD_1 0x0118
#define B_BE_SB1_TOGGLE BIT(31)
#define B_BE_SB1_WL_DATA_LINE_MASK GENMASK(30, 0)
#define R_BE_SCOREBOARD_1_BT_DATA 0x011C
#define B_BE_SB1_BT_DATA_LINE_MASK GENMASK(30, 0)
#define R_BE_HALT_H2C_CTRL 0x0160
#define B_BE_HALT_H2C_TRIGGER BIT(0)
@ -4403,6 +4417,31 @@
#define B_BE_FS_GPIO17_INT_EN BIT(1)
#define B_BE_FS_GPIO16_INT_EN BIT(0)
#define R_BE_FWS1ISR 0x019C
#define B_BE_FS_WL_HW_RADIO_OFF_INT BIT(28)
#define B_BE_SWRD_BOD_INT BIT(27)
#define B_BE_HCIDBG_INT BIT(25)
#define B_BE_FS_RPWM_INT_V1 BIT(24)
#define B_BE_PCIE_HOTRST BIT(22)
#define B_BE_PCIE_SER_TIMEOUT_INDIC BIT(21)
#define B_BE_PCIE_RXI300_SLVTOUT_INDIC BIT(20)
#define B_BE_AON_PCIE_FLR_INT BIT(19)
#define B_BE_PCIE_ERR_INDIC BIT(18)
#define B_BE_SDIO_ERR_INDIC BIT(17)
#define B_BE_USB_ERR_INDIC BIT(16)
#define B_BE_FS_GPIO27_INT BIT(11)
#define B_BE_FS_GPIO26_INT BIT(10)
#define B_BE_FS_GPIO25_INT BIT(9)
#define B_BE_FS_GPIO24_INT BIT(8)
#define B_BE_FS_GPIO23_INT BIT(7)
#define B_BE_FS_GPIO22_INT BIT(6)
#define B_BE_FS_GPIO21_INT BIT(5)
#define B_BE_FS_GPIO20_INT BIT(4)
#define B_BE_FS_GPIO19_INT BIT(3)
#define B_BE_FS_GPIO18_INT BIT(2)
#define B_BE_FS_GPIO17_INT BIT(1)
#define B_BE_FS_GPIO16_INT BIT(0)
#define R_BE_HIMR0 0x01A0
#define B_BE_WDT_DATACPU_TIMEOUT_INT_EN BIT(25)
#define B_BE_HALT_D2H_INT_EN BIT(24)
@ -4503,6 +4542,44 @@
#define R_BE_UDM2 0x01F8
#define B_BE_UDM2_EPC_RA_MASK GENMASK(31, 0)
#define R_BE_SPS_DIG_ON_CTRL1 0x0204
#define B_BE_SN_N_L_MASK GENMASK(31, 28)
#define B_BE_SP_N_L_MASK GENMASK(27, 24)
#define B_BE_SN_P_L_MASK GENMASK(23, 20)
#define B_BE_SP_P_L_MASK GENMASK(19, 16)
#define B_BE_VO_DISCHG_PWM_H BIT(15)
#define B_BE_REG_MODE_PREDRIVER BIT(14)
#define B_BE_VREFOCP_MASK GENMASK(13, 10)
#define B_BE_POWOCP_L1 BIT(9)
#define B_BE_PWM_FORCE BIT(8)
#define B_BE_PFM_PD_RST BIT(7)
#define B_BE_VC_PFM_RSTB BIT(6)
#define B_BE_PFM_IN_SEL BIT(5)
#define B_BE_VC_RSTB BIT(4)
#define B_BE_FPWMDELAY BIT(3)
#define B_BE_ENFPWMDELAY_H BIT(2)
#define B_BE_REG_MOS_HALF_L BIT(1)
#define B_BE_CURRENT_SENSE_MOS BIT(0)
#define R_BE_SPS_ANA_ON_CTRL1 0x0224
#define B_BE_SN_N_L_ANA_MASK GENMASK(31, 28)
#define B_BE_SP_N_L_ANA_MASK GENMASK(27, 24)
#define B_BE_SN_P_L_ANA_MASK GENMASK(23, 20)
#define B_BE_SP_P_L_ANA_MASK GENMASK(19, 16)
#define B_BE_VO_DISCHG_PWM_H_ANA BIT(15)
#define B_BE_REG_MODE_PREDRIVER_ANA BIT(14)
#define B_BE_VREFOCP_ANA_MASK GENMASK(13, 10)
#define B_BE_POWOCP_L1_ANA BIT(9)
#define B_BE_PWM_FORCE_ANA BIT(8)
#define B_BE_PFM_PD_RST_ANA BIT(7)
#define B_BE_VC_PFM_RSTB_ANA BIT(6)
#define B_BE_PFM_IN_SEL_ANA BIT(5)
#define B_BE_VC_RSTB_ANA BIT(4)
#define B_BE_FPWMDELAY_ANA BIT(3)
#define B_BE_ENFPWMDELAY_H_ANA BIT(2)
#define B_BE_REG_MOS_HALF_L_ANA BIT(1)
#define B_BE_CURRENT_SENSE_MOS_ANA BIT(0)
#define R_BE_AFE_ON_CTRL0 0x0240
#define B_BE_REG_LPF_R3_3_0_MASK GENMASK(31, 29)
#define B_BE_REG_LPF_R2_MASK GENMASK(28, 24)
@ -6738,6 +6815,7 @@
#define R_BE_MUEDCA_EN 0x10370
#define R_BE_MUEDCA_EN_C1 0x14370
#define B_BE_SIFS_TIMEOUT_TB_T2_MASK GENMASK(30, 24)
#define B_BE_SIFS_MACTXEN_TB_T1_DOT05US_MASK GENMASK(23, 16)
#define B_BE_SIFS_MACTXEN_TB_T1_MASK GENMASK(22, 16)
#define B_BE_MUEDCA_WMM_SEL BIT(8)
#define B_BE_SET_MUEDCATIMER_TF_MASK GENMASK(5, 4)
@ -8320,6 +8398,9 @@
#define B_BE_PWR_BT_VAL GENMASK(8, 0)
#define B_BE_PWR_FORCE_COEX_ON GENMASK(29, 27)
#define R_PWR_BOOST_BE4 0x11A64
#define B_PWR_BOOST_BE4 BIT(8)
#define R_BE_PWR_TH 0x11A78
#define R_BE_PWR_RSSI_TARGET_LMT 0x11A84
@ -8378,6 +8459,8 @@
#define RR_MOD_M_RXBB GENMASK(9, 5)
#define RR_MOD_LO_SEL BIT(1)
#define RR_MODOPT 0x01
#define RR_MODOPT_V1 0x10001
#define RR_SW_SEL BIT(19)
#define RR_TXG_SEL GENMASK(19, 17)
#define RR_MODOPT_M_TXPWR GENMASK(5, 0)
#define RR_WLSEL 0x02
@ -8454,6 +8537,7 @@
#define RR_LUTWD0_LB GENMASK(5, 0)
#define RR_TM 0x42
#define RR_TM_TRI BIT(19)
#define RR_TM_TRM GENMASK(17, 11)
#define RR_TM_VAL_V1 GENMASK(7, 0)
#define RR_TM_VAL GENMASK(6, 1)
#define RR_TM2 0x43
@ -8586,6 +8670,7 @@
#define RR_LDO 0xb1
#define RR_LDO_SEL GENMASK(8, 6)
#define RR_VCO 0xb2
#define RR_VCO_VAL GENMASK(18, 14)
#define RR_VCO_SEL GENMASK(9, 8)
#define RR_VCI 0xb3
#define RR_VCI_ON BIT(7)
@ -8709,6 +8794,7 @@
#define B_P0_HW_ANTSW_DIS_BY_GNT_BT BIT(12)
#define B_P0_TRSW_TX_EXTEND GENMASK(3, 0)
#define R_MAC_PIN_SEL 0x0734
#define R_MAC_PIN_SEL_BE4 0x20734
#define B_CH_IDX_SEG0 GENMASK(23, 16)
#define R_PLCP_HISTOGRAM 0x0738
#define R_PLCP_HISTOGRAM_BE_V1 0x20738
@ -8737,6 +8823,7 @@
#define R_PHY_STS_BITMAP_EHT 0x0788
#define R_PHY_STS_BITMAP_EHT_BE4 0x20788
#define R_EDCCA_RPTREG_SEL_BE 0x078C
#define R_EDCCA_RPTREG_SEL_BE4 0x2078C
#define B_EDCCA_RPTREG_SEL_BE_MSK GENMASK(22, 20)
#define R_PMAC_GNT 0x0980
#define B_PMAC_GNT_TXEN BIT(0)
@ -8850,6 +8937,7 @@
#define R_UDP_COEEF 0x0CBC
#define B_UDP_COEEF BIT(19)
#define R_TX_COLLISION_T2R_ST_BE 0x0CC8
#define R_TX_COLLISION_T2R_ST_BE4 0x20CC8
#define B_TX_COLLISION_T2R_ST_BE_M GENMASK(13, 8)
#define R_RXHT_MCS_LIMIT 0x0D18
#define B_RXHT_MCS_LIMIT GENMASK(9, 8)
@ -9078,7 +9166,11 @@
#define R_P1_EN_SOUND_WO_NDP 0x2D7C
#define B_P1_EN_SOUND_WO_NDP BIT(1)
#define R_EDCCA_RPT_A_BE 0x2E38
#define R_EDCCA_RPT_A_BE4 0x2EE30
#define R_EDCCA_RPT_A_BE4_C1 0x2FE30
#define R_EDCCA_RPT_B_BE 0x2E3C
#define R_EDCCA_RPT_B_BE4 0x2EE34
#define R_EDCCA_RPT_B_BE4_C1 0x2FE34
#define R_EDCCA_RPT_P1_A_BE 0x2E40
#define R_EDCCA_RPT_P1_B_BE 0x2E44
#define R_S1_HW_SI_DIS 0x3200
@ -9262,11 +9354,13 @@
#define R_PATH0_P20_FOLLOW_BY_PAGCUGC_V1 0x4C24
#define R_PATH0_P20_FOLLOW_BY_PAGCUGC_V2 0x46E8
#define R_PATH0_P20_FOLLOW_BY_PAGCUGC_V3 0x41C8
#define R_PATH0_P20_FOLLOW_BY_PAGCUGC_BE4 0x241C8
#define B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5)
#define R_PATH0_S20_FOLLOW_BY_PAGCUGC 0x46A4
#define R_PATH0_S20_FOLLOW_BY_PAGCUGC_V1 0x4C28
#define R_PATH0_S20_FOLLOW_BY_PAGCUGC_V2 0x46EC
#define R_PATH0_S20_FOLLOW_BY_PAGCUGC_V3 0x41CC
#define R_PATH0_S20_FOLLOW_BY_PAGCUGC_BE4 0x241CC
#define B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5)
#define R_PATH0_RXB_INIT_V1 0x46A8
#define B_PATH0_RXB_INIT_IDX_MSK_V1 GENMASK(14, 10)
@ -9313,11 +9407,13 @@
#define R_PATH1_P20_FOLLOW_BY_PAGCUGC_V1 0x4CE8
#define R_PATH1_P20_FOLLOW_BY_PAGCUGC_V2 0x47A8
#define R_PATH1_P20_FOLLOW_BY_PAGCUGC_V3 0x45C8
#define R_PATH1_P20_FOLLOW_BY_PAGCUGC_BE4 0x245C8
#define B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5)
#define R_PATH1_S20_FOLLOW_BY_PAGCUGC 0x4778
#define R_PATH1_S20_FOLLOW_BY_PAGCUGC_V1 0x4CEC
#define R_PATH1_S20_FOLLOW_BY_PAGCUGC_V2 0x47AC
#define R_PATH1_S20_FOLLOW_BY_PAGCUGC_V3 0x45CC
#define R_PATH1_S20_FOLLOW_BY_PAGCUGC_BE4 0x245CC
#define B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5)
#define R_PATH1_G_TIA0_LNA6_OP1DB_V1 0x4778
#define B_PATH1_G_TIA0_LNA6_OP1DB_V1 GENMASK(7, 0)
@ -9338,6 +9434,7 @@
#define R_SEG0R_PD 0x481C
#define R_SEG0R_PD_V1 0x4860
#define R_SEG0R_PD_V2 0x6A74
#define R_SEG0R_PD_BE4 0x26210
#define R_SEG0R_EDCCA_LVL 0x4840
#define R_SEG0R_EDCCA_LVL_V1 0x4884
#define B_EDCCA_LVL_MSK3 GENMASK(31, 24)
@ -9476,9 +9573,11 @@
#define B_DCFO_COMP_S0_V1_MSK GENMASK(13, 0)
#define R_BMODE_PDTH_V1 0x4B64
#define R_BMODE_PDTH_V2 0x6708
#define R_BMODE_PDTH_BE4 0x26040
#define B_BMODE_PDTH_LOWER_BOUND_MSK_V1 GENMASK(31, 24)
#define R_BMODE_PDTH_EN_V1 0x4B74
#define R_BMODE_PDTH_EN_V2 0x6718
#define R_BMODE_PDTH_EN_BE4 0x26050
#define B_BMODE_PDTH_LIMIT_EN_MSK_V1 BIT(30)
#define R_BSS_CLR_VLD_V2 0x4EBC
#define B_BSS_CLR_VLD0_V2 BIT(2)
@ -9653,7 +9752,9 @@
#define R_CCK_FC0INV 0x675c
#define B_CCK_FC0INV GENMASK(18, 0)
#define R_SEG0R_EDCCA_LVL_BE 0x69EC
#define R_SEG0R_EDCCA_LVL_BE4 0x2623C
#define R_SEG0R_PPDU_LVL_BE 0x69F0
#define R_SEG0R_PPDU_LVL_BE4 0x26240
#define R_SEGSND 0x6A14
#define B_SEGSND_EN BIT(31)
#define R_DBCC 0x6B48
@ -10148,6 +10249,8 @@
#define B_TSSI_CONT_EN BIT(3)
#define R_P0_TXPWRB_BE 0xE61C
#define R_P1_TXPWRB_BE 0xE71C
#define R_P0_TXPWRB_BE4 0x2251C
#define R_P1_TXPWRB_BE4 0x2261C
#define B_TXPWRB_MAX_BE GENMASK(20, 12)
#define R_TSSI_MAP_OFST_P0 0xE620
#define R_TSSI_MAP_OFST_P1 0xE720
@ -10166,6 +10269,8 @@
#define R_TSSI_K_P1 0xE7A0
#define B_TSSI_K_OFDM_P1 GENMASK(29, 20)
#define R_BBWRAP_ELMSR_BE4 0x11974
#define B_BBWRAP_ELMSR_EN_BE4 GENMASK(29, 28)
#define R_COMP_CIM3K_BE4 0x11998
#define B_COMP_CIM3K_OW_BE4 BIT(1)
#define B_COMP_CIM3K_TH_BE4 BIT(2)
@ -10370,16 +10475,51 @@
#define R_BANDEDGE_DBWY_BE4 0x11AD0
#define B_BANDEDGE_DBW160_BE4 BIT(0)
#define R_SYS_DBCC_BE4 0x20000
#define B_SYS_DBCC_BE4 BIT(0)
#define B_SYS_DBCC_24G_BAND_SEL_BE4 BIT(1)
#define R_EMLSR_SWITCH_BE4 0x20044
#define B_EMLSR_SWITCH_BE4 GENMASK(27, 12)
#define B_EMLSR_BB_CLK_BE4 GENMASK(31, 30)
#define R_CHINFO_SEG_BE4 0x200B4
#define B_CHINFO_SEG_LEN_BE4 GENMASK(12, 10)
#define R_STS_HDR2_PARSING_BE4 0x2070C
#define B_STS_HDR2_PARSING_BE4 BIT(10)
#define R_SEL_GNT_BT_RX_BE4 0x2010C
#define B_SEL_GNT_BT_RX_PATH0_BE4 GENMASK(3, 0)
#define B_SEL_GNT_BT_RX_PATH1_BE4 GENMASK(11, 8)
#define R_SW_SI_WDATA_BE4 0x20370
#define B_SW_SI_DATA_PATH_BE4 GENMASK(31, 28)
#define B_SW_SI_DATA_ADR_BE4 GENMASK(27, 20)
#define B_SW_SI_DATA_DAT_BE4 GENMASK(19, 0)
#define R_SW_SI_READ_ADDR_BE4 0x20378
#define B_SW_SI_READ_ADDR_BE4 GENMASK(10, 0)
#define R_RXBW67_BE4 0x2040C
#define B_RXBW6_BE4 GENMASK(22, 20)
#define B_RXBW7_BE4 GENMASK(25, 23)
#define R_RXBW_BE4 0x20410
#define B_RXBW_BE4 GENMASK(29, 27)
#define R_TXERRCT_EN_BE4 0x20518
#define B_TXERRCT_EN_BE4 BIT(13)
#define R_TXERRCT1_EN_BE4 0x2051C
#define B_TXERRCT1_EN_BE4 BIT(31)
#define R_ENABLE_CCK0_BE4 0x20700
#define B_ENABLE_CCK0_BE4 BIT(5)
#define R_RSTB_ASYNC_BE4 0x20704
#define B_RSTB_ASYNC_BE4 BIT(1)
#define R_STS_HDR2_PARSING_BE4 0x2070C
#define B_STS_HDR2_PARSING_BE4 BIT(10)
#define R_EDCCA_RPT_SEL_BE4 0x20780
#define R_EDCCA_RPT_SEL_BE4_C1 0x21780
#define B_EDCCA_RPT_SEL_BE4_MSK 0xE0000
#define R_SEL_GNT_BT_RXPHY_BE4 0x2079C
#define B_SEL_GNT_BT_RXPHY_BE4 GENMASK(11, 8)
#define R_IMR_TX_ERROR_BE4 0x20920
#define B_IMR_TX_ERROR_BE4 BIT(30)
#define R_TXINFO_PATH_BE4 0x209A4
#define B_TXINFO_PATH_EN_BE4 BIT(17)
#define B_TXINFO_PATH_MA_BE4 BIT(18)
#define B_TXINFO_PATH_MB_BE4 BIT(19)
#define R_SHAPER_COEFF_BE4 0x20CBC
#define B_SHAPER_COEFF_BE4 BIT(19)
#define R_IFS_T1_AVG_BE4 0x20EDC
#define B_IFS_T1_AVG_BE4 GENMASK(15, 0)
#define B_IFS_T2_AVG_BE4 GENMASK(31, 16)
@ -10402,15 +10542,137 @@
#define B_IFS_T3_HIS_BE4 GENMASK(15, 0)
#define B_IFS_T4_HIS_BE4 GENMASK(31, 16)
#define R_TX_ERROR_SEL_BE4 0x21254
#define B_TX_ERROR_PSDU_BE4 BIT(11)
#define B_TX_ERROR_NSYM_BE4 BIT(10)
#define B_TX_ERROR_LSIG_BE4 BIT(9)
#define B_TX_ERROR_TXINFO_BE4 BIT(8)
#define R_TXPWR_RSTB0_BE4 0x2250C
#define B_TXPWR_RSTB0_BE4 BIT(16)
#define R_TSSI_EN_P0_BE4 0x22510
#define B_TSSI_EN_P0_BE4 GENMASK(3, 0)
#define R_TXAGC_REF_DBM_PATH0_TBL0_BE4 0x22528
#define B_TXAGC_OFDM_REF_DBM_PATH0_TBL0_BE4 GENMASK(8, 0)
#define B_TXAGC_CCK_REF_DBM_PATH0_TBL0_BE4 GENMASK(17, 9)
#define R_USED_TSSI_TRK_ON_P0_BE4 0x22534
#define B_USED_TSSI_TRK_ON_P0_BE4 BIT(22)
#define R_TSSI_K_OFDM_PATH0_TBL0_BE4 0x225A0
#define B_TSSI_K_OFDM_PATH0_TBL0_BE4 GENMASK(29, 20)
#define R_TSSI_DCK_MOV_AVG_LEN_P0_BE4 0x225CC
#define B_TSSI_DCK_MOV_AVG_LEN_P0_BE4 GENMASK(8, 6)
#define R_TXPWR_RSTB1_BE4 0x2260C
#define B_TXPWR_RSTB1_BE4 BIT(16)
#define R_TXAGC_REF_DBM_PATH0_TBL1_BE4 0x23528
#define B_TXAGC_OFDM_REF_DBM_PATH0_TBL1_BE4 GENMASK(8, 0)
#define B_TXAGC_CCK_REF_DBM_PATH0_TBL1_BE4 GENMASK(17, 9)
#define R_TSSI_K_OFDM_PATH0_TBL1_BE4 0x235A0
#define B_TSSI_K_OFDM_PATH0_TBL1_BE4 GENMASK(29, 20)
#define R_OFDM_OFST_P0_BE4 0x240C8
#define B_OFDM_OFST_P0_BE4 GENMASK(31, 24)
#define R_PATH0_RXIDX_INIT_BE4 0x24108
#define B_PATH0_RXIDX_INIT_BE4 GENMASK(29, 25)
#define R_PATH0_LNA_INIT_BE4 0x24158
#define B_PATH0_LNA_INIT_IDX_BE4 GENMASK(14, 12)
#define R_BAND_SEL0_BE4 0x24160
#define B_BAND_SEL0_BE4 BIT(26)
#define R_PATH0_TIA_INIT_BE4 0x24168
#define B_PATH0_TIA_INIT_IDX_BE4 BIT(18)
#define R_OFDM_RPL_BIAS_P0_BE4 0x2420C
#define B_OFDM_RPL_BIAS_P0_BE4 GENMASK(11, 2)
#define R_OFDM_OFST_P1_BE4 0x244C8
#define B_OFDM_OFST_P1_BE4 GENMASK(31, 24)
#define R_PATH1_RXIDX_INIT_BE4 0x24508
#define B_PATH1_RXIDX_INIT_BE4 GENMASK(29, 25)
#define R_PATH1_LNA_INIT_BE4 0x24558
#define B_PATH1_LNA_INIT_IDX_BE4 GENMASK(14, 12)
#define R_BAND_SEL1_BE4 0x24560
#define B_BAND_SEL1_BE4 BIT(26)
#define R_PATH1_TIA_INIT_BE4 0x24568
#define B_PATH1_TIA_INIT_IDX_BE4 BIT(18)
#define R_OFDM_RPL_BIAS_P1_BE4 0x2460C
#define B_OFDM_RPL_BIAS_P1_BE4 GENMASK(11, 2)
#define R_TX_CFR_MANUAL_EN_BE4 0x2483C
#define B_TX_CFR_MANUAL_EN_BE4_M BIT(30)
#define R_PCOEFF0_BE4 0x24880
#define B_PCOEFF01_BE4 GENMASK(23, 0)
#define R_PCOEFF2_BE4 0x24884
#define B_PCOEFF23_BE4 GENMASK(23, 0)
#define R_PCOEFF4_BE4 0x24888
#define B_PCOEFF45_BE4 GENMASK(23, 0)
#define R_PCOEFF6_BE4 0x2488C
#define B_PCOEFF67_BE4 GENMASK(23, 0)
#define R_PCOEFF8_BE4 0x24890
#define B_PCOEFF89_BE4 GENMASK(23, 0)
#define R_PCOEFF10_BE4 0x24894
#define B_PCOEFF10_BE4 GENMASK(23, 0)
#define R_PCOEFF12_BE4 0x24898
#define B_PCOEFF12_BE4 GENMASK(23, 0)
#define R_PCOEFF14_BE4 0x2489C
#define B_PCOEFF14_BE4 GENMASK(23, 0)
#define R_BW_BE4 0x24EE4
#define B_BW_BE4 GENMASK(6, 4)
#define B_PRISB_BE4 GENMASK(3, 0)
#define R_FC0_BE4 0x24EE8
#define B_FC0_BE4 GENMASK(12, 0)
#define R_ANT_RX_1RCCA_BE4 0x24EEC
#define B_ANT_RX_1RCCA_BE4 GENMASK(17, 14)
#define R_ANT_RX_BE4 0x24EF0
#define B_ANT_RX_BE4 GENMASK(3, 0)
#define R_FC0_INV_BE4 0x24EF4
#define B_FC0_INV_BE4 GENMASK(15, 0)
#define R_CCK_RPL_OFST_BE4 0x26084
#define B_CCK_RPL_OFST_BE4 GENMASK(7, 0)
#define R_BK_FC0_INV_BE4 0x2608C
#define B_BK_FC0_INV_BE4 GENMASK(18, 0)
#define R_CCK_FC0_INV_BE4 0x26090
#define B_CCK_FC0_INV_BE4 GENMASK(18, 0)
#define R_GAIN_BIAS_BE4 0x260A0
#define B_GAIN_BIAS_BW20_BE4 GENMASK(11, 6)
#define B_GAIN_BIAS_BW40_BE4 GENMASK(17, 12)
#define R_AWGN_DET_BE4 0x2668C
#define B_AWGN_DET_BE4 GENMASK(17, 9)
#define R_CSI_WGT_BE4 0x26770
#define B_CSI_WGT_EN_BE4 BIT(0)
#define B_CSI_WGT_IDX_BE4 GENMASK(31, 20)
#define R_CHINFO_OPT_BE4 0x267C8
#define B_CHINFO_OPT_BE4 GENMASK(14, 13)
#define R_CHINFO_NX_BE4 0x267D0
#define B_CHINFO_NX_BE4 GENMASK(16, 6)
#define R_CHINFO_ALG_BE4 0x267C8
#define B_CHINFO_ALG_BE4 GENMASK(31, 30)
#define R_RX_AWGN02_BE4 0x2680C
#define B_RX_AWGN11_BE4 GENMASK(23, 18)
#define R_RX_AWGN00_BE4 0x26814
#define B_RX_AWGN04_BE4 GENMASK(5, 0)
#define B_RX_AWGN07_BE4 GENMASK(23, 18)
#define R_RX_AWGN01_BE4 0x26818
#define B_RX_AWGN09_BE4 GENMASK(5, 0)
#define R_RXCH_BCC0_BE4 0x26824
#define B_RXCH_MCS4_BE4 GENMASK(29, 24)
#define R_RXCH_BCC1_BE4 0x26828
#define B_RXCH_MCS5_BE4 GENMASK(5, 0)
#define B_RXCH_MCS6_BE4 GENMASK(11, 6)
#define B_RXCH_MCS7_BE4 GENMASK(17, 12)
#define B_RXCH_MCS8_BE4 GENMASK(23, 18)
#define B_RXCH_MCS9_BE4 GENMASK(29, 24)
#define R_RX_LDPC02_BE4 0x26834
#define B_RX_LDPC10_BE4 GENMASK(17, 12)
#define B_RX_LDPC11_BE4 GENMASK(23, 18)
#define R_RX_LDPC00_BE4 0x2683C
#define B_RX_LDPC04_BE4 GENMASK(5, 0)
#define B_RX_LDPC05_BE4 GENMASK(11, 6)
#define B_RX_LDPC06_BE4 GENMASK(17, 12)
#define B_RX_LDPC07_BE4 GENMASK(23, 18)
#define B_RX_LDPC08_BE4 GENMASK(29, 24)
#define R_RX_LDPC01_BE4 0x26840
#define B_RX_LDPC09_BE4 GENMASK(5, 0)
#define R_BSS_CLR_MAP_BE4 0x26914
#define R_BSS_CLR_VLD_BE4 0x26920
#define B_BSS_CLR_VLD_BE4 BIT(2)
#define R_SW_SI_DATA_BE4 0x2CF4C
#define B_SW_SI_READ_DATA_BE4 GENMASK(19, 0)
@ -10418,6 +10680,25 @@
#define B_SW_SI_R_BUSY_BE4 BIT(25)
#define B_SW_SI_READ_DATA_DONE_BE4 BIT(26)
#define R_RX_PATH0_TBL0_BE4 0x2E028
#define R_RX_PATH1_TBL0_BE4 0x2E128
#define R_KTBL0A_BE4 0x38104
#define R_KTBL0B_BE4 0x38204
#define B_KTBL0_IDX0 GENMASK(1, 0)
#define B_KTBL0_IDX1 GENMASK(9, 8)
#define B_KTBL0_RST BIT(31)
#define R_KTBL1A_BE4 0x38154
#define R_KTBL1B_BE4 0x38254
#define B_KTBL1_TBL0 BIT(3)
#define B_KTBL1_TBL1 BIT(5)
#define R_TC_EN_BE4 0x3c200
#define B_TC_EN_BE4 BIT(0)
#define B_TC_TRIG_BE4 BIT(1)
#define R_TC_VAL_BE4 0x3c208
#define B_TC_VAL_BE4 GENMASK(7, 0)
/* WiFi CPU local domain */
#define R_AX_WDT_CTRL 0x0040
#define B_AX_WDT_EN BIT(31)

49
drivers/net/wireless/realtek/rtw89/rtw8851b.c
View File

@ -15,10 +15,10 @@
#include "txrx.h"
#include "util.h"
#define RTW8851B_FW_FORMAT_MAX 0
#define RTW8851B_FW_FORMAT_MAX 1
#define RTW8851B_FW_BASENAME "rtw89/rtw8851b_fw"
#define RTW8851B_MODULE_FIRMWARE \
RTW8851B_FW_BASENAME ".bin"
RTW89_GEN_MODULE_FWNAME(RTW8851B_FW_BASENAME, RTW8851B_FW_FORMAT_MAX)
static const struct rtw89_hfc_ch_cfg rtw8851b_hfc_chcfg_pcie[] = {
{5, 343, grp_0}, /* ACH 0 */
@ -52,25 +52,25 @@ static const struct rtw89_hfc_param_ini rtw8851b_hfc_param_ini_pcie[] = {
};
static const struct rtw89_hfc_ch_cfg rtw8851b_hfc_chcfg_usb[] = {
{18, 152, grp_0}, /* ACH 0 */
{18, 152, grp_0}, /* ACH 1 */
{18, 152, grp_0}, /* ACH 2 */
{18, 152, grp_0}, /* ACH 3 */
{18, 210, grp_0}, /* ACH 0 */
{18, 210, grp_0}, /* ACH 1 */
{18, 210, grp_0}, /* ACH 2 */
{18, 210, grp_0}, /* ACH 3 */
{0, 0, grp_0}, /* ACH 4 */
{0, 0, grp_0}, /* ACH 5 */
{0, 0, grp_0}, /* ACH 6 */
{0, 0, grp_0}, /* ACH 7 */
{18, 152, grp_0}, /* B0MGQ */
{18, 152, grp_0}, /* B0HIQ */
{18, 210, grp_0}, /* B0MGQ */
{18, 210, grp_0}, /* B0HIQ */
{0, 0, grp_0}, /* B1MGQ */
{0, 0, grp_0}, /* B1HIQ */
{0, 0, 0} /* FWCMDQ */
};
static const struct rtw89_hfc_pub_cfg rtw8851b_hfc_pubcfg_usb = {
152, /* Group 0 */
210, /* Group 0 */
0, /* Group 1 */
152, /* Public Max */
210, /* Public Max */
0 /* WP threshold */
};
@ -111,10 +111,10 @@ static const struct rtw89_dle_mem rtw8851b_dle_mem_pcie[] = {
};
static const struct rtw89_dle_mem rtw8851b_dle_mem_usb2[] = {
[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size25,
&rtw89_mac_size.ple_size32, &rtw89_mac_size.wde_qt25,
&rtw89_mac_size.wde_qt25, &rtw89_mac_size.ple_qt72,
&rtw89_mac_size.ple_qt73},
[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size30,
&rtw89_mac_size.ple_size27, &rtw89_mac_size.wde_qt30,
&rtw89_mac_size.wde_qt30, &rtw89_mac_size.ple_qt61,
&rtw89_mac_size.ple_qt62},
[RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size9,
&rtw89_mac_size.ple_size8, &rtw89_mac_size.wde_qt4,
&rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,
@ -124,10 +124,10 @@ static const struct rtw89_dle_mem rtw8851b_dle_mem_usb2[] = {
};
static const struct rtw89_dle_mem rtw8851b_dle_mem_usb3[] = {
[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size25,
&rtw89_mac_size.ple_size33, &rtw89_mac_size.wde_qt25,
&rtw89_mac_size.wde_qt25, &rtw89_mac_size.ple_qt74,
&rtw89_mac_size.ple_qt75},
[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size30,
&rtw89_mac_size.ple_size31, &rtw89_mac_size.wde_qt30,
&rtw89_mac_size.wde_qt30, &rtw89_mac_size.ple_qt27,
&rtw89_mac_size.ple_qt28},
[RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size9,
&rtw89_mac_size.ple_size8, &rtw89_mac_size.wde_qt4,
&rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,
@ -2580,8 +2580,11 @@ const struct rtw89_chip_info rtw8851b_chip_info = {
.ops = &rtw8851b_chip_ops,
.mac_def = &rtw89_mac_gen_ax,
.phy_def = &rtw89_phy_gen_ax,
.fw_basename = RTW8851B_FW_BASENAME,
.fw_format_max = RTW8851B_FW_FORMAT_MAX,
.fw_def = {
.fw_basename = RTW8851B_FW_BASENAME,
.fw_format_max = RTW8851B_FW_FORMAT_MAX,
.fw_b_aid = 0,
},
.try_ce_fw = true,
.bbmcu_nr = 0,
.needed_fw_elms = 0,
@ -2638,7 +2641,7 @@ const struct rtw89_chip_info rtw8851b_chip_info = {
.support_noise = false,
.ul_tb_waveform_ctrl = true,
.ul_tb_pwr_diff = false,
.rx_freq_frome_ie = true,
.rx_freq_from_ie = true,
.hw_sec_hdr = false,
.hw_mgmt_tx_encrypt = false,
.hw_tkip_crypto = false,
@ -2678,6 +2681,10 @@ const struct rtw89_chip_info rtw8851b_chip_info = {
.rf_para_ulink = rtw89_btc_8851b_rf_ul,
.rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8851b_rf_dl),
.rf_para_dlink = rtw89_btc_8851b_rf_dl,
.rf_para_ulink_v9 = NULL,
.rf_para_dlink_v9 = NULL,
.rf_para_ulink_num_v9 = 0,
.rf_para_dlink_num_v9 = 0,
.ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) |
BIT(RTW89_PS_MODE_CLK_GATED),
.low_power_hci_modes = 0,

1
drivers/net/wireless/realtek/rtw89/rtw8851bu.c
View File

@ -15,6 +15,7 @@ static const struct rtw89_usb_info rtw8851b_usb_info = {
.usb3_mac_npi_config_intf_0 = R_AX_USB3_MAC_NPI_CONFIG_INTF_0,
.usb_endpoint_0 = R_AX_USB_ENDPOINT_0,
.usb_endpoint_2 = R_AX_USB_ENDPOINT_2,
.rx_agg_alignment = 8,
.bulkout_id = {
[RTW89_DMA_ACH0] = 3,
[RTW89_DMA_ACH1] = 4,

68
drivers/net/wireless/realtek/rtw89/rtw8852a.c
View File

@ -12,10 +12,10 @@
#include "rtw8852a_table.h"
#include "txrx.h"
#define RTW8852A_FW_FORMAT_MAX 0
#define RTW8852A_FW_FORMAT_MAX 1
#define RTW8852A_FW_BASENAME "rtw89/rtw8852a_fw"
#define RTW8852A_MODULE_FIRMWARE \
RTW8852A_FW_BASENAME ".bin"
RTW89_GEN_MODULE_FWNAME(RTW8852A_FW_BASENAME, RTW8852A_FW_FORMAT_MAX)
static const struct rtw89_hfc_ch_cfg rtw8852a_hfc_chcfg_pcie[] = {
{128, 1896, grp_0}, /* ACH 0 */
@ -2179,6 +2179,57 @@ static void rtw8852a_query_ppdu(struct rtw89_dev *rtwdev,
rtw8852a_fill_freq_with_ppdu(rtwdev, phy_ppdu, status);
}
#define DECLARE_DIG_TABLE(name) \
static const struct rtw89_phy_dig_gain_cfg name##_table = { \
.table = name, \
.size = ARRAY_SIZE(name) \
}
static const struct rtw89_reg_def rtw89_8852a_lna_gain_g[] = {
{R_PATH0_LNA_ERR1, B_PATH0_LNA_ERR_G0_G_MSK},
{R_PATH0_LNA_ERR2, B_PATH0_LNA_ERR_G1_G_MSK},
{R_PATH0_LNA_ERR2, B_PATH0_LNA_ERR_G2_G_MSK},
{R_PATH0_LNA_ERR3, B_PATH0_LNA_ERR_G3_G_MSK},
{R_PATH0_LNA_ERR3, B_PATH0_LNA_ERR_G4_G_MSK},
{R_PATH0_LNA_ERR4, B_PATH0_LNA_ERR_G5_G_MSK},
{R_PATH0_LNA_ERR5, B_PATH0_LNA_ERR_G6_G_MSK},
};
DECLARE_DIG_TABLE(rtw89_8852a_lna_gain_g);
static const struct rtw89_reg_def rtw89_8852a_tia_gain_g[] = {
{R_PATH0_TIA_ERR_G0, B_PATH0_TIA_ERR_G0_G_MSK},
{R_PATH0_TIA_ERR_G1, B_PATH0_TIA_ERR_G1_G_MSK},
};
DECLARE_DIG_TABLE(rtw89_8852a_tia_gain_g);
static const struct rtw89_reg_def rtw89_8852a_lna_gain_a[] = {
{R_PATH0_LNA_ERR1, B_PATH0_LNA_ERR_G0_A_MSK},
{R_PATH0_LNA_ERR1, B_PATH0_LNA_ERR_G1_A_MSK},
{R_PATH0_LNA_ERR2, B_PATH0_LNA_ERR_G2_A_MSK},
{R_PATH0_LNA_ERR3, B_PATH0_LNA_ERR_G3_A_MSK},
{R_PATH0_LNA_ERR3, B_PATH0_LNA_ERR_G4_A_MSK},
{R_PATH0_LNA_ERR4, B_PATH0_LNA_ERR_G5_A_MSK},
{R_PATH0_LNA_ERR4, B_PATH0_LNA_ERR_G6_A_MSK},
};
DECLARE_DIG_TABLE(rtw89_8852a_lna_gain_a);
static const struct rtw89_reg_def rtw89_8852a_tia_gain_a[] = {
{R_PATH0_TIA_ERR_G0, B_PATH0_TIA_ERR_G0_A_MSK},
{R_PATH0_TIA_ERR_G1, B_PATH0_TIA_ERR_G1_A_MSK},
};
DECLARE_DIG_TABLE(rtw89_8852a_tia_gain_a);
static const struct rtw89_phy_dig_gain_table rtw89_8852a_phy_dig_table = {
.cfg_lna_g = &rtw89_8852a_lna_gain_g_table,
.cfg_tia_g = &rtw89_8852a_tia_gain_g_table,
.cfg_lna_a = &rtw89_8852a_lna_gain_a_table,
.cfg_tia_a = &rtw89_8852a_tia_gain_a_table
};
#ifdef CONFIG_PM
static const struct wiphy_wowlan_support rtw_wowlan_stub_8852a = {
.flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
@ -2265,8 +2316,11 @@ const struct rtw89_chip_info rtw8852a_chip_info = {
.ops = &rtw8852a_chip_ops,
.mac_def = &rtw89_mac_gen_ax,
.phy_def = &rtw89_phy_gen_ax,
.fw_basename = RTW8852A_FW_BASENAME,
.fw_format_max = RTW8852A_FW_FORMAT_MAX,
.fw_def = {
.fw_basename = RTW8852A_FW_BASENAME,
.fw_format_max = RTW8852A_FW_FORMAT_MAX,
.fw_b_aid = 0,
},
.try_ce_fw = false,
.bbmcu_nr = 0,
.needed_fw_elms = 0,
@ -2324,7 +2378,7 @@ const struct rtw89_chip_info rtw8852a_chip_info = {
.support_noise = true,
.ul_tb_waveform_ctrl = false,
.ul_tb_pwr_diff = false,
.rx_freq_frome_ie = true,
.rx_freq_from_ie = true,
.hw_sec_hdr = false,
.hw_mgmt_tx_encrypt = false,
.hw_tkip_crypto = false,
@ -2364,6 +2418,10 @@ const struct rtw89_chip_info rtw8852a_chip_info = {
.rf_para_ulink = rtw89_btc_8852a_rf_ul,
.rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852a_rf_dl),
.rf_para_dlink = rtw89_btc_8852a_rf_dl,
.rf_para_ulink_v9 = NULL,
.rf_para_dlink_v9 = NULL,
.rf_para_ulink_num_v9 = 0,
.rf_para_dlink_num_v9 = 0,
.ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) |
BIT(RTW89_PS_MODE_CLK_GATED) |
BIT(RTW89_PS_MODE_PWR_GATED),

51
drivers/net/wireless/realtek/rtw89/rtw8852a_table.c
View File

@ -50952,50 +50952,6 @@ const s8 rtw89_8852a_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[2][1][RTW89_UK][46] = 32,
};
#define DECLARE_DIG_TABLE(name) \
static const struct rtw89_phy_dig_gain_cfg name##_table = { \
.table = name, \
.size = ARRAY_SIZE(name) \
}
static const struct rtw89_reg_def rtw89_8852a_lna_gain_g[] = {
{R_PATH0_LNA_ERR1, B_PATH0_LNA_ERR_G0_G_MSK},
{R_PATH0_LNA_ERR2, B_PATH0_LNA_ERR_G1_G_MSK},
{R_PATH0_LNA_ERR2, B_PATH0_LNA_ERR_G2_G_MSK},
{R_PATH0_LNA_ERR3, B_PATH0_LNA_ERR_G3_G_MSK},
{R_PATH0_LNA_ERR3, B_PATH0_LNA_ERR_G4_G_MSK},
{R_PATH0_LNA_ERR4, B_PATH0_LNA_ERR_G5_G_MSK},
{R_PATH0_LNA_ERR5, B_PATH0_LNA_ERR_G6_G_MSK},
};
DECLARE_DIG_TABLE(rtw89_8852a_lna_gain_g);
static const struct rtw89_reg_def rtw89_8852a_tia_gain_g[] = {
{R_PATH0_TIA_ERR_G0, B_PATH0_TIA_ERR_G0_G_MSK},
{R_PATH0_TIA_ERR_G1, B_PATH0_TIA_ERR_G1_G_MSK},
};
DECLARE_DIG_TABLE(rtw89_8852a_tia_gain_g);
static const struct rtw89_reg_def rtw89_8852a_lna_gain_a[] = {
{R_PATH0_LNA_ERR1, B_PATH0_LNA_ERR_G0_A_MSK},
{R_PATH0_LNA_ERR1, B_PATH0_LNA_ERR_G1_A_MSK},
{R_PATH0_LNA_ERR2, B_PATH0_LNA_ERR_G2_A_MSK},
{R_PATH0_LNA_ERR3, B_PATH0_LNA_ERR_G3_A_MSK},
{R_PATH0_LNA_ERR3, B_PATH0_LNA_ERR_G4_A_MSK},
{R_PATH0_LNA_ERR4, B_PATH0_LNA_ERR_G5_A_MSK},
{R_PATH0_LNA_ERR4, B_PATH0_LNA_ERR_G6_A_MSK},
};
DECLARE_DIG_TABLE(rtw89_8852a_lna_gain_a);
static const struct rtw89_reg_def rtw89_8852a_tia_gain_a[] = {
{R_PATH0_TIA_ERR_G0, B_PATH0_TIA_ERR_G0_A_MSK},
{R_PATH0_TIA_ERR_G1, B_PATH0_TIA_ERR_G1_A_MSK},
};
DECLARE_DIG_TABLE(rtw89_8852a_tia_gain_a);
const struct rtw89_phy_table rtw89_8852a_phy_bb_table = {
.regs = rtw89_8852a_phy_bb_regs,
.n_regs = ARRAY_SIZE(rtw89_8852a_phy_bb_regs),
@ -51042,13 +50998,6 @@ const struct rtw89_txpwr_track_cfg rtw89_8852a_trk_cfg = {
.delta_swingidx_2g_cck_a_p = _txpwr_track_delta_swingidx_2g_cck_a_p,
};
const struct rtw89_phy_dig_gain_table rtw89_8852a_phy_dig_table = {
.cfg_lna_g = &rtw89_8852a_lna_gain_g_table,
.cfg_tia_g = &rtw89_8852a_tia_gain_g_table,
.cfg_lna_a = &rtw89_8852a_lna_gain_a_table,
.cfg_tia_a = &rtw89_8852a_tia_gain_a_table
};
const struct rtw89_rfe_parms rtw89_8852a_dflt_parms = {
.byr_tbl = &rtw89_8852a_byr_table,
.rule_2ghz = {

1
drivers/net/wireless/realtek/rtw89/rtw8852a_table.h
View File

@ -11,7 +11,6 @@ extern const struct rtw89_phy_table rtw89_8852a_phy_bb_table;
extern const struct rtw89_phy_table rtw89_8852a_phy_radioa_table;
extern const struct rtw89_phy_table rtw89_8852a_phy_radiob_table;
extern const struct rtw89_phy_table rtw89_8852a_phy_nctl_table;
extern const struct rtw89_phy_dig_gain_table rtw89_8852a_phy_dig_table;
extern const struct rtw89_txpwr_track_cfg rtw89_8852a_trk_cfg;
extern const struct rtw89_rfe_parms rtw89_8852a_dflt_parms;

1
drivers/net/wireless/realtek/rtw89/rtw8852au.c
View File

@ -15,6 +15,7 @@ static const struct rtw89_usb_info rtw8852a_usb_info = {
.usb3_mac_npi_config_intf_0 = R_AX_USB3_MAC_NPI_CONFIG_INTF_0,
.usb_endpoint_0 = R_AX_USB_ENDPOINT_0,
.usb_endpoint_2 = R_AX_USB_ENDPOINT_2,
.rx_agg_alignment = 8,
.bulkout_id = {
[RTW89_DMA_ACH0] = 3,
[RTW89_DMA_ACH2] = 5,

41
drivers/net/wireless/realtek/rtw89/rtw8852b.c
View File

@ -13,10 +13,10 @@
#include "rtw8852b_table.h"
#include "txrx.h"
#define RTW8852B_FW_FORMAT_MAX 1
#define RTW8852B_FW_FORMAT_MAX 2
#define RTW8852B_FW_BASENAME "rtw89/rtw8852b_fw"
#define RTW8852B_MODULE_FIRMWARE \
RTW8852B_FW_BASENAME "-" __stringify(RTW8852B_FW_FORMAT_MAX) ".bin"
RTW89_GEN_MODULE_FWNAME(RTW8852B_FW_BASENAME, RTW8852B_FW_FORMAT_MAX)
static const struct rtw89_hfc_ch_cfg rtw8852b_hfc_chcfg_pcie[] = {
{5, 341, grp_0}, /* ACH 0 */
@ -50,25 +50,25 @@ static const struct rtw89_hfc_param_ini rtw8852b_hfc_param_ini_pcie[] = {
};
static const struct rtw89_hfc_ch_cfg rtw8852b_hfc_chcfg_usb[] = {
{18, 152, grp_0}, /* ACH 0 */
{18, 152, grp_0}, /* ACH 1 */
{18, 152, grp_0}, /* ACH 2 */
{18, 152, grp_0}, /* ACH 3 */
{18, 210, grp_0}, /* ACH 0 */
{18, 210, grp_0}, /* ACH 1 */
{18, 210, grp_0}, /* ACH 2 */
{18, 210, grp_0}, /* ACH 3 */
{0, 0, grp_0}, /* ACH 4 */
{0, 0, grp_0}, /* ACH 5 */
{0, 0, grp_0}, /* ACH 6 */
{0, 0, grp_0}, /* ACH 7 */
{18, 152, grp_0}, /* B0MGQ */
{18, 152, grp_0}, /* B0HIQ */
{18, 210, grp_0}, /* B0MGQ */
{18, 210, grp_0}, /* B0HIQ */
{0, 0, grp_0}, /* B1MGQ */
{0, 0, grp_0}, /* B1HIQ */
{0, 0, 0} /* FWCMDQ */
};
static const struct rtw89_hfc_pub_cfg rtw8852b_hfc_pubcfg_usb = {
152, /* Group 0 */
210, /* Group 0 */
0, /* Group 1 */
152, /* Public Max */
210, /* Public Max */
0 /* WP threshold */
};
@ -109,10 +109,10 @@ static const struct rtw89_dle_mem rtw8852b_dle_mem_pcie[] = {
};
static const struct rtw89_dle_mem rtw8852b_dle_mem_usb3[] = {
[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size25,
&rtw89_mac_size.ple_size33, &rtw89_mac_size.wde_qt25,
&rtw89_mac_size.wde_qt25, &rtw89_mac_size.ple_qt74,
&rtw89_mac_size.ple_qt75},
[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size30,
&rtw89_mac_size.ple_size31, &rtw89_mac_size.wde_qt30,
&rtw89_mac_size.wde_qt30, &rtw89_mac_size.ple_qt27,
&rtw89_mac_size.ple_qt28},
[RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size9,
&rtw89_mac_size.ple_size8, &rtw89_mac_size.wde_qt4,
&rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,
@ -911,8 +911,11 @@ const struct rtw89_chip_info rtw8852b_chip_info = {
.ops = &rtw8852b_chip_ops,
.mac_def = &rtw89_mac_gen_ax,
.phy_def = &rtw89_phy_gen_ax,
.fw_basename = RTW8852B_FW_BASENAME,
.fw_format_max = RTW8852B_FW_FORMAT_MAX,
.fw_def = {
.fw_basename = RTW8852B_FW_BASENAME,
.fw_format_max = RTW8852B_FW_FORMAT_MAX,
.fw_b_aid = 0,
},
.try_ce_fw = true,
.bbmcu_nr = 0,
.needed_fw_elms = 0,
@ -971,7 +974,7 @@ const struct rtw89_chip_info rtw8852b_chip_info = {
.support_noise = false,
.ul_tb_waveform_ctrl = true,
.ul_tb_pwr_diff = false,
.rx_freq_frome_ie = true,
.rx_freq_from_ie = true,
.hw_sec_hdr = false,
.hw_mgmt_tx_encrypt = false,
.hw_tkip_crypto = false,
@ -1011,6 +1014,10 @@ const struct rtw89_chip_info rtw8852b_chip_info = {
.rf_para_ulink = rtw89_btc_8852b_rf_ul,
.rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852b_rf_dl),
.rf_para_dlink = rtw89_btc_8852b_rf_dl,
.rf_para_ulink_v9 = NULL,
.rf_para_dlink_v9 = NULL,
.rf_para_ulink_num_v9 = 0,
.rf_para_dlink_num_v9 = 0,
.ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) |
BIT(RTW89_PS_MODE_CLK_GATED) |
BIT(RTW89_PS_MODE_PWR_GATED),

15
drivers/net/wireless/realtek/rtw89/rtw8852bt.c
View File

@ -14,7 +14,7 @@
#define RTW8852BT_FW_FORMAT_MAX 0
#define RTW8852BT_FW_BASENAME "rtw89/rtw8852bt_fw"
#define RTW8852BT_MODULE_FIRMWARE \
RTW8852BT_FW_BASENAME ".bin"
RTW89_GEN_MODULE_FWNAME(RTW8852BT_FW_BASENAME, RTW8852BT_FW_FORMAT_MAX)
static const struct rtw89_hfc_ch_cfg rtw8852bt_hfc_chcfg_pcie[] = {
{16, 742, grp_0}, /* ACH 0 */
@ -757,8 +757,11 @@ const struct rtw89_chip_info rtw8852bt_chip_info = {
.ops = &rtw8852bt_chip_ops,
.mac_def = &rtw89_mac_gen_ax,
.phy_def = &rtw89_phy_gen_ax,
.fw_basename = RTW8852BT_FW_BASENAME,
.fw_format_max = RTW8852BT_FW_FORMAT_MAX,
.fw_def = {
.fw_basename = RTW8852BT_FW_BASENAME,
.fw_format_max = RTW8852BT_FW_FORMAT_MAX,
.fw_b_aid = 0,
},
.try_ce_fw = true,
.bbmcu_nr = 0,
.needed_fw_elms = RTW89_AX_GEN_DEF_NEEDED_FW_ELEMENTS_NO_6GHZ,
@ -810,7 +813,7 @@ const struct rtw89_chip_info rtw8852bt_chip_info = {
.support_sar_by_ant = true,
.ul_tb_waveform_ctrl = true,
.ul_tb_pwr_diff = false,
.rx_freq_frome_ie = true,
.rx_freq_from_ie = true,
.hw_sec_hdr = false,
.hw_mgmt_tx_encrypt = false,
.hw_tkip_crypto = true,
@ -850,6 +853,10 @@ const struct rtw89_chip_info rtw8852bt_chip_info = {
.rf_para_ulink = rtw89_btc_8852bt_rf_ul,
.rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852bt_rf_dl),
.rf_para_dlink = rtw89_btc_8852bt_rf_dl,
.rf_para_ulink_v9 = NULL,
.rf_para_dlink_v9 = NULL,
.rf_para_ulink_num_v9 = 0,
.rf_para_dlink_num_v9 = 0,
.ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) |
BIT(RTW89_PS_MODE_CLK_GATED) |
BIT(RTW89_PS_MODE_PWR_GATED),

1
drivers/net/wireless/realtek/rtw89/rtw8852bu.c
View File

@ -15,6 +15,7 @@ static const struct rtw89_usb_info rtw8852b_usb_info = {
.usb3_mac_npi_config_intf_0 = R_AX_USB3_MAC_NPI_CONFIG_INTF_0,
.usb_endpoint_0 = R_AX_USB_ENDPOINT_0,
.usb_endpoint_2 = R_AX_USB_ENDPOINT_2,
.rx_agg_alignment = 8,
.bulkout_id = {
[RTW89_DMA_ACH0] = 3,
[RTW89_DMA_ACH1] = 4,

17
drivers/net/wireless/realtek/rtw89/rtw8852c.c
View File

@ -18,7 +18,7 @@
#define RTW8852C_FW_FORMAT_MAX 2
#define RTW8852C_FW_BASENAME "rtw89/rtw8852c_fw"
#define RTW8852C_MODULE_FIRMWARE \
RTW8852C_FW_BASENAME "-" __stringify(RTW8852C_FW_FORMAT_MAX) ".bin"
RTW89_GEN_MODULE_FWNAME(RTW8852C_FW_BASENAME, RTW8852C_FW_FORMAT_MAX)
static const struct rtw89_hfc_ch_cfg rtw8852c_hfc_chcfg_pcie[] = {
{13, 1614, grp_0}, /* ACH 0 */
@ -463,7 +463,7 @@ static int rtw8852c_pwr_off_func(struct rtw89_dev *rtwdev)
else if (rtwdev->hci.type == RTW89_HCI_TYPE_USB)
rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_SOP_EDSWR);
rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_XTAL_OFF_A_DIE);
rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_XTAL_OFF_A_DIE);
rtw89_write32_set(rtwdev, R_AX_SYS_SWR_CTRL1, B_AX_SYM_CTRL_SPS_PWMFREQ);
rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0,
B_AX_REG_ZCDC_H_MASK, 0x3);
@ -3106,8 +3106,11 @@ const struct rtw89_chip_info rtw8852c_chip_info = {
.ops = &rtw8852c_chip_ops,
.mac_def = &rtw89_mac_gen_ax,
.phy_def = &rtw89_phy_gen_ax,
.fw_basename = RTW8852C_FW_BASENAME,
.fw_format_max = RTW8852C_FW_FORMAT_MAX,
.fw_def = {
.fw_basename = RTW8852C_FW_BASENAME,
.fw_format_max = RTW8852C_FW_FORMAT_MAX,
.fw_b_aid = 0,
},
.try_ce_fw = false,
.bbmcu_nr = 0,
.needed_fw_elms = 0,
@ -3168,7 +3171,7 @@ const struct rtw89_chip_info rtw8852c_chip_info = {
.support_noise = false,
.ul_tb_waveform_ctrl = false,
.ul_tb_pwr_diff = true,
.rx_freq_frome_ie = false,
.rx_freq_from_ie = false,
.hw_sec_hdr = true,
.hw_mgmt_tx_encrypt = true,
.hw_tkip_crypto = true,
@ -3208,6 +3211,10 @@ const struct rtw89_chip_info rtw8852c_chip_info = {
.rf_para_ulink = rtw89_btc_8852c_rf_ul,
.rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852c_rf_dl),
.rf_para_dlink = rtw89_btc_8852c_rf_dl,
.rf_para_ulink_v9 = NULL,
.rf_para_dlink_v9 = NULL,
.rf_para_ulink_num_v9 = 0,
.rf_para_dlink_num_v9 = 0,
.ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) |
BIT(RTW89_PS_MODE_CLK_GATED) |
BIT(RTW89_PS_MODE_PWR_GATED),

7
drivers/net/wireless/realtek/rtw89/rtw8852cu.c
View File

@ -15,6 +15,7 @@ static const struct rtw89_usb_info rtw8852c_usb_info = {
.usb3_mac_npi_config_intf_0 = R_AX_USB3_MAC_NPI_CONFIG_INTF_0_V1,
.usb_endpoint_0 = R_AX_USB_ENDPOINT_0_V1,
.usb_endpoint_2 = R_AX_USB_ENDPOINT_2_V1,
.rx_agg_alignment = 8,
.bulkout_id = {
[RTW89_DMA_ACH0] = 3,
[RTW89_DMA_ACH2] = 5,
@ -38,6 +39,10 @@ static const struct rtw89_driver_info rtw89_8852cu_info = {
};
static const struct usb_device_id rtw_8852cu_id_table[] = {
{ USB_DEVICE_AND_INTERFACE_INFO(0x0411, 0x03a6, 0xff, 0xff, 0xff),
.driver_info = (kernel_ulong_t)&rtw89_8852cu_info },
{ USB_DEVICE_AND_INTERFACE_INFO(0x056e, 0x4024, 0xff, 0xff, 0xff),
.driver_info = (kernel_ulong_t)&rtw89_8852cu_info },
{ USB_DEVICE_AND_INTERFACE_INFO(0x0bda, 0xc832, 0xff, 0xff, 0xff),
.driver_info = (kernel_ulong_t)&rtw89_8852cu_info },
{ USB_DEVICE_AND_INTERFACE_INFO(0x0bda, 0xc85a, 0xff, 0xff, 0xff),
@ -54,6 +59,8 @@ static const struct usb_device_id rtw_8852cu_id_table[] = {
.driver_info = (kernel_ulong_t)&rtw89_8852cu_info },
{ USB_DEVICE_AND_INTERFACE_INFO(0x35bc, 0x0102, 0xff, 0xff, 0xff),
.driver_info = (kernel_ulong_t)&rtw89_8852cu_info },
{ USB_DEVICE_AND_INTERFACE_INFO(0x37ad, 0x0103, 0xff, 0xff, 0xff),
.driver_info = (kernel_ulong_t)&rtw89_8852cu_info },
{},
};
MODULE_DEVICE_TABLE(usb, rtw_8852cu_id_table);

18
drivers/net/wireless/realtek/rtw89/rtw8922a.c
View File

@ -18,7 +18,7 @@
#define RTW8922A_FW_FORMAT_MAX 4
#define RTW8922A_FW_BASENAME "rtw89/rtw8922a_fw"
#define RTW8922A_MODULE_FIRMWARE \
RTW8922A_FW_BASENAME "-" __stringify(RTW8922A_FW_FORMAT_MAX) ".bin"
RTW89_GEN_MODULE_FWNAME(RTW8922A_FW_BASENAME, RTW8922A_FW_FORMAT_MAX)
#define HE_N_USER_MAX_8922A 4
@ -492,7 +492,7 @@ static int rtw8922a_pwr_off_func(struct rtw89_dev *rtwdev)
return ret;
rtw89_write32(rtwdev, R_BE_WLLPS_CTRL, 0x0000A1B2);
rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_XTAL_OFF_A_DIE);
rtw89_write32_clr(rtwdev, R_BE_SYS_PW_CTRL, B_BE_XTAL_OFF_A_DIE);
rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFM_SWLPS);
rtw89_write32(rtwdev, R_BE_UDM1, 0);
@ -2916,8 +2916,11 @@ const struct rtw89_chip_info rtw8922a_chip_info = {
.ops = &rtw8922a_chip_ops,
.mac_def = &rtw89_mac_gen_be,
.phy_def = &rtw89_phy_gen_be,
.fw_basename = RTW8922A_FW_BASENAME,
.fw_format_max = RTW8922A_FW_FORMAT_MAX,
.fw_def = {
.fw_basename = RTW8922A_FW_BASENAME,
.fw_format_max = RTW8922A_FW_FORMAT_MAX,
.fw_b_aid = 0,
},
.try_ce_fw = false,
.bbmcu_nr = 1,
.needed_fw_elms = RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS,
@ -2972,7 +2975,7 @@ const struct rtw89_chip_info rtw8922a_chip_info = {
.support_noise = false,
.ul_tb_waveform_ctrl = false,
.ul_tb_pwr_diff = false,
.rx_freq_frome_ie = false,
.rx_freq_from_ie = false,
.hw_sec_hdr = true,
.hw_mgmt_tx_encrypt = true,
.hw_tkip_crypto = true,
@ -3012,6 +3015,10 @@ const struct rtw89_chip_info rtw8922a_chip_info = {
.rf_para_ulink = rtw89_btc_8922a_rf_ul,
.rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8922a_rf_dl),
.rf_para_dlink = rtw89_btc_8922a_rf_dl,
.rf_para_ulink_v9 = NULL,
.rf_para_dlink_v9 = NULL,
.rf_para_ulink_num_v9 = 0,
.rf_para_dlink_num_v9 = 0,
.ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) |
BIT(RTW89_PS_MODE_CLK_GATED) |
BIT(RTW89_PS_MODE_PWR_GATED),
@ -3057,6 +3064,7 @@ EXPORT_SYMBOL(rtw8922a_chip_info);
const struct rtw89_chip_variant rtw8922ae_vs_variant = {
.no_mcs_12_13 = true,
.fw_min_ver_code = RTW89_FW_VER_CODE(0, 35, 54, 0),
.fw_def_override = NULL,
};
EXPORT_SYMBOL(rtw8922ae_vs_variant);

3093
drivers/net/wireless/realtek/rtw89/rtw8922d.c Normal file
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83
drivers/net/wireless/realtek/rtw89/rtw8922d.h Normal file
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@ -0,0 +1,83 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2026 Realtek Corporation
*/
#ifndef __RTW89_8922D_H__
#define __RTW89_8922D_H__
#include "core.h"
#define RF_PATH_NUM_8922D 2
#define BB_PATH_NUM_8922D 2
struct rtw8922d_tssi_offset {
u8 cck_tssi[TSSI_CCK_CH_GROUP_NUM];
u8 bw40_tssi[TSSI_MCS_2G_CH_GROUP_NUM];
u8 rsvd[7];
u8 bw40_1s_tssi_5g[TSSI_MCS_5G_CH_GROUP_NUM];
u8 bw_diff_5g[10];
} __packed;
struct rtw8922d_tssi_offset_6g {
u8 bw40_1s_tssi_6g[TSSI_MCS_6G_CH_GROUP_NUM];
u8 rsvd[0xa];
} __packed;
struct rtw8922d_rx_gain {
u8 _2g_ofdm;
u8 _2g_cck;
u8 _5g_low;
u8 _5g_mid;
u8 _5g_high;
} __packed;
struct rtw8922d_rx_gain_6g {
u8 _6g_l0;
u8 _6g_l1;
u8 _6g_m0;
u8 _6g_m1;
u8 _6g_h0;
u8 _6g_h1;
u8 _6g_uh0;
u8 _6g_uh1;
} __packed;
struct rtw8922d_efuse {
u8 country_code[2];
u8 rsvd[0xe];
struct rtw8922d_tssi_offset path_a_tssi;
struct rtw8922d_tssi_offset path_b_tssi;
u8 rsvd1[0x54];
u8 channel_plan;
u8 xtal_k;
u8 rsvd2[0x7];
u8 board_info;
u8 rsvd3[0x8];
u8 rfe_type;
u8 rsvd4[2];
u8 bt_setting_2;
u8 bt_setting_3;
u8 rsvd4_2;
u8 path_a_therm;
u8 path_b_therm;
u8 rsvd5[0x2];
struct rtw8922d_rx_gain rx_gain_a;
struct rtw8922d_rx_gain rx_gain_b;
u8 rsvd6[0x18];
struct rtw8922d_rx_gain rx_gain_a_2;
struct rtw8922d_rx_gain rx_gain_b_2;
struct rtw8922d_tssi_offset_6g path_a_tssi_6g;
struct rtw8922d_tssi_offset_6g path_b_tssi_6g;
struct rtw8922d_tssi_offset_6g path_c_tssi_6g;
struct rtw8922d_tssi_offset_6g path_d_tssi_6g;
struct rtw8922d_rx_gain_6g rx_gain_6g_a;
struct rtw8922d_rx_gain_6g rx_gain_6g_b;
u8 rsvd7[0x5a];
struct rtw8922d_rx_gain_6g rx_gain_6g_a_2;
struct rtw8922d_rx_gain_6g rx_gain_6g_b_2;
} __packed;
extern const struct rtw89_chip_info rtw8922d_chip_info;
extern const struct rtw89_chip_variant rtw8922de_vs_variant;
#endif

372
drivers/net/wireless/realtek/rtw89/rtw8922d_rfk.c Normal file
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@ -0,0 +1,372 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/* Copyright(c) 2026 Realtek Corporation
*/
#include "chan.h"
#include "debug.h"
#include "phy.h"
#include "reg.h"
#include "rtw8922d.h"
#include "rtw8922d_rfk.h"
static const struct rtw89_reg5_def rtw8922d_nctl_post_defs[] = {
RTW89_DECL_RFK_WM(0x20c7c, 0x00e00000, 0x1),
};
RTW89_DECLARE_RFK_TBL(rtw8922d_nctl_post_defs);
static void rtw8922d_tssi_cont_en(struct rtw89_dev *rtwdev, bool en,
enum rtw89_rf_path path, u8 phy_idx)
{
static const u32 tssi_trk_man[2] = {R_TSSI_EN_P0_BE4,
R_TSSI_EN_P0_BE4 + 0x100};
if (en)
rtw89_phy_write32_idx(rtwdev, tssi_trk_man[path],
B_TSSI_CONT_EN, 0, phy_idx);
else
rtw89_phy_write32_idx(rtwdev, tssi_trk_man[path],
B_TSSI_CONT_EN, 1, phy_idx);
}
void rtw8922d_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en, u8 phy_idx)
{
if (rtwdev->mlo_dbcc_mode == MLO_1_PLUS_1_1RF) {
if (phy_idx == RTW89_PHY_0)
rtw8922d_tssi_cont_en(rtwdev, en, RF_PATH_A, phy_idx);
else
rtw8922d_tssi_cont_en(rtwdev, en, RF_PATH_B, phy_idx);
} else {
rtw8922d_tssi_cont_en(rtwdev, en, RF_PATH_A, phy_idx);
rtw8922d_tssi_cont_en(rtwdev, en, RF_PATH_B, phy_idx);
}
}
static
void rtw8922d_ctl_band_ch_bw(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
const struct rtw89_chan *chan)
{
u8 synpath;
u32 rf18;
synpath = rtw89_phy_get_syn_sel(rtwdev, phy);
rf18 = rtw89_chip_chan_to_rf18_val(rtwdev, chan);
rtw89_write_rf(rtwdev, synpath, RR_RSV1, RFREG_MASK, 0x0);
rtw89_write_rf(rtwdev, synpath, RR_MOD, RFREG_MASK, 0x30000);
rtw89_write_rf(rtwdev, synpath, RR_CFGCH, RFREG_MASK, rf18);
fsleep(400);
rtw89_write_rf(rtwdev, synpath, RR_RSV1, RFREG_MASK, 0x1);
rtw89_write_rf(rtwdev, synpath, RR_CFGCH_V1, RFREG_MASK, rf18);
}
void rtw8922d_set_channel_rf(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan,
enum rtw89_phy_idx phy_idx)
{
rtw8922d_ctl_band_ch_bw(rtwdev, phy_idx, chan);
}
enum _rf_syn_pow {
RF_SYN_ON_OFF,
RF_SYN_OFF_ON,
RF_SYN_ALLON,
RF_SYN_ALLOFF,
};
static void rtw8922d_set_syn01(struct rtw89_dev *rtwdev, enum _rf_syn_pow syn)
{
rtw89_debug(rtwdev, RTW89_DBG_RFK, "SYN config=%d\n", syn);
if (syn == RF_SYN_ALLON) {
rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, BIT(1), 0x0);
rtw89_write_rf(rtwdev, RF_PATH_B, RR_MOD, BIT(1), 0x0);
rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, MASKDWORD, 0x0);
rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, MASKDWORD, 0x0);
rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN_V1, 0xf);
rtw89_write_rf(rtwdev, RF_PATH_B, RR_POW, RR_POW_SYN_V1, 0xf);
rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, MASKDWORD, 0x1);
rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, MASKDWORD, 0x1);
} else if (syn == RF_SYN_ON_OFF) {
rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, BIT(1), 0x0);
rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, MASKDWORD, 0x0);
rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN_V1, 0xf);
rtw89_write_rf(rtwdev, RF_PATH_B, RR_POW, RR_POW_SYN_V1, 0x0);
rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, MASKDWORD, 0x1);
} else if (syn == RF_SYN_OFF_ON) {
rtw89_write_rf(rtwdev, RF_PATH_B, RR_MOD, BIT(1), 0x0);
rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, MASKDWORD, 0x0);
rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN_V1, 0x0);
rtw89_write_rf(rtwdev, RF_PATH_B, RR_POW, RR_POW_SYN_V1, 0xf);
rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, MASKDWORD, 0x1);
} else if (syn == RF_SYN_ALLOFF) {
rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN_V1, 0x0);
rtw89_write_rf(rtwdev, RF_PATH_B, RR_POW, RR_POW_SYN_V1, 0x0);
}
}
static void rtw8922d_chlk_ktbl_sel(struct rtw89_dev *rtwdev, u8 kpath, u8 idx)
{
bool mlo_linking = false;
if (idx > 2) {
rtw89_warn(rtwdev, "[DBCC][ERROR]indx is out of limit!! index(%d)", idx);
return;
}
if (mlo_linking) {
if (kpath & RF_A) {
rtw89_write_rf(rtwdev, RF_PATH_A, RR_MODOPT, RR_SW_SEL, 0x0);
rtw89_write_rf(rtwdev, RF_PATH_A, RR_MODOPT_V1, RR_SW_SEL, 0x0);
}
if (kpath & RF_B) {
rtw89_write_rf(rtwdev, RF_PATH_B, RR_MODOPT, RR_SW_SEL, 0x0);
rtw89_write_rf(rtwdev, RF_PATH_B, RR_MODOPT_V1, RR_SW_SEL, 0x0);
}
return;
}
if (kpath & RF_A) {
rtw89_phy_write32_mask(rtwdev, R_KTBL0A_BE4, B_KTBL0_RST, 0x1);
rtw89_phy_write32_mask(rtwdev, R_KTBL0A_BE4, B_KTBL0_IDX0, idx);
rtw89_phy_write32_mask(rtwdev, R_KTBL0A_BE4, B_KTBL0_IDX1, idx);
rtw89_write_rf(rtwdev, RF_PATH_A, RR_MODOPT, RR_TXG_SEL, 0x4 | idx);
rtw89_write_rf(rtwdev, RF_PATH_A, RR_MODOPT_V1, RR_TXG_SEL, 0x4 | idx);
rtw89_phy_write32_mask(rtwdev, R_KTBL1A_BE4, B_KTBL1_TBL0, idx & BIT(0));
rtw89_phy_write32_mask(rtwdev, R_KTBL1A_BE4, B_KTBL1_TBL1, (idx & BIT(1)) >> 1);
}
if (kpath & RF_B) {
rtw89_phy_write32_mask(rtwdev, R_KTBL0B_BE4, B_KTBL0_RST, 0x1);
rtw89_phy_write32_mask(rtwdev, R_KTBL0B_BE4, B_KTBL0_IDX0, idx);
rtw89_phy_write32_mask(rtwdev, R_KTBL0B_BE4, B_KTBL0_IDX1, idx);
rtw89_write_rf(rtwdev, RF_PATH_B, RR_MODOPT, RR_TXG_SEL, 0x4 | idx);
rtw89_write_rf(rtwdev, RF_PATH_B, RR_MODOPT_V1, RR_TXG_SEL, 0x4 | idx);
rtw89_phy_write32_mask(rtwdev, R_KTBL1B_BE4, B_KTBL1_TBL0, idx & BIT(0));
rtw89_phy_write32_mask(rtwdev, R_KTBL1B_BE4, B_KTBL1_TBL1, (idx & BIT(1)) >> 1);
}
}
static u8 rtw8922d_chlk_reload_sel_tbl(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan, u8 path)
{
struct rtw89_rfk_mcc_info_data *rfk_mcc = rtwdev->rfk_mcc.data;
struct rtw89_rfk_chan_desc desc[__RTW89_RFK_CHS_NR_V1] = {};
u8 tbl_sel;
for (tbl_sel = 0; tbl_sel < ARRAY_SIZE(desc); tbl_sel++) {
struct rtw89_rfk_chan_desc *p = &desc[tbl_sel];
p->ch = rfk_mcc->ch[tbl_sel];
p->has_band = true;
p->band = rfk_mcc->band[tbl_sel];
p->has_bw = true;
p->bw = rfk_mcc->bw[tbl_sel];
}
tbl_sel = rtw89_rfk_chan_lookup(rtwdev, desc, ARRAY_SIZE(desc), chan);
rfk_mcc->ch[tbl_sel] = chan->channel;
rfk_mcc->band[tbl_sel] = chan->band_type;
rfk_mcc->bw[tbl_sel] = chan->band_width;
rfk_mcc->rf18[tbl_sel] = rtw89_chip_chan_to_rf18_val(rtwdev, chan);
/* shared table array, but tbl_sel can be independent by path */
rfk_mcc[path].table_idx = tbl_sel;
return tbl_sel;
}
static void rtw8922d_chlk_reload(struct rtw89_dev *rtwdev)
{
const struct rtw89_chan *chan0, *chan1;
u8 s0_tbl, s1_tbl;
switch (rtwdev->mlo_dbcc_mode) {
default:
case MLO_2_PLUS_0_1RF:
chan0 = rtw89_mgnt_chan_get(rtwdev, 0);
chan1 = chan0;
break;
case MLO_0_PLUS_2_1RF:
chan1 = rtw89_mgnt_chan_get(rtwdev, 1);
chan0 = chan1;
break;
case MLO_1_PLUS_1_1RF:
chan0 = rtw89_mgnt_chan_get(rtwdev, 0);
chan1 = rtw89_mgnt_chan_get(rtwdev, 1);
break;
}
s0_tbl = rtw8922d_chlk_reload_sel_tbl(rtwdev, chan0, 0);
s1_tbl = rtw8922d_chlk_reload_sel_tbl(rtwdev, chan1, 1);
rtw8922d_chlk_ktbl_sel(rtwdev, RF_A, s0_tbl);
rtw8922d_chlk_ktbl_sel(rtwdev, RF_B, s1_tbl);
}
static enum _rf_syn_pow rtw8922d_get_syn_pow(struct rtw89_dev *rtwdev)
{
switch (rtwdev->mlo_dbcc_mode) {
case MLO_0_PLUS_2_1RF:
return RF_SYN_OFF_ON;
case MLO_0_PLUS_2_2RF:
case MLO_1_PLUS_1_2RF:
case MLO_2_PLUS_0_1RF:
case MLO_2_PLUS_0_2RF:
case MLO_2_PLUS_2_2RF:
case MLO_DBCC_NOT_SUPPORT:
default:
return RF_SYN_ON_OFF;
case MLO_1_PLUS_1_1RF:
case DBCC_LEGACY:
return RF_SYN_ALLON;
}
}
void rtw8922d_rfk_mlo_ctrl(struct rtw89_dev *rtwdev)
{
enum _rf_syn_pow syn_pow = rtw8922d_get_syn_pow(rtwdev);
if (!rtwdev->dbcc_en)
goto set_rfk_reload;
rtw8922d_set_syn01(rtwdev, syn_pow);
set_rfk_reload:
rtw8922d_chlk_reload(rtwdev);
}
static void rtw8922d_x4k_setting(struct rtw89_dev *rtwdev)
{
u32 val;
val = rtw89_read_rf(rtwdev, RF_PATH_A, 0xB9, 0xF000);
rtw89_write_rf(rtwdev, RF_PATH_A, 0xB9, 0xF000, val);
val = rtw89_read_rf(rtwdev, RF_PATH_B, 0xB9, 0xF000);
rtw89_write_rf(rtwdev, RF_PATH_B, 0xB9, 0xF000, val);
rtw89_write_rf(rtwdev, RF_PATH_A, 0xC2, BIT(19), 0x1);
rtw89_write_rf(rtwdev, RF_PATH_B, 0xC2, BIT(19), 0x1);
}
void rtw8922d_rfk_hw_init(struct rtw89_dev *rtwdev)
{
rtw8922d_x4k_setting(rtwdev);
}
void rtw8922d_pre_set_channel_rf(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
{
bool mlo_1_1;
if (!rtwdev->dbcc_en)
return;
mlo_1_1 = rtw89_is_mlo_1_1(rtwdev);
if (mlo_1_1)
rtw8922d_set_syn01(rtwdev, RF_SYN_ALLON);
else if (phy_idx == RTW89_PHY_0)
rtw8922d_set_syn01(rtwdev, RF_SYN_ON_OFF);
else
rtw8922d_set_syn01(rtwdev, RF_SYN_OFF_ON);
fsleep(1000);
}
void rtw8922d_post_set_channel_rf(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
{
rtw8922d_rfk_mlo_ctrl(rtwdev);
}
static u8 _get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
{
rtw89_write_rf(rtwdev, path, RR_TM, RR_TM_TRI, 0x1);
rtw89_write_rf(rtwdev, path, RR_TM, RR_TM_TRI, 0x0);
rtw89_write_rf(rtwdev, path, RR_TM, RR_TM_TRI, 0x1);
fsleep(200);
return rtw89_read_rf(rtwdev, path, RR_TM, RR_TM_VAL_V1);
}
static void _lck_keep_thermal(struct rtw89_dev *rtwdev)
{
struct rtw89_lck_info *lck = &rtwdev->lck;
int path;
for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
lck->thermal[path] = _get_thermal(rtwdev, path);
rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
"[LCK] path=%d thermal=0x%x", path, lck->thermal[path]);
}
}
static void _lck(struct rtw89_dev *rtwdev)
{
enum _rf_syn_pow syn_pow = rtw8922d_get_syn_pow(rtwdev);
u8 path_mask = 0;
u32 tmp18, tmp5;
int path;
rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, "[LCK] DO LCK\n");
if (syn_pow == RF_SYN_ALLON)
path_mask = BIT(RF_PATH_A) | BIT(RF_PATH_B);
else if (syn_pow == RF_SYN_ON_OFF)
path_mask = BIT(RF_PATH_A);
else if (syn_pow == RF_SYN_OFF_ON)
path_mask = BIT(RF_PATH_B);
else
return;
for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
if (!(path_mask & BIT(path)))
continue;
tmp18 = rtw89_read_rf(rtwdev, path, RR_CFGCH, MASKDWORD);
tmp5 = rtw89_read_rf(rtwdev, path, RR_RSV1, MASKDWORD);
rtw89_write_rf(rtwdev, path, RR_MOD, MASKDWORD, 0x10000);
rtw89_write_rf(rtwdev, path, RR_RSV1, MASKDWORD, 0x0);
rtw89_write_rf(rtwdev, path, RR_LCK_TRG, RR_LCK_TRGSEL, 0x1);
rtw89_write_rf(rtwdev, path, RR_CFGCH, MASKDWORD, tmp18);
rtw89_write_rf(rtwdev, path, RR_LCK_TRG, RR_LCK_TRGSEL, 0x0);
fsleep(400);
rtw89_write_rf(rtwdev, path, RR_RSV1, MASKDWORD, tmp5);
}
_lck_keep_thermal(rtwdev);
}
#define RTW8922D_LCK_TH 16
void rtw8922d_lck_track(struct rtw89_dev *rtwdev)
{
struct rtw89_lck_info *lck = &rtwdev->lck;
u8 cur_thermal;
int delta;
int path;
for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
cur_thermal = _get_thermal(rtwdev, path);
delta = abs((int)cur_thermal - lck->thermal[path]);
rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
"[LCK] path=%d current thermal=0x%x delta=0x%x\n",
path, cur_thermal, delta);
if (delta >= RTW8922D_LCK_TH) {
_lck(rtwdev);
return;
}
}
}

22
drivers/net/wireless/realtek/rtw89/rtw8922d_rfk.h Normal file
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@ -0,0 +1,22 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2026 Realtek Corporation
*/
#ifndef __RTW89_8922D_RFK_H__
#define __RTW89_8922D_RFK_H__
#include "core.h"
extern const struct rtw89_rfk_tbl rtw8922d_nctl_post_defs_tbl;
void rtw8922d_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en, u8 phy_idx);
void rtw8922d_set_channel_rf(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan,
enum rtw89_phy_idx phy_idx);
void rtw8922d_rfk_hw_init(struct rtw89_dev *rtwdev);
void rtw8922d_rfk_mlo_ctrl(struct rtw89_dev *rtwdev);
void rtw8922d_pre_set_channel_rf(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
void rtw8922d_post_set_channel_rf(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
void rtw8922d_lck_track(struct rtw89_dev *rtwdev);
#endif

119
drivers/net/wireless/realtek/rtw89/rtw8922de.c Normal file
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// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/* Copyright(c) 2026 Realtek Corporation
*/
#include <linux/module.h>
#include <linux/pci.h>
#include "pci.h"
#include "reg.h"
#include "rtw8922d.h"
static const struct rtw89_pci_info rtw8922d_pci_info = {
.gen_def = &rtw89_pci_gen_be,
.isr_def = &rtw89_pci_isr_be_v1,
.txbd_trunc_mode = MAC_AX_BD_TRUNC,
.rxbd_trunc_mode = MAC_AX_BD_TRUNC,
.rxbd_mode = MAC_AX_RXBD_PKT,
.tag_mode = MAC_AX_TAG_MULTI,
.tx_burst = MAC_AX_TX_BURST_V1_256B,
.rx_burst = MAC_AX_RX_BURST_V1_128B,
.wd_dma_idle_intvl = MAC_AX_WD_DMA_INTVL_256NS,
.wd_dma_act_intvl = MAC_AX_WD_DMA_INTVL_256NS,
.multi_tag_num = MAC_AX_TAG_NUM_8,
.lbc_en = MAC_AX_PCIE_ENABLE,
.lbc_tmr = MAC_AX_LBC_TMR_2MS,
.autok_en = MAC_AX_PCIE_DISABLE,
.io_rcy_en = MAC_AX_PCIE_ENABLE,
.io_rcy_tmr = MAC_AX_IO_RCY_ANA_TMR_DEF,
.rx_ring_eq_is_full = true,
.check_rx_tag = true,
.no_rxbd_fs = true,
.group_bd_addr = true,
.rpp_fmt_size = sizeof(struct rtw89_pci_rpp_fmt_v1),
.init_cfg_reg = R_BE_HAXI_INIT_CFG1,
.txhci_en_bit = B_BE_TXDMA_EN,
.rxhci_en_bit = B_BE_RXDMA_EN,
.rxbd_mode_bit = B_BE_RXQ_RXBD_MODE_MASK,
.exp_ctrl_reg = R_BE_HAXI_EXP_CTRL_V1,
.max_tag_num_mask = B_BE_MAX_TAG_NUM_MASK,
.rxbd_rwptr_clr_reg = R_BE_RXBD_RWPTR_CLR1_V1,
.txbd_rwptr_clr2_reg = R_BE_TXBD_RWPTR_CLR1,
.dma_io_stop = {R_BE_HAXI_INIT_CFG1, B_BE_STOP_AXI_MST},
.dma_stop1 = {R_BE_HAXI_DMA_STOP1, B_BE_TX_STOP1_MASK_V1},
.dma_stop2 = {0},
.dma_busy1 = {R_BE_HAXI_DMA_BUSY1, DMA_BUSY1_CHECK_BE_V1},
.dma_busy2_reg = 0,
.dma_busy3_reg = R_BE_HAXI_DMA_BUSY1,
.rpwm_addr = R_BE_PCIE_HRPWM,
.cpwm_addr = R_BE_PCIE_CRPWM,
.mit_addr = R_BE_PCIE_MIT_CH_EN,
.wp_sel_addr = R_BE_WP_ADDR_H_SEL0_3_V1,
.tx_dma_ch_mask = BIT(RTW89_TXCH_ACH1) | BIT(RTW89_TXCH_ACH3) |
BIT(RTW89_TXCH_ACH5) | BIT(RTW89_TXCH_ACH7) |
BIT(RTW89_TXCH_CH9) | BIT(RTW89_TXCH_CH11),
.bd_idx_addr_low_power = NULL,
.dma_addr_set = &rtw89_pci_ch_dma_addr_set_be_v1,
.bd_ram_table = NULL,
.ltr_set = rtw89_pci_ltr_set_v2,
.fill_txaddr_info = rtw89_pci_fill_txaddr_info_v1,
.parse_rpp = rtw89_pci_parse_rpp_v1,
.config_intr_mask = rtw89_pci_config_intr_mask_v3,
.enable_intr = rtw89_pci_enable_intr_v3,
.disable_intr = rtw89_pci_disable_intr_v3,
.recognize_intrs = rtw89_pci_recognize_intrs_v3,
.ssid_quirks = NULL,
};
static const struct rtw89_driver_info rtw89_8922de_vs_info = {
.chip = &rtw8922d_chip_info,
.variant = &rtw8922de_vs_variant,
.quirks = NULL,
.bus = {
.pci = &rtw8922d_pci_info,
},
};
static const struct rtw89_driver_info rtw89_8922de_info = {
.chip = &rtw8922d_chip_info,
.variant = NULL,
.quirks = NULL,
.bus = {
.pci = &rtw8922d_pci_info,
},
};
static const struct pci_device_id rtw89_8922de_id_table[] = {
{
PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x892D),
.driver_data = (kernel_ulong_t)&rtw89_8922de_vs_info,
},
{
PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x882D),
.driver_data = (kernel_ulong_t)&rtw89_8922de_vs_info,
},
{
PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x895D),
.driver_data = (kernel_ulong_t)&rtw89_8922de_info,
},
{},
};
MODULE_DEVICE_TABLE(pci, rtw89_8922de_id_table);
static struct pci_driver rtw89_8922de_driver = {
.name = "rtw89_8922de",
.id_table = rtw89_8922de_id_table,
.probe = rtw89_pci_probe,
.remove = rtw89_pci_remove,
.driver.pm = &rtw89_pm_ops_be,
.err_handler = &rtw89_pci_err_handler,
};
module_pci_driver(rtw89_8922de_driver);
MODULE_AUTHOR("Realtek Corporation");
MODULE_DESCRIPTION("Realtek 802.11be wireless 8922DE/8922DE-VS driver");
MODULE_LICENSE("Dual BSD/GPL");

4
drivers/net/wireless/realtek/rtw89/ser.c
View File

@ -498,6 +498,7 @@ static void ser_reset_trx_st_hdl(struct rtw89_ser *ser, u8 evt)
switch (evt) {
case SER_EV_STATE_IN:
wiphy_lock(wiphy);
ser->sw_cnt.l1++;
wiphy_delayed_work_cancel(wiphy, &rtwdev->track_work);
wiphy_delayed_work_cancel(wiphy, &rtwdev->track_ps_work);
wiphy_unlock(wiphy);
@ -588,7 +589,7 @@ static void ser_mac_mem_dump(struct rtw89_dev *rtwdev, u8 *buf,
start_page = start_addr / mem_page_size;
residue = start_addr % mem_page_size;
base_addr = mac->mem_base_addrs[sel];
base_addr = rtw89_mac_mem_base_addrs(rtwdev, sel);
base_addr += start_page * mem_page_size;
while (cnt < len) {
@ -730,6 +731,7 @@ static void ser_l2_reset_st_hdl(struct rtw89_ser *ser, u8 evt)
switch (evt) {
case SER_EV_STATE_IN:
wiphy_lock(rtwdev->hw->wiphy);
ser->sw_cnt.l2++;
ser_l2_reset_st_pre_hdl(ser);
wiphy_unlock(rtwdev->hw->wiphy);

107
drivers/net/wireless/realtek/rtw89/usb.c
View File

@ -161,16 +161,24 @@ static u32
rtw89_usb_ops_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev,
u8 txch)
{
struct rtw89_usb *rtwusb = rtw89_usb_priv(rtwdev);
int inflight;
if (txch == RTW89_TXCH_CH12)
return 1;
return 42; /* TODO some kind of calculation? */
inflight = atomic_read(&rtwusb->tx_inflight[txch]);
if (inflight >= RTW89_USB_MAX_TX_URBS_PER_CH)
return 0;
return RTW89_USB_MAX_TX_URBS_PER_CH - inflight;
}
static void rtw89_usb_write_port_complete(struct urb *urb)
{
struct rtw89_usb_tx_ctrl_block *txcb = urb->context;
struct rtw89_dev *rtwdev = txcb->rtwdev;
struct rtw89_usb *rtwusb = rtw89_usb_priv(rtwdev);
struct ieee80211_tx_info *info;
struct rtw89_txwd_body *txdesc;
struct sk_buff *skb;
@ -229,6 +237,8 @@ static void rtw89_usb_write_port_complete(struct urb *urb)
break;
}
atomic_dec(&rtwusb->tx_inflight[txcb->txch]);
kfree(txcb);
}
@ -306,9 +316,13 @@ static void rtw89_usb_ops_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch)
skb_queue_tail(&txcb->tx_ack_queue, skb);
atomic_inc(&rtwusb->tx_inflight[txch]);
ret = rtw89_usb_write_port(rtwdev, txch, skb->data, skb->len,
txcb);
if (ret) {
atomic_dec(&rtwusb->tx_inflight[txch]);
if (ret != -ENODEV)
rtw89_err(rtwdev, "write port txch %d failed: %d\n",
txch, ret);
@ -408,11 +422,14 @@ static int rtw89_usb_ops_tx_write(struct rtw89_dev *rtwdev,
static void rtw89_usb_rx_handler(struct work_struct *work)
{
struct rtw89_usb *rtwusb = container_of(work, struct rtw89_usb, rx_work);
const struct rtw89_usb_info *info = rtwusb->info;
struct rtw89_dev *rtwdev = rtwusb->rtwdev;
struct rtw89_rx_desc_info desc_info;
s32 aligned_offset, remaining;
struct sk_buff *rx_skb;
struct sk_buff *skb;
u32 pkt_offset;
u8 *pkt_ptr;
int limit;
for (limit = 0; limit < 200; limit++) {
@ -425,23 +442,38 @@ static void rtw89_usb_rx_handler(struct work_struct *work)
goto free_or_reuse;
}
memset(&desc_info, 0, sizeof(desc_info));
rtw89_chip_query_rxdesc(rtwdev, &desc_info, rx_skb->data, 0);
pkt_ptr = rx_skb->data;
remaining = rx_skb->len;
skb = rtw89_alloc_skb_for_rx(rtwdev, desc_info.pkt_size);
if (!skb) {
rtw89_debug(rtwdev, RTW89_DBG_HCI,
"failed to allocate RX skb of size %u\n",
desc_info.pkt_size);
goto free_or_reuse;
}
do {
memset(&desc_info, 0, sizeof(desc_info));
rtw89_chip_query_rxdesc(rtwdev, &desc_info, pkt_ptr, 0);
pkt_offset = desc_info.offset + desc_info.rxd_len;
pkt_offset = desc_info.offset + desc_info.rxd_len;
if (remaining < (pkt_offset + desc_info.pkt_size)) {
rtw89_debug(rtwdev, RTW89_DBG_HCI,
"Failed to get remaining RX pkt %u > %u\n",
pkt_offset + desc_info.pkt_size, remaining);
goto free_or_reuse;
}
skb_put_data(skb, rx_skb->data + pkt_offset,
desc_info.pkt_size);
skb = rtw89_alloc_skb_for_rx(rtwdev, desc_info.pkt_size);
if (!skb) {
rtw89_debug(rtwdev, RTW89_DBG_HCI,
"failed to allocate RX skb of size %u\n",
desc_info.pkt_size);
goto free_or_reuse;
}
rtw89_core_rx(rtwdev, &desc_info, skb);
skb_put_data(skb, pkt_ptr + pkt_offset, desc_info.pkt_size);
rtw89_core_rx(rtwdev, &desc_info, skb);
/* next frame */
pkt_offset += desc_info.pkt_size;
aligned_offset = ALIGN(pkt_offset, info->rx_agg_alignment);
pkt_ptr += aligned_offset;
remaining -= aligned_offset;
} while (remaining > 0);
free_or_reuse:
if (skb_queue_len(&rtwusb->rx_free_queue) >= RTW89_USB_RX_SKB_NUM)
@ -666,8 +698,10 @@ static void rtw89_usb_init_tx(struct rtw89_dev *rtwdev)
struct rtw89_usb *rtwusb = rtw89_usb_priv(rtwdev);
int i;
for (i = 0; i < ARRAY_SIZE(rtwusb->tx_queue); i++)
for (i = 0; i < ARRAY_SIZE(rtwusb->tx_queue); i++) {
skb_queue_head_init(&rtwusb->tx_queue[i]);
atomic_set(&rtwusb->tx_inflight[i], 0);
}
}
static void rtw89_usb_deinit_tx(struct rtw89_dev *rtwdev)
@ -745,6 +779,44 @@ static int rtw89_usb_ops_mac_pre_deinit(struct rtw89_dev *rtwdev)
return 0; /* Nothing to do. */
}
static void rtw89_usb_rx_agg_cfg_v1(struct rtw89_dev *rtwdev)
{
const u32 rxagg_0 = FIELD_PREP_CONST(B_AX_RXAGG_0_EN, 1) |
FIELD_PREP_CONST(B_AX_RXAGG_0_NUM_TH, 0) |
FIELD_PREP_CONST(B_AX_RXAGG_0_TIME_32US_TH, 32) |
FIELD_PREP_CONST(B_AX_RXAGG_0_BUF_SZ_4K, 5);
rtw89_write32(rtwdev, R_AX_RXAGG_0, rxagg_0);
}
static void rtw89_usb_rx_agg_cfg_v2(struct rtw89_dev *rtwdev)
{
const u32 rxagg_0 = FIELD_PREP_CONST(B_AX_RXAGG_0_EN, 1) |
FIELD_PREP_CONST(B_AX_RXAGG_0_NUM_TH, 255) |
FIELD_PREP_CONST(B_AX_RXAGG_0_TIME_32US_TH, 32) |
FIELD_PREP_CONST(B_AX_RXAGG_0_BUF_SZ_1K, 20);
rtw89_write32(rtwdev, R_AX_RXAGG_0_V1, rxagg_0);
rtw89_write32(rtwdev, R_AX_RXAGG_1_V1, 0x1F);
}
static void rtw89_usb_rx_agg_cfg(struct rtw89_dev *rtwdev)
{
switch (rtwdev->chip->chip_id) {
case RTL8851B:
case RTL8852A:
case RTL8852B:
rtw89_usb_rx_agg_cfg_v1(rtwdev);
break;
case RTL8852C:
rtw89_usb_rx_agg_cfg_v2(rtwdev);
break;
default:
rtw89_warn(rtwdev, "%s: USB RX agg not support\n", __func__);
return;
}
}
static int rtw89_usb_ops_mac_post_init(struct rtw89_dev *rtwdev)
{
struct rtw89_usb *rtwusb = rtw89_usb_priv(rtwdev);
@ -773,6 +845,8 @@ static int rtw89_usb_ops_mac_post_init(struct rtw89_dev *rtwdev)
rtw89_write8(rtwdev, info->usb_endpoint_2 + 1, NUMP);
}
rtw89_usb_rx_agg_cfg(rtwdev);
return 0;
}
@ -935,7 +1009,7 @@ static int rtw89_usb_intf_init(struct rtw89_dev *rtwdev,
if (!rtwusb->vendor_req_buf)
return -ENOMEM;
rtwusb->udev = usb_get_dev(interface_to_usbdev(intf));
rtwusb->udev = interface_to_usbdev(intf);
usb_set_intfdata(intf, rtwdev->hw);
@ -949,7 +1023,6 @@ static void rtw89_usb_intf_deinit(struct rtw89_dev *rtwdev,
{
struct rtw89_usb *rtwusb = rtw89_usb_priv(rtwdev);
usb_put_dev(rtwusb->udev);
kfree(rtwusb->vendor_req_buf);
usb_set_intfdata(intf, NULL);
}

15
drivers/net/wireless/realtek/rtw89/usb.h
View File

@ -20,6 +20,19 @@
#define RTW89_MAX_ENDPOINT_NUM 9
#define RTW89_MAX_BULKOUT_NUM 7
#define R_AX_RXAGG_0_V1 0x6000
#define B_AX_RXAGG_0_EN BIT(31)
#define B_AX_RXAGG_0_NUM_TH GENMASK(23, 16)
#define B_AX_RXAGG_0_TIME_32US_TH GENMASK(15, 8)
#define B_AX_RXAGG_0_BUF_SZ_1K GENMASK(7, 0)
#define R_AX_RXAGG_1_V1 0x6004
#define R_AX_RXAGG_0 0x8900
#define B_AX_RXAGG_0_BUF_SZ_4K GENMASK(7, 0)
#define RTW89_USB_MAX_TX_URBS_PER_CH 128
struct rtw89_usb_info {
u32 usb_host_request_2;
u32 usb_wlan0_1;
@ -27,6 +40,7 @@ struct rtw89_usb_info {
u32 usb3_mac_npi_config_intf_0;
u32 usb_endpoint_0;
u32 usb_endpoint_2;
u8 rx_agg_alignment;
u8 bulkout_id[RTW89_DMA_CH_NUM];
};
@ -63,6 +77,7 @@ struct rtw89_usb {
struct usb_anchor tx_submitted;
struct sk_buff_head tx_queue[RTW89_TXCH_NUM];
atomic_t tx_inflight[RTW89_TXCH_NUM];
};
static inline struct rtw89_usb *rtw89_usb_priv(struct rtw89_dev *rtwdev)

17
drivers/net/wireless/realtek/rtw89/util.h
View File

@ -6,6 +6,13 @@
#include "core.h"
#define RTW89_KEY_PN_0 GENMASK_ULL(7, 0)
#define RTW89_KEY_PN_1 GENMASK_ULL(15, 8)
#define RTW89_KEY_PN_2 GENMASK_ULL(23, 16)
#define RTW89_KEY_PN_3 GENMASK_ULL(31, 24)
#define RTW89_KEY_PN_4 GENMASK_ULL(39, 32)
#define RTW89_KEY_PN_5 GENMASK_ULL(47, 40)
#define rtw89_iterate_vifs_bh(rtwdev, iterator, data) \
ieee80211_iterate_active_interfaces_atomic((rtwdev)->hw, \
IEEE80211_IFACE_ITER_NORMAL, iterator, data)
@ -73,6 +80,16 @@ static inline void ether_addr_copy_mask(u8 *dst, const u8 *src, u8 mask)
}
}
static inline void ccmp_hdr2pn(s64 *pn, const u8 *hdr)
{
*pn = u64_encode_bits(hdr[0], RTW89_KEY_PN_0) |
u64_encode_bits(hdr[1], RTW89_KEY_PN_1) |
u64_encode_bits(hdr[4], RTW89_KEY_PN_2) |
u64_encode_bits(hdr[5], RTW89_KEY_PN_3) |
u64_encode_bits(hdr[6], RTW89_KEY_PN_4) |
u64_encode_bits(hdr[7], RTW89_KEY_PN_5);
}
s32 rtw89_linear_to_db_quarter(u64 val);
s32 rtw89_linear_to_db(u64 val);
u64 rtw89_db_quarter_to_linear(s32 db);

2
drivers/net/wireless/realtek/rtw89/wow.c
View File

@ -1741,6 +1741,8 @@ static int rtw89_wow_disable(struct rtw89_dev *rtwdev)
rtw89_wow_leave_ps(rtwdev, false);
rtw89_core_tid_rx_stats_reset(rtwdev);
ret = rtw89_wow_fw_stop(rtwdev);
if (ret) {
rtw89_err(rtwdev, "wow: failed to swap to normal fw\n");

7
drivers/net/wireless/realtek/rtw89/wow.h
View File

@ -8,13 +8,6 @@
#define RTW89_KEY_TKIP_PN_IV16 GENMASK_ULL(15, 0)
#define RTW89_KEY_TKIP_PN_IV32 GENMASK_ULL(47, 16)
#define RTW89_KEY_PN_0 GENMASK_ULL(7, 0)
#define RTW89_KEY_PN_1 GENMASK_ULL(15, 8)
#define RTW89_KEY_PN_2 GENMASK_ULL(23, 16)
#define RTW89_KEY_PN_3 GENMASK_ULL(31, 24)
#define RTW89_KEY_PN_4 GENMASK_ULL(39, 32)
#define RTW89_KEY_PN_5 GENMASK_ULL(47, 40)
#define RTW89_IGTK_IPN_0 GENMASK_ULL(7, 0)
#define RTW89_IGTK_IPN_1 GENMASK_ULL(15, 8)
#define RTW89_IGTK_IPN_2 GENMASK_ULL(23, 16)