From abb32edfc140b1c6cecc9bcc28fd0d3d0b833f91 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 5 Jul 2023 17:44:58 +0200 Subject: [PATCH 01/29] ARM: dts: stm32: remove shmem for scmi-optee on stm32mp15 Since the OP-TEE commit "plat-stm32mp1: scmi_server: default use OP-TEE shared memory", integrated in OP-TEE 3.22.0-rc1, the default configuration for STM32MP15x SoCs changes and CFG_STM32MP1_SCMI_SHM_SYSRAM is disabled by default and the OP-TEE SMCI server uses OP-TEE native shared memory registered by clients. To be compatible with this configuration and the next OP-TEE versions, this patch removes in the STM32MP15 SCMI device tree the SHMEM used by OP-TEE SCMI and the associated reserved memory in the last 4KByte page of SRAM. Fixes: ea3414e1249e ("ARM: dts: stm32: move SCMI related nodes in a dedicated file for stm32mp15") Signed-off-by: Patrick Delaunay Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp15-scmi.dtsi | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi b/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi index 543f24c2f4f6..ad2584213d99 100644 --- a/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi @@ -16,7 +16,6 @@ scmi: scmi { #address-cells = <1>; #size-cells = <0>; linaro,optee-channel-id = <0>; - shmem = <&scmi_shm>; scmi_clk: protocol@14 { reg = <0x14>; @@ -60,21 +59,6 @@ scmi_usb33: usb33@2 { }; }; }; - - soc { - scmi_sram: sram@2ffff000 { - compatible = "mmio-sram"; - reg = <0x2ffff000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x2ffff000 0x1000>; - - scmi_shm: scmi-sram@0 { - compatible = "arm,scmi-shmem"; - reg = <0 0x80>; - }; - }; - }; }; ®11 { From f0f0682c384d81bf25e6f8b23971fb8f69122f72 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 5 Jul 2023 17:44:59 +0200 Subject: [PATCH 02/29] ARM: dts: stm32: remove shmem for scmi-optee on stm32mp13 CFG_STM32MP1_SCMI_SHM_SYSRAM will be disabled by default for STM32MP13x SoCs in future OP-TEE version and the OP-TEE SMCI server uses only the OP-TEE native shared memory registered by clients. To be compatible by default with this configuration this patch removes the shared memory in the SCMI configuration and the associated reserved memory in SRAM. Fixes: 9005aeddd9fc ("ARM: dts: stm32: enable optee firmware and SCMI support on STM32MP13") Signed-off-by: Patrick Delaunay Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp131.dtsi | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi index d163c267e34c..d23bbc3639df 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -40,7 +40,6 @@ scmi: scmi { #address-cells = <1>; #size-cells = <0>; linaro,optee-channel-id = <0>; - shmem = <&scmi_shm>; scmi_clk: protocol@14 { reg = <0x14>; @@ -106,19 +105,6 @@ soc { interrupt-parent = <&intc>; ranges; - scmi_sram: sram@2ffff000 { - compatible = "mmio-sram"; - reg = <0x2ffff000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x2ffff000 0x1000>; - - scmi_shm: scmi-sram@0 { - compatible = "arm,scmi-shmem"; - reg = <0 0x80>; - }; - }; - timers2: timer@40000000 { #address-cells = <1>; #size-cells = <0>; From 099826ea21111a99f6bb8c1a31cd06daba2ccb9c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Leonard=20G=C3=B6hrs?= Date: Wed, 14 Jun 2023 14:32:18 +0200 Subject: [PATCH 03/29] dt-bindings: can: m_can: change from additional- to unevaluatedProperties MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This allows the usage of properties like termination-gpios and termination-ohms, which are specified in can-controller.yaml but were previously not usable due to additionalProperties: false. Signed-off-by: Leonard Göhrs Suggested-by: Rob Herring Acked-by: Rob Herring Reviewed-by: Chandrasekar Ramakrishnan Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/net/can/bosch,m_can.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml index 67879aab623b..76c5024b6423 100644 --- a/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml +++ b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml @@ -128,7 +128,7 @@ required: - clock-names - bosch,mram-cfg -additionalProperties: false +unevaluatedProperties: false examples: - | From 6d08cb0152a99ad8bd03d4b5205e4c4ade9652dc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Leonard=20G=C3=B6hrs?= Date: Wed, 14 Jun 2023 14:32:19 +0200 Subject: [PATCH 04/29] dt-bindings: net: dsa: microchip: add interrupts property for ksz switches MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The ksz switch driver allows specifying an interrupt line to prevent having to periodically poll the switch for link ups/downs and other asynchronous events. Signed-off-by: Leonard Göhrs Acked-by: Conor Dooley Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml b/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml index e51be1ac0362..03b5567be389 100644 --- a/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml +++ b/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml @@ -49,6 +49,9 @@ properties: Set if the output SYNCLKO clock should be disabled. Do not mix with microchip,synclko-125. + interrupts: + maxItems: 1 + required: - compatible - reg From d45cc9ea251eafbf645fdb8980da1d8390429e82 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Leonard=20G=C3=B6hrs?= Date: Wed, 14 Jun 2023 14:32:20 +0200 Subject: [PATCH 05/29] ARM: dts: stm32: Add pinmux groups for Linux Automation GmbH TAC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add pinmux groups required for the Linux Automation GmbH TAC. Signed-off-by: Leonard Göhrs Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi | 129 ++++++++++++++++++++ 1 file changed, 129 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi index 05c9c4f8064c..098153ee99a3 100644 --- a/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi @@ -6,6 +6,17 @@ #include &pinctrl { + adc1_ain_pins_a: adc1-ain-0 { + pins { + pinmux = , /* ADC1_INP2 */ + , /* ADC1_INP5 */ + , /* ADC1_INP9 */ + , /* ADC1_INP10 */ + , /* ADC1_INP13 */ + ; /* ADC1_INP15 */ + }; + }; + adc1_in6_pins_a: adc1-in6-0 { pins { pinmux = ; @@ -391,6 +402,46 @@ pins1 { }; }; + ethernet0_rgmii_pins_e: rgmii-4 { + pins1 { + pinmux = , /* ETH_RGMII_GTX_CLK */ + , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + ; /* ETH_RGMII_TX_CTL */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CLK */ + ; /* ETH_RGMII_RX_CTL */ + bias-disable; + }; + }; + + ethernet0_rgmii_sleep_pins_e: rgmii-sleep-4 { + pins1 { + pinmux = , /* ETH_RGMII_GTX_CLK */ + , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CLK */ + ; /* ETH_RGMII_RX_CTL */ + }; + }; + ethernet0_rmii_pins_a: rmii-0 { pins1 { pinmux = , /* ETH1_RMII_TXD0 */ @@ -1154,6 +1205,20 @@ pins { }; }; + pwm1_pins_c: pwm1-2 { + pins { + pinmux = ; /* TIM1_CH2 */ + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm1_sleep_pins_c: pwm1-sleep-2 { + pins { + pinmux = ; /* TIM1_CH2 */ + }; + }; + pwm2_pins_a: pwm2-0 { pins { pinmux = ; /* TIM2_CH4 */ @@ -1280,6 +1345,26 @@ pins { }; }; + pwm8_pins_b: pwm8-1 { + pins { + pinmux = , /* TIM8_CH1 */ + , /* TIM8_CH2 */ + , /* TIM8_CH3 */ + ; /* TIM8_CH4 */ + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm8_sleep_pins_b: pwm8-sleep-1 { + pins { + pinmux = , /* TIM8_CH1 */ + , /* TIM8_CH2 */ + , /* TIM8_CH3 */ + ; /* TIM8_CH4 */ + }; + }; + pwm12_pins_a: pwm12-0 { pins { pinmux = ; /* TIM12_CH1 */ @@ -2074,6 +2159,20 @@ pins2 { }; }; + spi2_pins_c: spi2-2 { + pins1 { + pinmux = , /* SPI2_SCK */ + ; /* SPI2_MOSI */ + bias-disable; + drive-push-pull; + }; + + pins2 { + pinmux = ; /* SPI2_MISO */ + bias-pull-down; + }; + }; + spi4_pins_a: spi4-0 { pins { pinmux = , /* SPI4_SCK */ @@ -2088,6 +2187,21 @@ pins2 { }; }; + spi5_pins_a: spi5-0 { + pins1 { + pinmux = , /* SPI5_SCK */ + ; /* SPI5_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = ; /* SPI5_MISO */ + bias-disable; + }; + }; + stusb1600_pins_a: stusb1600-0 { pins { pinmux = ; @@ -2578,6 +2692,21 @@ pins { }; }; + usart3_pins_f: usart3-5 { + pins1 { + pinmux = , /* USART3_TX */ + ; /* USART3_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART3_RX */ + ; /* USART3_CTS_NSS */ + bias-disable; + }; + }; + usbotg_hs_pins_a: usbotg-hs-0 { pins { pinmux = ; /* OTG_ID */ From e58944088cb01923f81b547809a8f332a30dc75b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Leonard=20G=C3=B6hrs?= Date: Wed, 14 Jun 2023 14:32:21 +0200 Subject: [PATCH 06/29] dt-bindings: arm: stm32: Add compatible string for Linux Automation LXA TAC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add DT compatible string for Linux Automation GmbH Test Automation Controllers (LXA TAC). LXA TACs are a development tool for embedded devices with a focus on embedded Linux devices. As of now there are two STM32MP157 based hardware generations (Gen 1 and Gen 2) that have most of their hardware config in common. In the future there will also be a STM32MP153 based hardware generation. Signed-off-by: Leonard Göhrs Acked-by: Conor Dooley Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index 4466b455bffa..4bf28e717a56 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -143,7 +143,9 @@ properties: - description: Octavo OSD32MP15x System-in-Package based boards items: - enum: - - lxa,stm32mp157c-mc1 # Linux Automation MC-1 + - lxa,stm32mp157c-mc1 # Linux Automation MC-1 + - lxa,stm32mp157c-tac-gen1 # Linux Automation TAC (Generation 1) + - lxa,stm32mp157c-tac-gen2 # Linux Automation TAC (Generation 2) - const: oct,stm32mp15xx-osd32 - enum: - st,stm32mp157 From 518272af37b218161dc321e5a11316fc72422f9c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Leonard=20G=C3=B6hrs?= Date: Wed, 14 Jun 2023 14:32:22 +0200 Subject: [PATCH 07/29] ARM: dts: stm32: lxa-tac: add Linux Automation GmbH TAC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Linux Automation Test Automation Controller (LXA TAC)[1] is an embedded software development tool built around the Octavo Systems OSD32MP15x SiP. The device contains an eMMC for storage, a DSA-capable on board ethernet switch with two external ports, dual CAN busses, a power switch to turn a device under test on or off and some other I/O. As of now there are two STM32MP157 based hardware generations (Gen 1 and Gen 2) that have most of their hardware config in common. In the future there will also be a STM32MP153 based hardware generation. [1]: https://www.linux-automation.com/en/products/lxa-tac.html Signed-off-by: Leonard Göhrs Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/Makefile | 2 + .../boot/dts/st/stm32mp157c-lxa-tac-gen1.dts | 93 +++ .../boot/dts/st/stm32mp157c-lxa-tac-gen2.dts | 172 +++++ arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi | 610 ++++++++++++++++++ 4 files changed, 877 insertions(+) create mode 100644 arch/arm/boot/dts/st/stm32mp157c-lxa-tac-gen1.dts create mode 100644 arch/arm/boot/dts/st/stm32mp157c-lxa-tac-gen2.dts create mode 100644 arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi diff --git a/arch/arm/boot/dts/st/Makefile b/arch/arm/boot/dts/st/Makefile index b3e9d29390e3..44b264c399ec 100644 --- a/arch/arm/boot/dts/st/Makefile +++ b/arch/arm/boot/dts/st/Makefile @@ -56,6 +56,8 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp157c-ev1.dtb \ stm32mp157c-ev1-scmi.dtb \ stm32mp157c-lxa-mc1.dtb \ + stm32mp157c-lxa-tac-gen1.dtb \ + stm32mp157c-lxa-tac-gen2.dtb \ stm32mp157c-odyssey.dtb \ stm32mp157c-phycore-stm32mp1-3.dtb dtb-$(CONFIG_ARCH_U8500) += \ diff --git a/arch/arm/boot/dts/st/stm32mp157c-lxa-tac-gen1.dts b/arch/arm/boot/dts/st/stm32mp157c-lxa-tac-gen1.dts new file mode 100644 index 000000000000..81f254fb88b0 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157c-lxa-tac-gen1.dts @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) 2020 STMicroelectronics - All Rights Reserved + * Copyright (C) 2021 Rouven Czerwinski, Pengutronix + * Copyright (C) 2023 Leonard Göhrs, Pengutronix + */ + +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15xc-lxa-tac.dtsi" + +/ { + model = "Linux Automation Test Automation Controller (TAC) Gen 1"; + compatible = "lxa,stm32mp157c-tac-gen1", "oct,stm32mp15xx-osd32", "st,stm32mp157"; + + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&v3v3>; + + brightness-levels = <0 31 63 95 127 159 191 223 255>; + default-brightness-level = <7>; + pwms = <&backlight_pwm 1 1000000 0>; + }; + + reg_iobus_12v: regulator-iobus-12v { + compatible = "regulator-fixed"; + vin-supply = <®_12v>; + + gpio = <&gpioh 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-max-microvolt = <12000000>; + regulator-min-microvolt = <12000000>; + regulator-name = "12V_IOBUS"; + }; +}; + +&gpioa { + gpio-line-names = "", "", "STACK_CS2", "", "STACK_CS3", /* 0 */ + "ETH_GPIO1", "ETH_INT", "", "", "", /* 5 */ + "", "", "", "BOOTROM_LED", "ETH_LAB_LEDRP", /* 10 */ + ""; /* 15 */ +}; + +&gpioc { + gpio-line-names = "", "STACK_CS1", "", "", "", /* 0 */ + "", "", "", "", "", /* 5 */ + "", ""; /* 10 */ +}; + +&gpu { + status = "disabled"; +}; + +&i2c1 { + powerboard_gpio: gpio@24 { + compatible = "nxp,pca9570"; + reg = <0x24>; + + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = "DUT_PWR_EN", "DUT_PWR_DISCH", "DUT_PWR_ADCRST", ""; + }; +}; + +&spi2 { + adc@0 { + compatible = "ti,lmp92064"; + reg = <0>; + spi-max-frequency = <5000000>; + vdd-supply = <®_pb_3v3>; + vdig-supply = <®_pb_3v3>; + reset-gpios = <&powerboard_gpio 2 GPIO_ACTIVE_HIGH>; + + shunt-resistor-micro-ohms = <15000>; + }; +}; + +&timers1 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; + + backlight_pwm: pwm { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pwm1_pins_c>; + pinctrl-1 = <&pwm1_sleep_pins_c>; + + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157c-lxa-tac-gen2.dts b/arch/arm/boot/dts/st/stm32mp157c-lxa-tac-gen2.dts new file mode 100644 index 000000000000..8a34d15e9005 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157c-lxa-tac-gen2.dts @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) 2020 STMicroelectronics - All Rights Reserved + * Copyright (C) 2021 Rouven Czerwinski, Pengutronix + * Copyright (C) 2023 Leonard Göhrs, Pengutronix + */ + +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15xc-lxa-tac.dtsi" + +/ { + model = "Linux Automation Test Automation Controller (TAC) Gen 2"; + compatible = "lxa,stm32mp157c-tac-gen2", "oct,stm32mp15xx-osd32", "st,stm32mp157"; + + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&v3v3>; + + brightness-levels = <0 31 63 95 127 159 191 223 255>; + default-brightness-level = <7>; + pwms = <&led_pwm 3 1000000 0>; + }; + + reg_iobus_12v: regulator-iobus-12v { + compatible = "regulator-fixed"; + vin-supply = <®_12v>; + gpio = <&gpioh 13 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <12000000>; + regulator-min-microvolt = <12000000>; + regulator-name = "12V_IOBUS"; + }; + + led-controller-1 { + compatible = "pwm-leds-multicolor"; + + multi-led { + color = ; + function = LED_FUNCTION_STATUS; + max-brightness = <65535>; + + led-red { + active-low; + color = ; + pwms = <&led_pwm 0 1000000 0>; + }; + + led-green { + active-low; + color = ; + pwms = <&led_pwm 2 1000000 0>; + }; + + led-blue { + active-low; + color = ; + pwms = <&led_pwm 1 1000000 0>; + }; + }; + }; + + led-controller-2 { + compatible = "gpio-leds"; + + led-5 { + label = "tac:green:iobus"; + gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>; + }; + + led-6 { + label = "tac:green:can"; + gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>; + }; + + led-7 { + label = "tac:green:out0"; + gpios = <&gpiob 8 GPIO_ACTIVE_HIGH>; + }; + + led-8 { + label = "tac:green:out1"; + gpios = <&gpiog 3 GPIO_ACTIVE_HIGH>; + }; + + led-9 { + label = "tac:green:uarttx"; + gpios = <&gpiod 3 GPIO_ACTIVE_HIGH>; + }; + + led-10 { + label = "tac:green:uartrx"; + gpios = <&gpiof 6 GPIO_ACTIVE_HIGH>; + }; + + led-11 { + label = "tac:green:usbh1"; + gpios = <&gpioc 8 GPIO_ACTIVE_HIGH>; + }; + + led-12 { + label = "tac:green:usbh2"; + gpios = <&gpiod 6 GPIO_ACTIVE_HIGH>; + }; + + led-13 { + label = "tac:green:usbh3"; + gpios = <&gpiob 9 GPIO_ACTIVE_HIGH>; + }; + + led-14 { + label = "tac:green:usbg"; + gpios = <&gpiod 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "usb-gadget"; + }; + + led-15 { + label = "tac:green:dutpwr"; + gpios = <&gpioa 15 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&gpioa { + gpio-line-names = "", "", "DUT_PWR_EN", "", "STACK_CS3", /* 0 */ + "ETH_GPIO1", "ETH_INT", "", "", "", /* 5 */ + "", "", "", "BOOTROM_LED", "ETH_LAB_LEDRP", /* 10 */ + ""; /* 15 */ +}; + +&gpioc { + gpio-line-names = "", "DUT_PWR_DISCH", "", "", "", /* 0 */ + "", "", "", "", "", /* 5 */ + "", ""; /* 10 */ +}; + +&gpu { + status = "disabled"; +}; + +&m_can2 { + termination-gpios = <&gpioe 4 GPIO_ACTIVE_HIGH>; + termination-ohms = <120>; +}; + +&spi2 { + adc@0 { + compatible = "ti,lmp92064"; + reg = <0>; + + reset-gpios = <&gpioa 4 GPIO_ACTIVE_HIGH>; + shunt-resistor-micro-ohms = <15000>; + spi-max-frequency = <5000000>; + vdd-supply = <®_pb_3v3>; + vdig-supply = <®_pb_3v3>; + }; +}; + +&timers8 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; + + led_pwm: pwm { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pwm8_pins_b>; + pinctrl-1 = <&pwm8_sleep_pins_b>; + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi b/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi new file mode 100644 index 000000000000..184b8bb4ebbf --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi @@ -0,0 +1,610 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) 2020 STMicroelectronics - All Rights Reserved + * Copyright (C) 2021 Rouven Czerwinski, Pengutronix + * Copyright (C) 2023 Leonard Göhrs, Pengutronix + */ + +#include "stm32mp15xc.dtsi" +#include "stm32mp15xx-osd32.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" + +#include +#include +#include +#include + +/ { + aliases { + ethernet0 = ðernet0; + ethernet1 = &port_uplink; + ethernet2 = &port_dut; + mmc1 = &sdmmc2; + serial0 = &uart4; + serial1 = &usart3; + }; + + chosen { + stdout-path = &uart4; + }; + + led-controller-0 { + compatible = "gpio-leds"; + + led-0 { + label = "tac:green:user1"; + gpios = <&gpiof 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + label = "tac:green:user2"; + gpios = <&gpiog 7 GPIO_ACTIVE_HIGH>; + }; + + led-2 { + label = "tac:green:statusdut"; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + }; + + /* led-3 and led-4 are internally connected antiparallel to one + * another inside the ethernet jack like this: + * GPIOA14 ---+---|led-3|>--+--- GPIOD15 + * +--<|led-4|---+ + * E.g. only one of the LEDs can be illuminated at a time while + * the other output must be driven low. + * This should likely be implemented using a multi color LED + * driver for antiparallel LEDs. + */ + led-3 { + label = "tac:green:statuslab"; + gpios = <&gpioa 14 GPIO_ACTIVE_HIGH>; + }; + + led-4 { + label = "tac:orange:statuslab"; + gpios = <&gpiod 15 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-lower { + label = "USER_BTN2"; + linux,code = ; + gpios = <&gpioe 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + + button-upper { + label = "USER_BTN"; + linux,code = ; + gpios = <&gpioi 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + }; + + /* supplied by either barrel connector or PoE */ + reg_12v: regulator-12v { + compatible = "regulator-fixed"; + regulator-name = "12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <®_12v>; + }; + + reg_1v2: regulator-1v2 { + compatible = "regulator-fixed"; + regulator-name = "1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + vin-supply = <®_5v>; + }; + + reg_pb_5v: regulator-pb-5v { + compatible = "regulator-fixed"; + regulator-name = "5V_POWERBOARD"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <®_5v>; + }; + + reg_pb_3v3: regulator-pb-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3_POWERBOARD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <®_pb_5v>; + }; + + output-iobus-12v { + compatible = "regulator-output"; + vout-supply = <®_iobus_12v>; + }; + + output-vuart { + compatible = "regulator-output"; + vout-supply = <&v3v3_hdmi>; + }; +}; + +baseboard_eeprom: &sip_eeprom { +}; + +&adc { + pinctrl-names = "default"; + pinctrl-0 = <&adc1_ain_pins_a>; + vdd-supply = <&vdd>; + vdda-supply = <&vdda>; + vref-supply = <&vrefbuf>; + status = "okay"; + + adc1: adc@0 { + st,adc-channels = <0 1 2 5 9 10 13 15>; + st,min-sample-time-nsecs = <5000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + channel@0 { + reg = <0>; + label = "HOST_2_CURR_FB"; + }; + + channel@1 { + reg = <1>; + label = "HOST_3_CURR_FB"; + }; + + channel@2 { + reg = <2>; + label = "OUT_0_FB"; + }; + + channel@5 { + reg = <5>; + label = "IOBUS_CURR_FB"; + }; + + channel@9 { + reg = <9>; + label = "IOBUS_VOLT_FB"; + }; + + channel@10 { + reg = <10>; + label = "OUT_1_FB"; + }; + + channel@13 { + reg = <13>; + label = "HOST_CURR_FB"; + }; + + channel@15 { + reg = <15>; + label = "HOST_1_CURR_FB"; + }; + }; + + adc2: adc@100 { + st,adc-channels = <12>; + st,min-sample-time-nsecs = <500000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + channel@12 { + reg = <12>; + label = "TEMP_INTERNAL"; + }; + }; +}; + +&crc1 { + status = "okay"; +}; + +&cryp1 { + status = "okay"; +}; + +&dts { + status = "okay"; +}; + +ðernet0 { + assigned-clocks = <&rcc ETHCK_K>, <&rcc PLL4_P>; + assigned-clock-parents = <&rcc PLL4_P>; + assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF */ + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ðernet0_rgmii_pins_e>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_e>; + + st,eth-clk-sel; + phy-mode = "rgmii-id"; + + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +ðernet0_rgmii_pins_e { + pins1 { + /* Reduce EMI emission by reducing RGMII drive strength */ + slew-rate = <1>; + }; +}; + +&gpiob { + gpio-line-names = "", "", "", "", "", /* 0 */ + "", "USB_RESET", "", "", "", /* 5 */ + "", "", "", "", "", /* 10 */ + ""; /* 15 */ +}; + +&gpiod { + gpio-line-names = "", "", "", "", "TP38", /* 0 */ + "TP39", "", "", "TP41", "TP42", /* 5 */ + "OLED_DC", "", "", "ETH_CS", "", /* 10 */ + "ETH_LAB_LEDRN"; /* 15 */ +}; + +&gpioe { + gpio-line-names = "TP35", "", "", "", "CAN_1_120R", /* 0 */ + "", "", "USER_BTN2", "TP48", "UART_TX_EN", /* 5 */ + "UART_RX_EN", "TP24", "", "TP25", "TP26", /* 10 */ + "TP27"; /* 15 */ +}; + +&gpiof { + gpio-line-names = "TP36", "TP37", "", "", "OLED_CS", /* 0 */ + "", "", "", "", "", /* 5 */ + "USER_LED1", "", "STACK_CS0", "", "", /* 10 */ + ""; /* 15 */ +}; + +&gpiog { + gpio-line-names = "ETH_RESET", "", "", "", "", /* 0 */ + "IOBUS_FLT_FB", "", "USER_LED2", "ETH1_PPS_A", "CAN_0_120R", /* 5 */ + "TP49", "", "", "", "", /* 10 */ + ""; /* 15 */ +}; + +&gpioh { + gpio-line-names = "", "", "OUT_1", "OUT_0", "OLED_RESET", /* 0 */ + "", "", "", "", "", /* 5 */ + "ETH1_PPS_B", "ETH_GPIO2", "", "IOBUS_PWR_EN", "", /* 10 */ + "TP33"; /* 15 */ +}; + +&gpioi { + gpio-line-names = "TIM_RTS", "", "", "", "DEVICE_DATA_EN", /* 0 */ + "", "", "", "ETH_WOL", "TP43", /* 5 */ + "", "USER_BTN"; /* 10 */ +}; + +&gpioz { + gpio-line-names = "HWID0", "HWID1", "HWID2", "HWID3", "", /* 0 */ + "", "HWID4", "HWID5"; /* 5 */ +}; + +&hash1 { + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_b>; + pinctrl-1 = <&i2c1_sleep_pins_b>; + status = "okay"; + + powerboard_eeprom: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + vcc-supply = <&v3v3>; + }; + + temperature-sensor@48 { + compatible = "national,lm75a"; + reg = <0x48>; + status = "disabled"; + }; +}; + +&i2c5 { + /delete-property/dmas; + /delete-property/dma-names; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c5_pins_b>; + pinctrl-1 = <&i2c5_sleep_pins_b>; + + status = "okay"; + + usbhub: usbhub@2c { + compatible ="microchip,usb2514b"; + reg = <0x2c>; + vdd-supply = <&v3v3>; + reset-gpios = <&gpiob 6 GPIO_ACTIVE_LOW>; + }; +}; + +&iwdg2 { + timeout-sec = <8>; + status = "okay"; +}; + +&m_can1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can1_pins_b>; + pinctrl-1 = <&m_can1_sleep_pins_b>; + status = "okay"; +}; + +&m_can2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can2_pins_a>; + pinctrl-1 = <&m_can2_sleep_pins_a>; + status = "okay"; +}; + +&pmic { + regulators { + buck1-supply = <®_5v>; /* VIN */ + buck2-supply = <®_5v>; /* VIN */ + buck3-supply = <®_5v>; /* VIN */ + buck4-supply = <®_5v>; /* VIN */ + ldo2-supply = <®_5v>; /* PMIC_LDO25IN */ + ldo4-supply = <®_5v>; /* VIN */ + ldo5-supply = <®_5v>; /* PMIC_LDO25IN */ + vref_ddr-supply = <®_5v>; /* VIN */ + boost-supply = <®_5v>; /* PMIC_BSTIN */ + pwr_sw2-supply = <&bst_out>; /* PMIC_SWIN */ + }; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&rtc { + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_b>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_b>; + vmmc-supply = <&v3v3>; + + bus-width = <8>; + mmc-ddr-3_3v; + no-1-8-v; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + + status = "okay"; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_c>; + cs-gpios = <&gpiof 12 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&spi4 { + pinctrl-names = "default"; + pinctrl-0 = <&spi4_pins_a>; + cs-gpios = <&gpiof 4 GPIO_ACTIVE_LOW>; + status = "okay"; + + lcd: display@0 { + compatible = "shineworld,lh133k", "panel-mipi-dbi-spi"; + reg = <0>; + power-supply = <&v3v3>; + io-supply = <&v3v3>; + backlight = <&backlight>; + dc-gpios = <&gpiod 10 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpioh 4 GPIO_ACTIVE_HIGH>; + spi-3wire; + spi-max-frequency = <32000000>; + + width-mm = <23>; + height-mm = <23>; + rotation = <180>; + + panel-timing { + hactive = <240>; + vactive = <240>; + hback-porch = <0>; + vback-porch = <0>; + + clock-frequency = <0>; + hfront-porch = <0>; + hsync-len = <0>; + vfront-porch = <0>; + vsync-len = <0>; + }; + }; +}; + +&spi5 { + pinctrl-names = "default"; + pinctrl-0 = <&spi5_pins_a>; + + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + cs-gpios = <&gpiod 13 GPIO_ACTIVE_LOW>; + + status = "okay"; + + switch: switch@0 { + compatible = "microchip,ksz9563"; + reg = <0>; + + reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; + spi-max-frequency = <44000000>; + + interrupt-parent = <&gpioa>; + interrupts = <6 IRQ_TYPE_EDGE_RISING>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port_dut: port@0 { + reg = <0>; + label = "dut"; + }; + + port_uplink: port@1 { + reg = <1>; + label = "uplink"; + }; + + port_cpu: port@2 { + reg = <2>; + label = "cpu"; + + ethernet = <ðernet0>; + + phy-mode = "rgmii-id"; + rx-internal-delay-ps = <2000>; + tx-internal-delay-ps = <2000>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; +}; + +&timers2 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; + + timer@1 { + status = "okay"; + }; +}; + +&timers3 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; + + timer@2 { + status = "okay"; + }; +}; + +&timers4 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; + + timer@3 { + status = "okay"; + }; +}; + +&uart4 { + label = "debug"; + + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; +}; + +&usart3 { + label = "dut"; + uart-has-rtscts; + + pinctrl-names = "default"; + pinctrl-0 = <&usart3_pins_f>; + + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + + status = "okay"; +}; + +&usbotg_hs { + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + + vusb_d-supply = <&vdd_usb>; + vusb_a-supply = <®18>; + + dr_mode = "peripheral"; + + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; + +&v3v3_hdmi { + /delete-property/regulator-always-on; +}; + +&vrefbuf { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vdda-supply = <&vdda>; + + status = "okay"; +}; From 5060e27012f7e0044ae838de59a46f563c54fb84 Mon Sep 17 00:00:00 2001 From: Etienne Carriere Date: Mon, 10 Jul 2023 17:05:15 +0200 Subject: [PATCH 08/29] ARM: dts: stm32: leverage OP-TEE ASync notif on STM32MP13x Soc family Enables use of GIC PPI#15 for OP-TEE asynchronous notifications on stm32mp13 platforms. Signed-off-by: Etienne Carriere Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp131.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi index d23bbc3639df..672f3b7735a2 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -33,6 +33,8 @@ firmware { optee { method = "smc"; compatible = "linaro,optee-tz"; + interrupt-parent = <&intc>; + interrupts = ; }; scmi: scmi { From 5408d51846b4ddb8e062c89e0b3097e51cd798af Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 1 Jun 2023 01:10:44 +0200 Subject: [PATCH 09/29] ARM: dts: stm32: Deduplicate DSI node on stm32mp15 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All boards using the DSI node duplicate the same pattern common pattern in board DTs, that pattern is ports with endpoint labels and the same in-SoC regulator connection. Move that common pattern into stm32mp157.dtsi instead. The two boards which do define panel@0 directly in the DSI bridge node now have #address-cells/#size-cells in their board DT instead of it being in stm32mp157.dtsi and activated incorrectly for all boards, even the ones which use e.g. another DSI-to-something bridge. Signed-off-by: Marek Vasut Acked-by: Raphaël Gallais-Pou Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp157.dtsi | 18 ++++++++++++ ...tm32mp157a-icore-stm32mp1-ctouch2-of10.dts | 24 ++++------------ .../stm32mp157a-icore-stm32mp1-edimm2.2.dts | 28 ++++++------------- arch/arm/boot/dts/st/stm32mp157c-dk2.dts | 28 ++++++------------- arch/arm/boot/dts/st/stm32mp157c-ev1.dts | 28 ++++++------------- 5 files changed, 48 insertions(+), 78 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp157.dtsi b/arch/arm/boot/dts/st/stm32mp157.dtsi index 5e733cd16ff9..6197d878894d 100644 --- a/arch/arm/boot/dts/st/stm32mp157.dtsi +++ b/arch/arm/boot/dts/st/stm32mp157.dtsi @@ -22,9 +22,27 @@ dsi: dsi@5a000000 { reg = <0x5a000000 0x800>; clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>; clock-names = "pclk", "ref", "px_clk"; + phy-dsi-supply = <®18>; resets = <&rcc DSI_R>; reset-names = "apb"; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + }; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts index 4279b26547df..df97e03d2a5a 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts +++ b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts @@ -46,26 +46,14 @@ panel_in_lvds: endpoint { &dsi { status = "okay"; - phy-dsi-supply = <®18>; +}; - ports { - #address-cells = <1>; - #size-cells = <0>; +&dsi_in { + remote-endpoint = <<dc_ep0_out>; +}; - port@0 { - reg = <0>; - dsi_in: endpoint { - remote-endpoint = <<dc_ep0_out>; - }; - }; - - port@1 { - reg = <1>; - dsi_out: endpoint { - remote-endpoint = <&bridge_in>; - }; - }; - }; +&dsi_out { + remote-endpoint = <&bridge_in>; }; &i2c6 { diff --git a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts index efba54289820..f8e404346396 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts +++ b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts @@ -46,26 +46,14 @@ panel_out_bridge: endpoint { &dsi { status = "okay"; - phy-dsi-supply = <®18>; +}; - ports { - #address-cells = <1>; - #size-cells = <0>; +&dsi_in { + remote-endpoint = <<dc_out_dsi>; +}; - port@0 { - reg = <0>; - dsi_in_ltdc: endpoint { - remote-endpoint = <<dc_out_dsi>; - }; - }; - - port@1 { - reg = <1>; - dsi_out_bridge: endpoint { - remote-endpoint = <&bridge_in_dsi>; - }; - }; - }; +&dsi_out { + remote-endpoint = <&bridge_in_dsi>; }; &i2c6 { @@ -88,7 +76,7 @@ ports { port@0 { reg = <0>; bridge_in_dsi: endpoint { - remote-endpoint = <&dsi_out_bridge>; + remote-endpoint = <&dsi_out>; data-lanes = <1 2>; }; }; @@ -108,7 +96,7 @@ <dc { port { ltdc_out_dsi: endpoint { - remote-endpoint = <&dsi_in_ltdc>; + remote-endpoint = <&dsi_in>; }; }; }; diff --git a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts index 4bef2300ed7c..510cca5acb79 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts @@ -34,26 +34,6 @@ &dsi { #address-cells = <1>; #size-cells = <0>; status = "okay"; - phy-dsi-supply = <®18>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi_in: endpoint { - remote-endpoint = <<dc_ep1_out>; - }; - }; - - port@1 { - reg = <1>; - dsi_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; panel@0 { compatible = "orisetech,otm8009a"; @@ -70,6 +50,14 @@ panel_in: endpoint { }; }; +&dsi_in { + remote-endpoint = <<dc_ep1_out>; +}; + +&dsi_out { + remote-endpoint = <&panel_in>; +}; + &i2c1 { touchscreen@38 { compatible = "focaltech,ft6236"; diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts index af3800501875..cd9c3ff5378b 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts @@ -100,30 +100,10 @@ dcmi_0: endpoint { }; &dsi { - phy-dsi-supply = <®18>; #address-cells = <1>; #size-cells = <0>; status = "okay"; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi_in: endpoint { - remote-endpoint = <<dc_ep0_out>; - }; - }; - - port@1 { - reg = <1>; - dsi_out: endpoint { - remote-endpoint = <&dsi_panel_in>; - }; - }; - }; - panel@0 { compatible = "raydium,rm68200"; reg = <0>; @@ -140,6 +120,14 @@ dsi_panel_in: endpoint { }; }; +&dsi_in { + remote-endpoint = <<dc_ep0_out>; +}; + +&dsi_out { + remote-endpoint = <&dsi_panel_in>; +}; + ðernet0 { status = "okay"; pinctrl-0 = <ðernet0_rgmii_pins_a>; From df362914eeadb82572434391f533d66f66360453 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Tue, 4 Jul 2023 19:33:17 +0200 Subject: [PATCH 10/29] ARM: dts: stm32: re-add CAN support on stm32f746 The revert commit 36a6418bb1259 ("Revert "ARM: dts: stm32: add CAN support on stm32f746"") prevented parsing errors due to the lack of CAN3 binding. Now that the binding definition for CAN3 is available in the mainline thanks to commit 8f3ef556f8e1a ("dt-bindings: mfd: stm32f7: Add binding definition for CAN3"), we can re-add the CAN support and make the driver usable again. Signed-off-by: Dario Binacchi Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32f746.dtsi | 47 +++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32f746.dtsi b/arch/arm/boot/dts/st/stm32f746.dtsi index d1802efd067c..9f3b26cfd0a3 100644 --- a/arch/arm/boot/dts/st/stm32f746.dtsi +++ b/arch/arm/boot/dts/st/stm32f746.dtsi @@ -257,6 +257,23 @@ rtc: rtc@40002800 { status = "disabled"; }; + can3: can@40003400 { + compatible = "st,stm32f4-bxcan"; + reg = <0x40003400 0x200>; + interrupts = <104>, <105>, <106>, <107>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F7_APB1_RESET(CAN3)>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>; + st,gcan = <&gcan3>; + status = "disabled"; + }; + + gcan3: gcan@40003600 { + compatible = "st,stm32f4-gcan", "syscon"; + reg = <0x40003600 0x200>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>; + }; + usart2: serial@40004400 { compatible = "st,stm32f7-uart"; reg = <0x40004400 0x400>; @@ -337,6 +354,36 @@ i2c4: i2c@40006000 { status = "disabled"; }; + can1: can@40006400 { + compatible = "st,stm32f4-bxcan"; + reg = <0x40006400 0x200>; + interrupts = <19>, <20>, <21>, <22>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F7_APB1_RESET(CAN1)>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>; + st,can-primary; + st,gcan = <&gcan1>; + status = "disabled"; + }; + + gcan1: gcan@40006600 { + compatible = "st,stm32f4-gcan", "syscon"; + reg = <0x40006600 0x200>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>; + }; + + can2: can@40006800 { + compatible = "st,stm32f4-bxcan"; + reg = <0x40006800 0x200>; + interrupts = <63>, <64>, <65>, <66>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F7_APB1_RESET(CAN2)>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN2)>; + st,can-secondary; + st,gcan = <&gcan1>; + status = "disabled"; + }; + cec: cec@40006c00 { compatible = "st,stm32-cec"; reg = <0x40006C00 0x400>; From 0637e66f8250c61f75042131fcb7f88ead2ad436 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Tue, 4 Jul 2023 19:34:06 +0200 Subject: [PATCH 11/29] ARM: dts: stm32: add pin map for i2c3 controller on stm32f7 Add pin configurations for using i2c3 controller on stm32f7. Signed-off-by: Dario Binacchi Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi index 9f65403295ca..c8dfda7bd04f 100644 --- a/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi @@ -171,6 +171,16 @@ pins { }; }; + i2c3_pins_a: i2c3-0 { + pins { + pinmux = , /* I2C3_SDA */ + ; /* I2C3_SCL */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + usbotg_hs_pins_a: usbotg-hs-0 { pins { pinmux = , /* OTG_HS_ULPI_NXT */ From f0215440069c4fb12958d2d321e05faa2708a11d Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Tue, 4 Jul 2023 19:34:07 +0200 Subject: [PATCH 12/29] ARM: dts: stm32: add touchscreen on stm32f746-disco board The patch adds support for touchscreen on the stm32f746-disco board. Signed-off-by: Dario Binacchi Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32f746-disco.dts | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/st/stm32f746-disco.dts b/arch/arm/boot/dts/st/stm32f746-disco.dts index c11616ed5fc6..a53da9c3a507 100644 --- a/arch/arm/boot/dts/st/stm32f746-disco.dts +++ b/arch/arm/boot/dts/st/stm32f746-disco.dts @@ -43,8 +43,9 @@ /dts-v1/; #include "stm32f746.dtsi" #include "stm32f746-pinctrl.dtsi" -#include #include +#include +#include / { model = "STMicroelectronics STM32F746-DISCO board"; @@ -99,6 +100,22 @@ &i2c1 { status = "okay"; }; +&i2c3 { + pinctrl-0 = <&i2c3_pins_a>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5306"; + reg = <0x38>; + interrupt-parent = <&gpioi>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <480>; + touchscreen-size-y = <272>; + }; +}; + &sdio1 { status = "okay"; vmmc-supply = <&mmc_vcard>; From 4193b9387562e1cb5894fda951fb639125292921 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 11 Jul 2023 14:25:31 +0200 Subject: [PATCH 13/29] ARM: dts: stm32: prtt1c: Add PoDL PSE regulator nodes This commit introduces Power over Data Line (PoDL) Power Source Equipment (PSE) regulator nodes to the PRTT1C devicetree. The addition of these nodes enables support for PoDL in PRTT1C devices, allowing power delivery and data transmission over a single twisted pair. The new PoDL PSE regulator nodes provide voltage capability information of the current board design, which can be used as a hint for system administrators when configuring and managing power settings. This update enhances the versatility and simplifies the power management of PRTT1C devices while ensuring compatibility with connected Powered Devices (PDs). After applying this patch, the power delivery can be controlled from user space with a patched [1] ethtool version using the following commands: ethtool --set-pse t1l2 podl-pse-admin-control enable to enable power delivery, and ethtool --show-pse t1l2 to display the PoDL PSE settings. By integrating PoDL PSE support into the PRTT1C devicetree, users can benefit from streamlined power and data connections in their deployments, improving overall system efficiency and reducing cabling complexity. [1] https://lore.kernel.org/all/20230317093024.1051999-1-o.rempel@pengutronix.de/ Signed-off-by: Oleksij Rempel Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp151a-prtt1c.dts | 32 +++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp151a-prtt1c.dts b/arch/arm/boot/dts/st/stm32mp151a-prtt1c.dts index 7ecf31263abc..c90d815f906b 100644 --- a/arch/arm/boot/dts/st/stm32mp151a-prtt1c.dts +++ b/arch/arm/boot/dts/st/stm32mp151a-prtt1c.dts @@ -23,6 +23,18 @@ clock_sja1105: clock-sja1105 { clock-frequency = <25000000>; }; + pse_t1l1: ethernet-pse-1 { + compatible = "podl-pse-regulator"; + pse-supply = <®_t1l1>; + #pse-cells = <0>; + }; + + pse_t1l2: ethernet-pse-2 { + compatible = "podl-pse-regulator"; + pse-supply = <®_t1l2>; + #pse-cells = <0>; + }; + mdio0: mdio { compatible = "virtual,mdio-gpio"; #address-cells = <1>; @@ -32,6 +44,24 @@ mdio0: mdio { }; + reg_t1l1: regulator-pse-t1l1 { + compatible = "regulator-fixed"; + regulator-name = "pse-t1l1"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpiog 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_t1l2: regulator-pse-t1l2 { + compatible = "regulator-fixed"; + regulator-name = "pse-t1l2"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpiog 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + wifi_pwrseq: wifi-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpiod 8 GPIO_ACTIVE_LOW>; @@ -92,6 +122,7 @@ t1l1_phy: ethernet-phy@7 { reset-gpios = <&gpiog 12 GPIO_ACTIVE_LOW>; reset-assert-us = <10>; reset-deassert-us = <35>; + pses = <&pse_t1l1>; }; /* TI DP83TD510E */ @@ -102,6 +133,7 @@ t1l2_phy: ethernet-phy@10 { reset-gpios = <&gpiog 11 GPIO_ACTIVE_LOW>; reset-assert-us = <10>; reset-deassert-us = <35>; + pses = <&pse_t1l2>; }; /* Micrel KSZ9031 */ From 0ee0ef38aa9f75f21b51f729dd42b2e932515188 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 18 May 2023 03:12:42 +0200 Subject: [PATCH 14/29] ARM: dts: stm32: Add missing detach mailbox for emtrion emSBC-Argon Add missing "detach" mailbox to this board to permit the CPU to inform the remote processor on a detach. This signal allows the remote processor firmware to stop IPC communication and to reinitialize the resources for a re-attach. Without this mailbox, detach is not possible and kernel log contains the following warning to, so make sure all the STM32MP15xx platform DTs are in sync regarding the mailboxes to fix the detach issue and the warning: " stm32-rproc 10000000.m4: mbox_request_channel_byname() could not locate channel named "detach" " Fixes: 6257dfc1c412 ("ARM: dts: stm32: Add coprocessor detach mbox on stm32mp15x-dkx boards") Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp157c-emstamp-argon.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp157c-emstamp-argon.dtsi b/arch/arm/boot/dts/st/stm32mp157c-emstamp-argon.dtsi index 94e38141af67..fd89542c69c9 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-emstamp-argon.dtsi +++ b/arch/arm/boot/dts/st/stm32mp157c-emstamp-argon.dtsi @@ -368,8 +368,8 @@ &iwdg2 { &m4_rproc { memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>; - mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; - mbox-names = "vq0", "vq1", "shutdown"; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>; + mbox-names = "vq0", "vq1", "shutdown", "detach"; interrupt-parent = <&exti>; interrupts = <68 1>; interrupt-names = "wdg"; From 966f04a89d77548e673de2c400abe0b2cf5c15db Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 18 May 2023 03:12:43 +0200 Subject: [PATCH 15/29] ARM: dts: stm32: Add missing detach mailbox for Odyssey SoM Add missing "detach" mailbox to this board to permit the CPU to inform the remote processor on a detach. This signal allows the remote processor firmware to stop IPC communication and to reinitialize the resources for a re-attach. Without this mailbox, detach is not possible and kernel log contains the following warning to, so make sure all the STM32MP15xx platform DTs are in sync regarding the mailboxes to fix the detach issue and the warning: " stm32-rproc 10000000.m4: mbox_request_channel_byname() could not locate channel named "detach" " Fixes: 6257dfc1c412 ("ARM: dts: stm32: Add coprocessor detach mbox on stm32mp15x-dkx boards") Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi b/arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi index e22871dc580c..cf7485251490 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi +++ b/arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi @@ -230,8 +230,8 @@ &iwdg2 { &m4_rproc { memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>; - mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; - mbox-names = "vq0", "vq1", "shutdown"; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>; + mbox-names = "vq0", "vq1", "shutdown", "detach"; interrupt-parent = <&exti>; interrupts = <68 1>; status = "okay"; From deb7edbc27a6ec4d8f5edfd8519b7ed13cbd2a52 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 11 Jul 2023 15:09:07 +0200 Subject: [PATCH 16/29] ARM: dts: stm32: Add missing detach mailbox for DHCOM SoM Add missing "detach" mailbox to this board to permit the CPU to inform the remote processor on a detach. This signal allows the remote processor firmware to stop IPC communication and to reinitialize the resources for a re-attach. Without this mailbox, detach is not possible and kernel log contains the following warning to, so make sure all the STM32MP15xx platform DTs are in sync regarding the mailboxes to fix the detach issue and the warning: " stm32-rproc 10000000.m4: mbox_request_channel_byname() could not locate channel named "detach" " Fixes: 6257dfc1c412 ("ARM: dts: stm32: Add coprocessor detach mbox on stm32mp15x-dkx boards") Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi index e61df23d361a..74a11ccc5333 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi @@ -416,8 +416,8 @@ &iwdg2 { &m4_rproc { memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>; - mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; - mbox-names = "vq0", "vq1", "shutdown"; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>; + mbox-names = "vq0", "vq1", "shutdown", "detach"; interrupt-parent = <&exti>; interrupts = <68 1>; status = "okay"; From 2f38de940f072db369edd3e6e8d82bb8f42c5c9b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 11 Jul 2023 15:11:21 +0200 Subject: [PATCH 17/29] ARM: dts: stm32: Add missing detach mailbox for DHCOR SoM Add missing "detach" mailbox to this board to permit the CPU to inform the remote processor on a detach. This signal allows the remote processor firmware to stop IPC communication and to reinitialize the resources for a re-attach. Without this mailbox, detach is not possible and kernel log contains the following warning to, so make sure all the STM32MP15xx platform DTs are in sync regarding the mailboxes to fix the detach issue and the warning: " stm32-rproc 10000000.m4: mbox_request_channel_byname() could not locate channel named "detach" " Fixes: 6257dfc1c412 ("ARM: dts: stm32: Add coprocessor detach mbox on stm32mp15x-dkx boards") Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi index bba19f21e527..89881a26c614 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi @@ -227,8 +227,8 @@ &iwdg2 { &m4_rproc { memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>; - mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; - mbox-names = "vq0", "vq1", "shutdown"; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>; + mbox-names = "vq0", "vq1", "shutdown", "detach"; interrupt-parent = <&exti>; interrupts = <68 1>; status = "okay"; From a77d289bddfe88290ff30524357434d9c708439d Mon Sep 17 00:00:00 2001 From: Pascal Paillet Date: Mon, 17 Jul 2023 15:46:27 +0200 Subject: [PATCH 18/29] ARM: dts: stm32: fix dts check warnings on stm32mp15-scmi Fix dts check warnings on stm32mp15-scmi reported by arm,scmi.yaml. Signed-off-by: Pascal Paillet Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp15-scmi.dtsi | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi b/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi index ad2584213d99..dc3b09f2f2af 100644 --- a/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi @@ -34,22 +34,21 @@ scmi_reguls: regulators { #address-cells = <1>; #size-cells = <0>; - scmi_reg11: reg11@0 { + scmi_reg11: regulator@0 { reg = <0>; regulator-name = "reg11"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; }; - scmi_reg18: reg18@1 { - voltd-name = "reg18"; + scmi_reg18: regulator@1 { reg = <1>; regulator-name = "reg18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - scmi_usb33: usb33@2 { + scmi_usb33: regulator@2 { reg = <2>; regulator-name = "usb33"; regulator-min-microvolt = <3300000>; From efbb7f91ca997939bb0b06baab9c9dec51863ce5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 30 Jul 2023 19:49:51 +0200 Subject: [PATCH 19/29] ARM: dts: st: stm32mp157c-emstamp: drop incorrect vref_ddr property The STPMIC1 PMIC vref_ddr regulator does not support over-current protection, according to bindings and Linux driver: stm32mp157c-emsbc-argon.dtb: stpmic@33: regulators:vref_ddr: 'regulator-over-current-protection' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp157c-emstamp-argon.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/st/stm32mp157c-emstamp-argon.dtsi b/arch/arm/boot/dts/st/stm32mp157c-emstamp-argon.dtsi index fd89542c69c9..f8e9980ed3d4 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-emstamp-argon.dtsi +++ b/arch/arm/boot/dts/st/stm32mp157c-emstamp-argon.dtsi @@ -310,7 +310,6 @@ vdda: ldo6 { vref_ddr: vref_ddr { regulator-name = "vref_ddr"; regulator-always-on; - regulator-over-current-protection; }; bst_out: boost { From a35f08a7d9bac137bce5d63b987f39dd21725eb9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 30 Jul 2023 19:49:52 +0200 Subject: [PATCH 20/29] ARM: dts: st: stm32mp157c-emstamp: correct regulator-active-discharge The "regulator-active-discharge" property is uint32, not boolean: stm32mp157c-emsbc-argon.dtb: stpmic@33: regulators:pwr_sw1:regulator-active-discharge: True is not of type 'array' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp157c-emstamp-argon.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/st/stm32mp157c-emstamp-argon.dtsi b/arch/arm/boot/dts/st/stm32mp157c-emstamp-argon.dtsi index f8e9980ed3d4..009209ca673b 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-emstamp-argon.dtsi +++ b/arch/arm/boot/dts/st/stm32mp157c-emstamp-argon.dtsi @@ -320,7 +320,7 @@ bst_out: boost { vbus_otg: pwr_sw1 { regulator-name = "vbus_otg"; interrupts = ; - regulator-active-discharge; + regulator-active-discharge = <1>; }; vbus_usbh: pwr_sw2 { From 756065e3f1e1733e4329b19d02c2e91021882861 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Tue, 8 Aug 2023 11:31:18 +0200 Subject: [PATCH 21/29] ARM: dts: st: Add gpio-ranges for stm32f746-pinctrl Since commit 913a956c4363 ("pinctrl: stm32: use dynamic allocation of GPIO base"), it's impossible to retrieve gpios from phandle, for example, mmc driver can't retrieve cd-gpios. Add missing gpio-ranges properties to fix it. Signed-off-by: Patrice Chotard Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32f746-pinctrl.dtsi | 44 +++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32f746-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f746-pinctrl.dtsi index 781197ef42d6..139f72b790c0 100644 --- a/arch/arm/boot/dts/st/stm32f746-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32f746-pinctrl.dtsi @@ -8,4 +8,48 @@ &pinctrl { compatible = "st,stm32f746-pinctrl"; + + gpioa: gpio@40020000 { + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@40020400 { + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@40020800 { + gpio-ranges = <&pinctrl 0 32 16>; + }; + + gpiod: gpio@40020c00 { + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@40021000 { + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@40021400 { + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@40021800 { + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@40021c00 { + gpio-ranges = <&pinctrl 0 112 16>; + }; + + gpioi: gpio@40022000 { + gpio-ranges = <&pinctrl 0 128 16>; + }; + + gpioj: gpio@40022400 { + gpio-ranges = <&pinctrl 0 144 16>; + }; + + gpiok: gpio@40022800 { + gpio-ranges = <&pinctrl 0 160 8>; + }; }; From 06113b7ac2dfe2eff8f1f8d901924d6710528d79 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Tue, 8 Aug 2023 11:31:19 +0200 Subject: [PATCH 22/29] ARM: dts: st: Add gpio-ranges for stm32f769-pinctrl Since commit 913a956c4363 ("pinctrl: stm32: use dynamic allocation of GPIO base"), it's impossible to retrieve gpios from phandle, for example, mmc driver can't retrieve cd-gpios. Add missing gpio-ranges properties to fix it. Signed-off-by: Patrice Chotard Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32f769-pinctrl.dtsi | 44 +++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32f769-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f769-pinctrl.dtsi index c26abc04e2ce..02c2a8b08468 100644 --- a/arch/arm/boot/dts/st/stm32f769-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32f769-pinctrl.dtsi @@ -8,4 +8,48 @@ &pinctrl { compatible = "st,stm32f769-pinctrl"; + + gpioa: gpio@40020000 { + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@40020400 { + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@40020800 { + gpio-ranges = <&pinctrl 0 32 16>; + }; + + gpiod: gpio@40020c00 { + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@40021000 { + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@40021400 { + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@40021800 { + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@40021c00 { + gpio-ranges = <&pinctrl 0 112 16>; + }; + + gpioi: gpio@40022000 { + gpio-ranges = <&pinctrl 0 128 16>; + }; + + gpioj: gpio@40022400 { + gpio-ranges = <&pinctrl 0 144 16>; + }; + + gpiok: gpio@40022800 { + gpio-ranges = <&pinctrl 0 160 8>; + }; }; From 008ef8b3a1a0095d61b156202cd9babb048f6d80 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Mon, 14 Aug 2023 15:28:41 +0200 Subject: [PATCH 23/29] ARM: dts: stm32: add ltdc support on stm32f746 MCU MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add LTDC (Lcd-tft Display Controller) support. Signed-off-by: Dario Binacchi Reviewed-by: Raphaël Gallais-Pou Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32f746.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32f746.dtsi b/arch/arm/boot/dts/st/stm32f746.dtsi index 9f3b26cfd0a3..53a8e2dec9a4 100644 --- a/arch/arm/boot/dts/st/stm32f746.dtsi +++ b/arch/arm/boot/dts/st/stm32f746.dtsi @@ -554,6 +554,16 @@ pwm { }; }; + ltdc: display-controller@40016800 { + compatible = "st,stm32-ltdc"; + reg = <0x40016800 0x200>; + interrupts = <88>, <89>; + resets = <&rcc STM32F7_APB2_RESET(LTDC)>; + clocks = <&rcc 1 CLK_LCD>; + clock-names = "lcd"; + status = "disabled"; + }; + pwrcfg: power-config@40007000 { compatible = "st,stm32-power-config", "syscon"; reg = <0x40007000 0x400>; From ba287d1a0137702a224b1f48673d529257b3c4bf Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Mon, 14 Aug 2023 15:28:42 +0200 Subject: [PATCH 24/29] ARM: dts: stm32: add pin map for LTDC on stm32f7 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add pin configurations for using LTDC (LCD-tft Display Controller) on stm32f746-disco board. Signed-off-by: Dario Binacchi Reviewed-by: Raphaël Gallais-Pou Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi | 35 +++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi index c8dfda7bd04f..65480a9f5cc4 100644 --- a/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi @@ -375,6 +375,41 @@ pins2 { bias-pull-up; }; }; + + + ltdc_pins_a: ltdc-0 { + pins { + pinmux = , /* LCD_B0 */ + , /* LCD_B4 */ + , /* LCD_VSYNC */ + , /* LCD_HSYNC */ + , /* LCD_CLK */ + , /* LCD_R0 */ + , /* LCD_R1 */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G0 */ + , /* LCD_G1 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_B1 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + , /* LCD_B7 */ + ; /* LCD_DE */ + slew-rate = <2>; + }; + }; }; }; }; From e4e724099f04072053cf411456e3e9aae48c4af1 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Mon, 14 Aug 2023 15:28:43 +0200 Subject: [PATCH 25/29] ARM: dts: stm32: rename mmc_vcard to vcc-3v3 on stm32f746-disco In the schematics of document UM1907, the power supply for the micro SD card is the same 3v3 voltage that is used to power other devices on the board. By generalizing the name of the voltage regulator, it can be referenced by other nodes in the device tree without creating misunderstandings. This patch is preparatory for future developments. Signed-off-by: Dario Binacchi Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32f746-disco.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32f746-disco.dts b/arch/arm/boot/dts/st/stm32f746-disco.dts index a53da9c3a507..960aed12aa9e 100644 --- a/arch/arm/boot/dts/st/stm32f746-disco.dts +++ b/arch/arm/boot/dts/st/stm32f746-disco.dts @@ -80,9 +80,9 @@ vcc5v_otg_fs: vcc5v-otg-fs-regulator { regulator-always-on; }; - mmc_vcard: mmc_vcard { + vcc_3v3: vcc-3v3 { compatible = "regulator-fixed"; - regulator-name = "mmc_vcard"; + regulator-name = "vcc_3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; @@ -118,7 +118,7 @@ touchscreen@38 { &sdio1 { status = "okay"; - vmmc-supply = <&mmc_vcard>; + vmmc-supply = <&vcc_3v3>; cd-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; pinctrl-names = "default", "opendrain"; pinctrl-0 = <&sdio_pins_a>; From 10a970bc3ebfaf1c751421ffc2ac3e40838f86ef Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Wed, 16 Aug 2023 09:26:58 +0200 Subject: [PATCH 26/29] ARM: dts: stm32: support display on stm32f746-disco board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support to Rocktech RK043FN48H display on stm32f746-disco board. Signed-off-by: Dario Binacchi Reviewed-by: Raphaël Gallais-Pou Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32f746-disco.dts | 44 ++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32f746-disco.dts b/arch/arm/boot/dts/st/stm32f746-disco.dts index 960aed12aa9e..37e3a905fc3c 100644 --- a/arch/arm/boot/dts/st/stm32f746-disco.dts +++ b/arch/arm/boot/dts/st/stm32f746-disco.dts @@ -61,6 +61,19 @@ memory@c0000000 { reg = <0xC0000000 0x800000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + no-map; + size = <0x80000>; + linux,dma-default; + }; + }; + aliases { serial0 = &usart1; }; @@ -86,6 +99,25 @@ vcc_3v3: vcc-3v3 { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; + + backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&gpiok 3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + panel_rgb: panel-rgb { + compatible = "rocktech,rk043fn48h"; + power-supply = <&vcc_3v3>; + backlight = <&backlight>; + enable-gpios = <&gpioi 12 GPIO_ACTIVE_HIGH>; + status = "okay"; + port { + panel_in_rgb: endpoint { + remote-endpoint = <<dc_out_rgb>; + }; + }; + }; }; &clk_hse { @@ -116,6 +148,18 @@ touchscreen@38 { }; }; +<dc { + pinctrl-0 = <<dc_pins_a>; + pinctrl-names = "default"; + status = "okay"; + + port { + ltdc_out_rgb: endpoint { + remote-endpoint = <&panel_in_rgb>; + }; + }; +}; + &sdio1 { status = "okay"; vmmc-supply = <&vcc_3v3>; From fe95052fc7b4f9f077d066dec78d59ec6fac9006 Mon Sep 17 00:00:00 2001 From: Etienne Carriere Date: Wed, 12 Jul 2023 16:24:29 +0200 Subject: [PATCH 27/29] dt-bindings: rcc: stm32: add STM32MP13 SCMI regulators IDs Adds SCMI regulator identifiers for STM32MP13x family. Signed-off-by: Etienne Carriere Signed-off-by: Pascal Paillet Acked-by: Conor Dooley Signed-off-by: Alexandre Torgue --- .../regulator/st,stm32mp13-regulator.h | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 include/dt-bindings/regulator/st,stm32mp13-regulator.h diff --git a/include/dt-bindings/regulator/st,stm32mp13-regulator.h b/include/dt-bindings/regulator/st,stm32mp13-regulator.h new file mode 100644 index 000000000000..b3a974dfc585 --- /dev/null +++ b/include/dt-bindings/regulator/st,stm32mp13-regulator.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */ +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + */ + +#ifndef __DT_BINDINGS_REGULATOR_ST_STM32MP13_REGULATOR_H +#define __DT_BINDINGS_REGULATOR_ST_STM32MP13_REGULATOR_H + +/* SCMI voltage domains identifiers */ + +/* SOC Internal regulators */ +#define VOLTD_SCMI_REG11 0 +#define VOLTD_SCMI_REG18 1 +#define VOLTD_SCMI_USB33 2 +#define VOLTD_SCMI_SDMMC1_IO 3 +#define VOLTD_SCMI_SDMMC2_IO 4 +#define VOLTD_SCMI_VREFBUF 5 + +/* STPMIC1 regulators */ +#define VOLTD_SCMI_STPMIC1_BUCK1 6 +#define VOLTD_SCMI_STPMIC1_BUCK2 7 +#define VOLTD_SCMI_STPMIC1_BUCK3 8 +#define VOLTD_SCMI_STPMIC1_BUCK4 9 +#define VOLTD_SCMI_STPMIC1_LDO1 10 +#define VOLTD_SCMI_STPMIC1_LDO2 11 +#define VOLTD_SCMI_STPMIC1_LDO3 12 +#define VOLTD_SCMI_STPMIC1_LDO4 13 +#define VOLTD_SCMI_STPMIC1_LDO5 14 +#define VOLTD_SCMI_STPMIC1_LDO6 15 +#define VOLTD_SCMI_STPMIC1_VREFDDR 16 +#define VOLTD_SCMI_STPMIC1_BOOST 17 +#define VOLTD_SCMI_STPMIC1_PWR_SW1 18 +#define VOLTD_SCMI_STPMIC1_PWR_SW2 19 + +/* External regulators */ +#define VOLTD_SCMI_REGU0 20 +#define VOLTD_SCMI_REGU1 21 +#define VOLTD_SCMI_REGU2 22 +#define VOLTD_SCMI_REGU3 23 +#define VOLTD_SCMI_REGU4 24 + +#endif /*__DT_BINDINGS_REGULATOR_ST_STM32MP13_REGULATOR_H */ From fb266d2d80b4fb2e65fd0868eddd996685ebd70e Mon Sep 17 00:00:00 2001 From: Etienne Carriere Date: Wed, 12 Jul 2023 16:24:30 +0200 Subject: [PATCH 28/29] ARM: dts: stm32: STM32MP13x SoC exposes SCMI regulators Updates STM32MP13x SoC DTSI file to define the SoC voltage regulators exposed by OP-TEE SCMI service and remove the fixed regulator abstraction previously used until OP-TEE OS firmware embeds the service which it does since its release tag 3.22.0. Signed-off-by: Etienne Carriere Signed-off-by: Pascal Paillet Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp131.dtsi | 50 ++++++++++++++-------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi index 672f3b7735a2..ac90fcbf0c09 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -52,6 +52,28 @@ scmi_reset: protocol@16 { reg = <0x16>; #reset-cells = <1>; }; + + scmi_voltd: protocol@17 { + reg = <0x17>; + + scmi_regu: regulators { + #address-cells = <1>; + #size-cells = <0>; + + scmi_reg11: regulator@0 { + reg = ; + regulator-name = "reg11"; + }; + scmi_reg18: regulator@1 { + reg = ; + regulator-name = "reg18"; + }; + scmi_usb33: regulator@2 { + reg = ; + regulator-name = "usb33"; + }; + }; + }; }; }; @@ -78,28 +100,6 @@ timer { always-on; }; - /* PWR 1v1, 1v8 and 3v3 regulators defined as fixed, waiting for SCMI */ - reg11: reg11 { - compatible = "regulator-fixed"; - regulator-name = "reg11"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - reg18: reg18 { - compatible = "regulator-fixed"; - regulator-name = "reg18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - usb33: usb33 { - compatible = "regulator-fixed"; - regulator-name = "usb33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - soc { compatible = "simple-bus"; #address-cells = <1>; @@ -801,7 +801,7 @@ usbotg_hs: usb@49000000 { g-tx-fifo-size = <256 16 16 16 16 16 16 16>; dr_mode = "otg"; otg-rev = <0x200>; - usb33d-supply = <&usb33>; + usb33d-supply = <&scmi_usb33>; status = "disabled"; }; @@ -1331,8 +1331,8 @@ usbphyc: usbphyc@5a006000 { reg = <0x5a006000 0x1000>; clocks = <&rcc USBPHY_K>; resets = <&rcc USBPHY_R>; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18>; + vdda1v1-supply = <&scmi_reg11>; + vdda1v8-supply = <&scmi_reg18>; status = "disabled"; usbphyc_port0: usb-phy@0 { From 4c757f6b8026f7d65bbcd2b821651848a074a12b Mon Sep 17 00:00:00 2001 From: Etienne Carriere Date: Wed, 12 Jul 2023 16:24:31 +0200 Subject: [PATCH 29/29] ARM: dts: stm32: add SCMI PMIC regulators on stm32mp135f-dk board Since OP-TEE release tag 3.22.0, OP-TEE SCMI service for STM32MP13x SoC family exposes PMIC voltage regulators. This change defines them in the platform DTS file and removes the fixed regulators that were previously defined to abstract them before OP-TEE firmware was ready. Signed-off-by: Etienne Carriere Signed-off-by: Pascal Paillet Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp135f-dk.dts | 68 +++++++++++-------------- 1 file changed, 30 insertions(+), 38 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts index f0900ca672b5..eea740d097c7 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts @@ -9,6 +9,7 @@ #include #include #include +#include #include "stm32mp135.dtsi" #include "stm32mp13xf.dtsi" #include "stm32mp13-pinctrl.dtsi" @@ -65,45 +66,13 @@ led-blue { default-state = "off"; }; }; - - v3v3_sw: v3v3-sw { - compatible = "regulator-fixed"; - regulator-name = "v3v3_sw"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_adc: vdd-adc { - compatible = "regulator-fixed"; - regulator-name = "vdd_adc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_sd: vdd-sd { - compatible = "regulator-fixed"; - regulator-name = "vdd_sd"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - regulator-always-on; - }; - - vdd_usb: vdd-usb { - compatible = "regulator-fixed"; - regulator-name = "vdd_usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; }; &adc_1 { pinctrl-names = "default"; pinctrl-0 = <&adc1_usb_cc_pins_a>; - vdda-supply = <&vdd_adc>; - vref-supply = <&vdd_adc>; + vdda-supply = <&scmi_vdd_adc>; + vref-supply = <&scmi_vdd_adc>; status = "okay"; adc1: adc@0 { status = "okay"; @@ -195,6 +164,29 @@ &rtc { status = "okay"; }; +&scmi_regu { + scmi_vdd_adc: regulator@10 { + reg = ; + regulator-name = "vdd_adc"; + }; + scmi_vdd_usb: regulator@13 { + reg = ; + regulator-name = "vdd_usb"; + }; + scmi_vdd_sd: regulator@14 { + reg = ; + regulator-name = "vdd_sd"; + }; + scmi_v1v8_periph: regulator@15 { + reg = ; + regulator-name = "v1v8_periph"; + }; + scmi_v3v3_sw: regulator@19 { + reg = ; + regulator-name = "v3v3_sw"; + }; +}; + &sdmmc1 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>; @@ -204,7 +196,7 @@ &sdmmc1 { disable-wp; st,neg-edge; bus-width = <4>; - vmmc-supply = <&vdd_sd>; + vmmc-supply = <&scmi_vdd_sd>; status = "okay"; }; @@ -321,7 +313,7 @@ &usbh_ehci { hub@1 { compatible = "usb424,2514"; reg = <1>; - vdd-supply = <&v3v3_sw>; + vdd-supply = <&scmi_v3v3_sw>; }; }; @@ -342,7 +334,7 @@ &usbphyc { }; &usbphyc_port0 { - phy-supply = <&vdd_usb>; + phy-supply = <&scmi_vdd_usb>; st,current-boost-microamp = <1000>; st,decrease-hs-slew-rate; st,tune-hs-dc-level = <2>; @@ -356,7 +348,7 @@ &usbphyc_port0 { }; &usbphyc_port1 { - phy-supply = <&vdd_usb>; + phy-supply = <&scmi_vdd_usb>; st,current-boost-microamp = <1000>; st,decrease-hs-slew-rate; st,tune-hs-dc-level = <2>;