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soc: mediatek: mmsys: Migrate all tables to MMSYS_ROUTE() macro
Now that all of the mmsys routing tables have been fixed, migrate all of them to use the MMSYS_ROUTE() macro: this will make sure that future additions to any of the tables for the currently supported SoCs are compile-time sanity checked, greatly reducing room for (way too common) mistakes. Link: https://lore.kernel.org/r/20250212100012.33001-8-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
This commit is contained in:
AngeloGioacchino Del Regno
parent
d294d56cb9
commit
aa0f05dcf3
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@ -14,27 +14,21 @@
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#define MT8167_DSI0_SEL_IN_RDMA0 0x1
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static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] = {
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{
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DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
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MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
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OVL0_MOUT_EN_COLOR0
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}, {
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DDP_COMPONENT_DITHER0, DDP_COMPONENT_RDMA0,
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MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_RDMA0,
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MT8167_DITHER_MOUT_EN_RDMA0
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}, {
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DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
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MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0,
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COLOR0_SEL_IN_OVL0
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}, {
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DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI0,
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MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, MT8167_DSI0_SEL_IN_RDMA0,
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MT8167_DSI0_SEL_IN_RDMA0
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}, {
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DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI0,
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MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_DSI0,
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MT8167_RDMA0_SOUT_DSI0
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},
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MMSYS_ROUTE(OVL0, COLOR0,
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MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
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OVL0_MOUT_EN_COLOR0),
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MMSYS_ROUTE(DITHER0, RDMA0,
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MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_RDMA0,
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MT8167_DITHER_MOUT_EN_RDMA0),
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MMSYS_ROUTE(OVL0, COLOR0,
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MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0,
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COLOR0_SEL_IN_OVL0),
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MMSYS_ROUTE(RDMA0, DSI0,
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MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, MT8167_DSI0_SEL_IN_RDMA0,
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MT8167_DSI0_SEL_IN_RDMA0),
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MMSYS_ROUTE(RDMA0, DSI0,
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MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_DSI0,
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MT8167_RDMA0_SOUT_DSI0),
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};
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#endif /* __SOC_MEDIATEK_MT8167_MMSYS_H */
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@ -33,63 +33,48 @@
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#define MT8173_RDMA0_SOUT_COLOR0 BIT(0)
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static const struct mtk_mmsys_routes mt8173_mmsys_routing_table[] = {
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{
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DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
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MT8173_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN,
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MT8173_OVL0_MOUT_EN_COLOR0, MT8173_OVL0_MOUT_EN_COLOR0
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}, {
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DDP_COMPONENT_OD0, DDP_COMPONENT_RDMA0,
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MT8173_DISP_REG_CONFIG_DISP_OD_MOUT_EN,
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MT8173_OD0_MOUT_EN_RDMA0, MT8173_OD0_MOUT_EN_RDMA0
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}, {
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DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0,
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MT8173_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN,
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MT8173_UFOE_MOUT_EN_DSI0, MT8173_UFOE_MOUT_EN_DSI0
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}, {
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DDP_COMPONENT_COLOR0, DDP_COMPONENT_AAL0,
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MT8173_DISP_REG_CONFIG_DISP_COLOR0_SOUT_SEL_IN,
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MT8173_COLOR0_SOUT_MERGE, 0 /* SOUT to AAL */
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}, {
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DDP_COMPONENT_RDMA0, DDP_COMPONENT_UFOE,
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MT8173_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN,
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MT8173_RDMA0_SOUT_COLOR0, 0 /* SOUT to UFOE */
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}, {
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DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
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MT8173_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN,
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MT8173_COLOR0_SEL_IN_OVL0, MT8173_COLOR0_SEL_IN_OVL0
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}, {
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DDP_COMPONENT_AAL0, DDP_COMPONENT_COLOR0,
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MT8173_DISP_REG_CONFIG_DISP_AAL_SEL_IN,
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MT8173_AAL_SEL_IN_MERGE, 0 /* SEL_IN from COLOR0 */
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}, {
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DDP_COMPONENT_RDMA0, DDP_COMPONENT_UFOE,
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MT8173_DISP_REG_CONFIG_DISP_UFOE_SEL_IN,
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MT8173_UFOE_SEL_IN_RDMA0, 0 /* SEL_IN from RDMA0 */
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}, {
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DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0,
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MT8173_DISP_REG_CONFIG_DSI0_SEL_IN,
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MT8173_DSI0_SEL_IN_UFOE, 0, /* SEL_IN from UFOE */
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}, {
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DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
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MT8173_DISP_REG_CONFIG_DISP_OVL1_MOUT_EN,
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MT8173_OVL1_MOUT_EN_COLOR1, MT8173_OVL1_MOUT_EN_COLOR1
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}, {
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DDP_COMPONENT_GAMMA, DDP_COMPONENT_RDMA1,
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MT8173_DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN,
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MT8173_GAMMA_MOUT_EN_RDMA1, MT8173_GAMMA_MOUT_EN_RDMA1
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}, {
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DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
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MT8173_DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN,
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RDMA1_SOUT_MASK, RDMA1_SOUT_DPI0
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}, {
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DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
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MT8173_DISP_REG_CONFIG_DISP_COLOR1_SEL_IN,
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COLOR1_SEL_IN_OVL1, COLOR1_SEL_IN_OVL1
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}, {
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DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
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MT8173_DISP_REG_CONFIG_DPI_SEL_IN,
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MT8173_DPI0_SEL_IN_MASK, MT8173_DPI0_SEL_IN_RDMA1
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}
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MMSYS_ROUTE(OVL0, COLOR0,
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MT8173_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, MT8173_OVL0_MOUT_EN_COLOR0,
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MT8173_OVL0_MOUT_EN_COLOR0),
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MMSYS_ROUTE(OD0, RDMA0,
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MT8173_DISP_REG_CONFIG_DISP_OD_MOUT_EN, MT8173_OD0_MOUT_EN_RDMA0,
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MT8173_OD0_MOUT_EN_RDMA0),
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MMSYS_ROUTE(UFOE, DSI0,
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MT8173_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, MT8173_UFOE_MOUT_EN_DSI0,
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MT8173_UFOE_MOUT_EN_DSI0),
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MMSYS_ROUTE(COLOR0, AAL0,
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MT8173_DISP_REG_CONFIG_DISP_COLOR0_SOUT_SEL_IN, MT8173_COLOR0_SOUT_MERGE,
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0 /* SOUT to AAL */),
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MMSYS_ROUTE(RDMA0, UFOE,
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MT8173_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8173_RDMA0_SOUT_COLOR0,
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0 /* SOUT to UFOE */),
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MMSYS_ROUTE(OVL0, COLOR0,
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MT8173_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, MT8173_COLOR0_SEL_IN_OVL0,
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MT8173_COLOR0_SEL_IN_OVL0),
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MMSYS_ROUTE(AAL0, COLOR0,
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MT8173_DISP_REG_CONFIG_DISP_AAL_SEL_IN, MT8173_AAL_SEL_IN_MERGE,
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0 /* SEL_IN from COLOR0 */),
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MMSYS_ROUTE(RDMA0, UFOE,
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MT8173_DISP_REG_CONFIG_DISP_UFOE_SEL_IN, MT8173_UFOE_SEL_IN_RDMA0,
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0 /* SEL_IN from RDMA0 */),
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MMSYS_ROUTE(UFOE, DSI0,
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MT8173_DISP_REG_CONFIG_DSI0_SEL_IN, MT8173_DSI0_SEL_IN_UFOE,
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0 /* SEL_IN from UFOE */),
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MMSYS_ROUTE(OVL1, COLOR1,
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MT8173_DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, MT8173_OVL1_MOUT_EN_COLOR1,
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MT8173_OVL1_MOUT_EN_COLOR1),
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MMSYS_ROUTE(GAMMA, RDMA1,
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MT8173_DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, MT8173_GAMMA_MOUT_EN_RDMA1,
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MT8173_GAMMA_MOUT_EN_RDMA1),
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MMSYS_ROUTE(RDMA1, DPI0,
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MT8173_DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
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RDMA1_SOUT_DPI0),
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MMSYS_ROUTE(OVL1, COLOR1,
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MT8173_DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, COLOR1_SEL_IN_OVL1,
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COLOR1_SEL_IN_OVL1),
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MMSYS_ROUTE(RDMA1, DPI0,
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MT8173_DISP_REG_CONFIG_DPI_SEL_IN, MT8173_DPI0_SEL_IN_MASK,
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MT8173_DPI0_SEL_IN_RDMA1),
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};
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#endif /* __SOC_MEDIATEK_MT8173_MMSYS_H */
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@ -28,35 +28,27 @@
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#define MT8183_MMSYS_SW0_RST_B 0x140
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static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
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{
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DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,
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MT8183_DISP_OVL0_MOUT_EN, MT8183_OVL0_MOUT_EN_OVL0_2L,
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MT8183_OVL0_MOUT_EN_OVL0_2L
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}, {
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DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
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MT8183_DISP_OVL0_2L_MOUT_EN, MT8183_OVL0_2L_MOUT_EN_DISP_PATH0,
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MT8183_OVL0_2L_MOUT_EN_DISP_PATH0
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}, {
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DDP_COMPONENT_OVL_2L1, DDP_COMPONENT_RDMA1,
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MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1,
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MT8183_OVL1_2L_MOUT_EN_RDMA1
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}, {
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DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
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MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0,
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MT8183_DITHER0_MOUT_IN_DSI0
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}, {
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DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
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MT8183_DISP_PATH0_SEL_IN, MT8183_DISP_PATH0_SEL_IN_OVL0_2L,
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MT8183_DISP_PATH0_SEL_IN_OVL0_2L
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}, {
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DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
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MT8183_DISP_DPI0_SEL_IN, MT8183_DPI0_SEL_IN_RDMA1,
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MT8183_DPI0_SEL_IN_RDMA1
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}, {
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DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
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MT8183_DISP_RDMA0_SOUT_SEL_IN, MT8183_RDMA0_SOUT_COLOR0,
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MT8183_RDMA0_SOUT_COLOR0
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}
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MMSYS_ROUTE(OVL0, OVL_2L0,
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MT8183_DISP_OVL0_MOUT_EN, MT8183_OVL0_MOUT_EN_OVL0_2L,
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MT8183_OVL0_MOUT_EN_OVL0_2L),
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MMSYS_ROUTE(OVL_2L0, RDMA0,
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MT8183_DISP_OVL0_2L_MOUT_EN, MT8183_OVL0_2L_MOUT_EN_DISP_PATH0,
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MT8183_OVL0_2L_MOUT_EN_DISP_PATH0),
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MMSYS_ROUTE(OVL_2L1, RDMA1,
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MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1,
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MT8183_OVL1_2L_MOUT_EN_RDMA1),
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MMSYS_ROUTE(DITHER0, DSI0,
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MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0,
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MT8183_DITHER0_MOUT_IN_DSI0),
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MMSYS_ROUTE(OVL_2L0, RDMA0,
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MT8183_DISP_PATH0_SEL_IN, MT8183_DISP_PATH0_SEL_IN_OVL0_2L,
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MT8183_DISP_PATH0_SEL_IN_OVL0_2L),
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MMSYS_ROUTE(RDMA1, DPI0,
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MT8183_DISP_DPI0_SEL_IN, MT8183_DPI0_SEL_IN_RDMA1,
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MT8183_DPI0_SEL_IN_RDMA1),
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MMSYS_ROUTE(RDMA0, COLOR0,
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MT8183_DISP_RDMA0_SOUT_SEL_IN, MT8183_RDMA0_SOUT_COLOR0,
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MT8183_RDMA0_SOUT_COLOR0),
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};
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#endif /* __SOC_MEDIATEK_MT8183_MMSYS_H */
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@ -63,61 +63,39 @@
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#define MT8186_MMSYS_SW0_RST_B 0x160
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static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = {
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{
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DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
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MT8186_DISP_OVL0_MOUT_EN, MT8186_OVL0_MOUT_EN_MASK,
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MT8186_OVL0_MOUT_TO_RDMA0
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},
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{
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DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
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MT8186_DISP_RDMA0_SEL_IN, MT8186_RDMA0_SEL_IN_MASK,
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MT8186_RDMA0_FROM_OVL0
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},
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{
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DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
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MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_CON_MASK,
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MT8186_OVL0_GO_BLEND
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},
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{
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DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
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MT8186_DISP_RDMA0_SOUT_SEL, MT8186_RDMA0_SOUT_SEL_MASK,
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MT8186_RDMA0_SOUT_TO_COLOR0
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},
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{
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DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
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MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK,
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MT8186_DITHER0_MOUT_TO_DSI0,
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},
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{
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DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
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MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK,
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MT8186_DSI0_FROM_DITHER0
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},
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{
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DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
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MT8186_DISP_OVL0_2L_MOUT_EN, MT8186_OVL0_2L_MOUT_EN_MASK,
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MT8186_OVL0_2L_MOUT_TO_RDMA1
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},
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{
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DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
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MT8186_DISP_RDMA1_SEL_IN, MT8186_RDMA1_SEL_IN_MASK,
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MT8186_RDMA1_FROM_OVL0_2L
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},
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{
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DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
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MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_2L_CON_MASK,
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MT8186_OVL0_2L_GO_BLEND
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},
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{
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DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
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MT8186_DISP_RDMA1_MOUT_EN, MT8186_RDMA1_MOUT_EN_MASK,
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MT8186_RDMA1_MOUT_TO_DPI0_SEL
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},
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{
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DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
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MT8186_DISP_DPI0_SEL_IN, MT8186_DPI0_SEL_IN_MASK,
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MT8186_DPI0_FROM_RDMA1
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},
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MMSYS_ROUTE(OVL0, RDMA0,
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MT8186_DISP_OVL0_MOUT_EN, MT8186_OVL0_MOUT_EN_MASK,
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MT8186_OVL0_MOUT_TO_RDMA0),
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MMSYS_ROUTE(OVL0, RDMA0,
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MT8186_DISP_RDMA0_SEL_IN, MT8186_RDMA0_SEL_IN_MASK,
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MT8186_RDMA0_FROM_OVL0),
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MMSYS_ROUTE(OVL0, RDMA0,
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MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_CON_MASK,
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MT8186_OVL0_GO_BLEND),
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MMSYS_ROUTE(RDMA0, COLOR0,
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MT8186_DISP_RDMA0_SOUT_SEL, MT8186_RDMA0_SOUT_SEL_MASK,
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MT8186_RDMA0_SOUT_TO_COLOR0),
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MMSYS_ROUTE(DITHER0, DSI0,
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MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK,
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MT8186_DITHER0_MOUT_TO_DSI0),
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MMSYS_ROUTE(DITHER0, DSI0,
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MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK,
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MT8186_DSI0_FROM_DITHER0),
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MMSYS_ROUTE(OVL_2L0, RDMA1,
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MT8186_DISP_OVL0_2L_MOUT_EN, MT8186_OVL0_2L_MOUT_EN_MASK,
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MT8186_OVL0_2L_MOUT_TO_RDMA1),
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MMSYS_ROUTE(OVL_2L0, RDMA1,
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MT8186_DISP_RDMA1_SEL_IN, MT8186_RDMA1_SEL_IN_MASK,
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||||
MT8186_RDMA1_FROM_OVL0_2L),
|
||||
MMSYS_ROUTE(OVL_2L0, RDMA1,
|
||||
MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_2L_CON_MASK,
|
||||
MT8186_OVL0_2L_GO_BLEND),
|
||||
MMSYS_ROUTE(RDMA1, DPI0,
|
||||
MT8186_DISP_RDMA1_MOUT_EN, MT8186_RDMA1_MOUT_EN_MASK,
|
||||
MT8186_RDMA1_MOUT_TO_DPI0_SEL),
|
||||
MMSYS_ROUTE(RDMA1, DPI0,
|
||||
MT8186_DISP_DPI0_SEL_IN, MT8186_DPI0_SEL_IN_MASK,
|
||||
MT8186_DPI0_FROM_RDMA1),
|
||||
};
|
||||
|
||||
#endif /* __SOC_MEDIATEK_MT8186_MMSYS_H */
|
||||
|
|
|
|||
|
|
@ -31,47 +31,36 @@
|
|||
#define MT8192_DSI0_SEL_IN_DITHER0 0x1
|
||||
|
||||
static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
|
||||
{
|
||||
DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
|
||||
MT8192_DISP_OVL0_2L_MOUT_EN, MT8192_OVL0_MOUT_EN_DISP_RDMA0,
|
||||
MT8192_OVL0_MOUT_EN_DISP_RDMA0
|
||||
}, {
|
||||
DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_RDMA4,
|
||||
MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4,
|
||||
MT8192_OVL2_2L_MOUT_EN_RDMA4
|
||||
}, {
|
||||
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
|
||||
MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0,
|
||||
MT8192_DITHER0_MOUT_IN_DSI0
|
||||
}, {
|
||||
DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
|
||||
MT8192_DISP_RDMA0_SEL_IN, MT8192_RDMA0_SEL_IN_OVL0_2L,
|
||||
MT8192_RDMA0_SEL_IN_OVL0_2L
|
||||
}, {
|
||||
DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0,
|
||||
MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0,
|
||||
MT8192_AAL0_SEL_IN_CCORR0
|
||||
}, {
|
||||
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
|
||||
MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0,
|
||||
MT8192_DSI0_SEL_IN_DITHER0
|
||||
}, {
|
||||
DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
|
||||
MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0,
|
||||
MT8192_RDMA0_SOUT_COLOR0
|
||||
}, {
|
||||
DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0,
|
||||
MT8192_DISP_CCORR0_SOUT_SEL, MT8192_CCORR0_SOUT_AAL0,
|
||||
MT8192_CCORR0_SOUT_AAL0
|
||||
}, {
|
||||
DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,
|
||||
MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_GO_BG,
|
||||
MT8192_DISP_OVL0_GO_BG
|
||||
}, {
|
||||
DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
|
||||
MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_2L_GO_BLEND,
|
||||
MT8192_DISP_OVL0_2L_GO_BLEND
|
||||
}
|
||||
MMSYS_ROUTE(OVL_2L0, RDMA0,
|
||||
MT8192_DISP_OVL0_2L_MOUT_EN, MT8192_OVL0_MOUT_EN_DISP_RDMA0,
|
||||
MT8192_OVL0_MOUT_EN_DISP_RDMA0),
|
||||
MMSYS_ROUTE(OVL_2L2, RDMA4,
|
||||
MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4,
|
||||
MT8192_OVL2_2L_MOUT_EN_RDMA4),
|
||||
MMSYS_ROUTE(DITHER0, DSI0,
|
||||
MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0,
|
||||
MT8192_DITHER0_MOUT_IN_DSI0),
|
||||
MMSYS_ROUTE(OVL_2L0, RDMA0,
|
||||
MT8192_DISP_RDMA0_SEL_IN, MT8192_RDMA0_SEL_IN_OVL0_2L,
|
||||
MT8192_RDMA0_SEL_IN_OVL0_2L),
|
||||
MMSYS_ROUTE(CCORR, AAL0,
|
||||
MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0,
|
||||
MT8192_AAL0_SEL_IN_CCORR0),
|
||||
MMSYS_ROUTE(DITHER0, DSI0,
|
||||
MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0,
|
||||
MT8192_DSI0_SEL_IN_DITHER0),
|
||||
MMSYS_ROUTE(RDMA0, COLOR0,
|
||||
MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0,
|
||||
MT8192_RDMA0_SOUT_COLOR0),
|
||||
MMSYS_ROUTE(CCORR, AAL0,
|
||||
MT8192_DISP_CCORR0_SOUT_SEL, MT8192_CCORR0_SOUT_AAL0,
|
||||
MT8192_CCORR0_SOUT_AAL0),
|
||||
MMSYS_ROUTE(OVL0, OVL_2L0,
|
||||
MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_GO_BG,
|
||||
MT8192_DISP_OVL0_GO_BG),
|
||||
MMSYS_ROUTE(OVL_2L0, RDMA0,
|
||||
MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_2L_GO_BLEND,
|
||||
MT8192_DISP_OVL0_2L_GO_BLEND),
|
||||
};
|
||||
|
||||
#endif /* __SOC_MEDIATEK_MT8192_MMSYS_H */
|
||||
|
|
|
|||
|
|
@ -160,370 +160,278 @@
|
|||
#define MT8195_SVPP3_MDP_RSZ BIT(5)
|
||||
|
||||
static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
|
||||
{
|
||||
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
|
||||
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,
|
||||
MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
|
||||
}, {
|
||||
DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
|
||||
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0,
|
||||
MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0
|
||||
}, {
|
||||
DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1,
|
||||
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1,
|
||||
MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1
|
||||
}, {
|
||||
DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
|
||||
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,
|
||||
MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
|
||||
}, {
|
||||
DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
|
||||
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1,
|
||||
MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1
|
||||
}, {
|
||||
DDP_COMPONENT_OVL1, DDP_COMPONENT_OVL0,
|
||||
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0,
|
||||
MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0
|
||||
}, {
|
||||
DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
|
||||
MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
|
||||
}, {
|
||||
DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
|
||||
MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
|
||||
MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0
|
||||
}, {
|
||||
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE
|
||||
}, {
|
||||
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
|
||||
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
|
||||
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
|
||||
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
|
||||
}, {
|
||||
DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
|
||||
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
|
||||
}, {
|
||||
DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
|
||||
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
|
||||
}, {
|
||||
DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
|
||||
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
|
||||
}, {
|
||||
DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
|
||||
MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
|
||||
}, {
|
||||
DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
|
||||
MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
|
||||
}, {
|
||||
DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
|
||||
MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
|
||||
}, {
|
||||
DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
|
||||
MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
|
||||
MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
|
||||
MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0
|
||||
}, {
|
||||
DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
|
||||
MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
|
||||
}, {
|
||||
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
|
||||
MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
|
||||
}, {
|
||||
DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
|
||||
MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
|
||||
MT8195_SEL_IN_DSI1_FROM_VPP_MERGE
|
||||
}, {
|
||||
DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
|
||||
MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
|
||||
MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE
|
||||
}, {
|
||||
DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
|
||||
}, {
|
||||
DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
|
||||
}, {
|
||||
DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
|
||||
}, {
|
||||
DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
|
||||
}, {
|
||||
DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
|
||||
}, {
|
||||
DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
|
||||
}, {
|
||||
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
|
||||
}, {
|
||||
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
|
||||
}, {
|
||||
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
|
||||
}, {
|
||||
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
|
||||
}, {
|
||||
DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
|
||||
MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
|
||||
}, {
|
||||
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
|
||||
MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
|
||||
}, {
|
||||
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
|
||||
MT8195_SOUT_DISP_DITHER0_TO_DSI0
|
||||
}, {
|
||||
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
|
||||
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN
|
||||
}, {
|
||||
DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
|
||||
MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE
|
||||
}, {
|
||||
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
|
||||
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
|
||||
}, {
|
||||
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
|
||||
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
|
||||
}, {
|
||||
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
|
||||
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
|
||||
}, {
|
||||
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
|
||||
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
|
||||
}, {
|
||||
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
|
||||
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
|
||||
MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
|
||||
MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
|
||||
MT8195_SOUT_VPP_MERGE_TO_DSI1
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
|
||||
MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
|
||||
MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
|
||||
MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
|
||||
MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
|
||||
MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
|
||||
MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK,
|
||||
MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN
|
||||
}, {
|
||||
DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
|
||||
MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0
|
||||
}, {
|
||||
DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
|
||||
MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
|
||||
}, {
|
||||
DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
|
||||
MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
|
||||
}, {
|
||||
DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
|
||||
MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
|
||||
}, {
|
||||
DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
|
||||
MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
|
||||
}, {
|
||||
DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
|
||||
MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1
|
||||
}, {
|
||||
DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
|
||||
MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0
|
||||
}, {
|
||||
DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
|
||||
MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
|
||||
}, {
|
||||
DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
|
||||
MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
|
||||
}, {
|
||||
DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
|
||||
MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
|
||||
}, {
|
||||
DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
|
||||
MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
|
||||
}
|
||||
MMSYS_ROUTE(OVL0, RDMA0,
|
||||
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,
|
||||
MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0),
|
||||
MMSYS_ROUTE(OVL0, WDMA0,
|
||||
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0,
|
||||
MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0),
|
||||
MMSYS_ROUTE(OVL0, OVL1,
|
||||
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1,
|
||||
MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1),
|
||||
MMSYS_ROUTE(OVL1, RDMA1,
|
||||
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,
|
||||
MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1),
|
||||
MMSYS_ROUTE(OVL1, WDMA1,
|
||||
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1,
|
||||
MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1),
|
||||
MMSYS_ROUTE(OVL1, OVL0,
|
||||
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0,
|
||||
MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0),
|
||||
MMSYS_ROUTE(DSC0, MERGE0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
|
||||
MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT),
|
||||
MMSYS_ROUTE(DITHER1, MERGE0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
|
||||
MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1),
|
||||
MMSYS_ROUTE(MERGE5, MERGE0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
|
||||
MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0),
|
||||
MMSYS_ROUTE(DITHER0, DSC0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0),
|
||||
MMSYS_ROUTE(MERGE0, DSC0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE),
|
||||
MMSYS_ROUTE(DITHER1, DSC1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1),
|
||||
MMSYS_ROUTE(MERGE0, DSC1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE),
|
||||
MMSYS_ROUTE(MERGE0, DP_INTF1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
|
||||
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE),
|
||||
MMSYS_ROUTE(MERGE0, DPI0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
|
||||
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE),
|
||||
MMSYS_ROUTE(MERGE0, DPI1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
|
||||
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE),
|
||||
MMSYS_ROUTE(DSC1, DP_INTF1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
|
||||
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT),
|
||||
MMSYS_ROUTE(DSC1, DPI0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
|
||||
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT),
|
||||
MMSYS_ROUTE(DSC1, DPI1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
|
||||
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT),
|
||||
MMSYS_ROUTE(DSC0, DP_INTF1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
|
||||
MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT),
|
||||
MMSYS_ROUTE(DSC0, DPI0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
|
||||
MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT),
|
||||
MMSYS_ROUTE(DSC0, DPI1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
|
||||
MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT),
|
||||
MMSYS_ROUTE(DSC1, DP_INTF0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
|
||||
MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT),
|
||||
MMSYS_ROUTE(MERGE0, DP_INTF0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
|
||||
MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE),
|
||||
MMSYS_ROUTE(MERGE5, DP_INTF0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
|
||||
MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0),
|
||||
MMSYS_ROUTE(DSC0, DSI0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
|
||||
MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT),
|
||||
MMSYS_ROUTE(DITHER0, DSI0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
|
||||
MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0),
|
||||
MMSYS_ROUTE(DSC1, DSI1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
|
||||
MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT),
|
||||
MMSYS_ROUTE(MERGE0, DSI1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
|
||||
MT8195_SEL_IN_DSI1_FROM_VPP_MERGE),
|
||||
MMSYS_ROUTE(OVL1, WDMA1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
|
||||
MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1),
|
||||
MMSYS_ROUTE(MERGE0, WDMA1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
|
||||
MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE),
|
||||
MMSYS_ROUTE(DSC1, DSI1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN),
|
||||
MMSYS_ROUTE(DSC1, DP_INTF0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN),
|
||||
MMSYS_ROUTE(DSC1, DP_INTF1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN),
|
||||
MMSYS_ROUTE(DSC1, DPI0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN),
|
||||
MMSYS_ROUTE(DSC1, DPI1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN),
|
||||
MMSYS_ROUTE(DSC1, MERGE0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN),
|
||||
MMSYS_ROUTE(DITHER1, DSI1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1),
|
||||
MMSYS_ROUTE(DITHER1, DP_INTF0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1),
|
||||
MMSYS_ROUTE(DITHER1, DPI0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1),
|
||||
MMSYS_ROUTE(DITHER1, DPI1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1),
|
||||
MMSYS_ROUTE(OVL0, WDMA0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
|
||||
MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0),
|
||||
MMSYS_ROUTE(DITHER0, DSC0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
|
||||
MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN),
|
||||
MMSYS_ROUTE(DITHER0, DSI0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
|
||||
MT8195_SOUT_DISP_DITHER0_TO_DSI0),
|
||||
MMSYS_ROUTE(DITHER1, DSC1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
|
||||
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN),
|
||||
MMSYS_ROUTE(DITHER1, MERGE0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
|
||||
MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE),
|
||||
MMSYS_ROUTE(DITHER1, DSI1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
|
||||
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT),
|
||||
MMSYS_ROUTE(DITHER1, DP_INTF0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
|
||||
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT),
|
||||
MMSYS_ROUTE(DITHER1, DP_INTF1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
|
||||
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT),
|
||||
MMSYS_ROUTE(DITHER1, DPI0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
|
||||
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT),
|
||||
MMSYS_ROUTE(DITHER1, DPI1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
|
||||
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT),
|
||||
MMSYS_ROUTE(MERGE5, MERGE0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
|
||||
MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE),
|
||||
MMSYS_ROUTE(MERGE5, DP_INTF0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
|
||||
MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0),
|
||||
MMSYS_ROUTE(MERGE0, DSI1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
|
||||
MT8195_SOUT_VPP_MERGE_TO_DSI1),
|
||||
MMSYS_ROUTE(MERGE0, DP_INTF0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
|
||||
MT8195_SOUT_VPP_MERGE_TO_DP_INTF0),
|
||||
MMSYS_ROUTE(MERGE0, DP_INTF1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
|
||||
MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0),
|
||||
MMSYS_ROUTE(MERGE0, DPI0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
|
||||
MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0),
|
||||
MMSYS_ROUTE(MERGE0, DPI1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
|
||||
MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0),
|
||||
MMSYS_ROUTE(MERGE0, WDMA1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
|
||||
MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1),
|
||||
MMSYS_ROUTE(MERGE0, DSC0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
|
||||
MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN),
|
||||
MMSYS_ROUTE(MERGE0, DSC1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK,
|
||||
MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN),
|
||||
MMSYS_ROUTE(DSC0, DSI0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
|
||||
MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0),
|
||||
MMSYS_ROUTE(DSC0, DP_INTF1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
|
||||
MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0),
|
||||
MMSYS_ROUTE(DSC0, DPI0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
|
||||
MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0),
|
||||
MMSYS_ROUTE(DSC0, DPI1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
|
||||
MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0),
|
||||
MMSYS_ROUTE(DSC0, MERGE0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
|
||||
MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE),
|
||||
MMSYS_ROUTE(DSC1, DSI1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
|
||||
MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1),
|
||||
MMSYS_ROUTE(DSC1, DP_INTF0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
|
||||
MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0),
|
||||
MMSYS_ROUTE(DSC1, DP_INTF1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
|
||||
MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0),
|
||||
MMSYS_ROUTE(DSC1, DPI0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
|
||||
MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0),
|
||||
MMSYS_ROUTE(DSC1, DPI1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
|
||||
MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0),
|
||||
MMSYS_ROUTE(DSC1, MERGE0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
|
||||
MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE),
|
||||
};
|
||||
|
||||
static const struct mtk_mmsys_routes mmsys_mt8195_vdo1_routing_table[] = {
|
||||
{
|
||||
DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1,
|
||||
MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
|
||||
MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
|
||||
}, {
|
||||
DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1,
|
||||
MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
|
||||
MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
|
||||
}, {
|
||||
DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2,
|
||||
MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
|
||||
MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
|
||||
MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
|
||||
MT8195_SOUT_TO_MIXER_IN1_SEL
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
|
||||
MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
|
||||
MT8195_SOUT_TO_MIXER_IN2_SEL
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
|
||||
MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
|
||||
MT8195_SOUT_TO_MIXER_IN3_SEL
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
|
||||
MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
|
||||
MT8195_SOUT_TO_MIXER_IN4_SEL
|
||||
}, {
|
||||
DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
|
||||
MT8195_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
|
||||
MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
|
||||
MT8195_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
|
||||
MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
|
||||
MT8195_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
|
||||
MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
|
||||
MT8195_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
|
||||
MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
|
||||
MT8195_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
|
||||
MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
|
||||
}, {
|
||||
DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
|
||||
MT8195_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
|
||||
MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
|
||||
}, {
|
||||
DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
|
||||
MT8195_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
|
||||
MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
|
||||
MT8195_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
|
||||
MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
|
||||
MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
|
||||
MT8195_MERGE4_SOUT_TO_DPI1_SEL
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
|
||||
MT8195_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
|
||||
MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
|
||||
MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
|
||||
MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL
|
||||
}
|
||||
MMSYS_ROUTE(MDP_RDMA0, MERGE1,
|
||||
MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
|
||||
MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0),
|
||||
MMSYS_ROUTE(MDP_RDMA1, MERGE1,
|
||||
MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
|
||||
MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1),
|
||||
MMSYS_ROUTE(MDP_RDMA2, MERGE2,
|
||||
MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
|
||||
MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2),
|
||||
MMSYS_ROUTE(MERGE1, ETHDR_MIXER,
|
||||
MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
|
||||
MT8195_SOUT_TO_MIXER_IN1_SEL),
|
||||
MMSYS_ROUTE(MERGE2, ETHDR_MIXER,
|
||||
MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
|
||||
MT8195_SOUT_TO_MIXER_IN2_SEL),
|
||||
MMSYS_ROUTE(MERGE3, ETHDR_MIXER,
|
||||
MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
|
||||
MT8195_SOUT_TO_MIXER_IN3_SEL),
|
||||
MMSYS_ROUTE(MERGE4, ETHDR_MIXER,
|
||||
MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
|
||||
MT8195_SOUT_TO_MIXER_IN4_SEL),
|
||||
MMSYS_ROUTE(ETHDR_MIXER, MERGE5,
|
||||
MT8195_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
|
||||
MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL),
|
||||
MMSYS_ROUTE(MERGE1, ETHDR_MIXER,
|
||||
MT8195_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
|
||||
MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT),
|
||||
MMSYS_ROUTE(MERGE2, ETHDR_MIXER,
|
||||
MT8195_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
|
||||
MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT),
|
||||
MMSYS_ROUTE(MERGE3, ETHDR_MIXER,
|
||||
MT8195_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
|
||||
MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT),
|
||||
MMSYS_ROUTE(MERGE4, ETHDR_MIXER,
|
||||
MT8195_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
|
||||
MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT),
|
||||
MMSYS_ROUTE(ETHDR_MIXER, MERGE5,
|
||||
MT8195_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
|
||||
MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER),
|
||||
MMSYS_ROUTE(ETHDR_MIXER, MERGE5,
|
||||
MT8195_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
|
||||
MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT),
|
||||
MMSYS_ROUTE(MERGE5, DPI1,
|
||||
MT8195_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
|
||||
MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT),
|
||||
MMSYS_ROUTE(MERGE5, DPI1,
|
||||
MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
|
||||
MT8195_MERGE4_SOUT_TO_DPI1_SEL),
|
||||
MMSYS_ROUTE(MERGE5, DP_INTF1,
|
||||
MT8195_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
|
||||
MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT),
|
||||
MMSYS_ROUTE(MERGE5, DP_INTF1,
|
||||
MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
|
||||
MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL),
|
||||
};
|
||||
#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
|
||||
|
|
|
|||
|
|
@ -28,47 +28,37 @@
|
|||
#define MT8365_DPI0_SEL_IN_RDMA1 0x0
|
||||
|
||||
static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = {
|
||||
{
|
||||
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
|
||||
MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN,
|
||||
MT8365_DISP_MS_IN_OUT_MASK, MT8365_OVL0_MOUT_PATH0_SEL
|
||||
}, {
|
||||
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
|
||||
MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN,
|
||||
MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_SEL_IN_OVL0
|
||||
}, {
|
||||
DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
|
||||
MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL,
|
||||
MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_SOUT_COLOR0
|
||||
}, {
|
||||
DDP_COMPONENT_COLOR0, DDP_COMPONENT_CCORR,
|
||||
MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN,
|
||||
MT8365_DISP_MS_IN_OUT_MASK, MT8365_DISP_COLOR_SEL_IN_COLOR0
|
||||
}, {
|
||||
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
|
||||
MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN,
|
||||
MT8365_DISP_MS_IN_OUT_MASK, MT8365_DITHER_MOUT_EN_DSI0
|
||||
}, {
|
||||
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
|
||||
MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
|
||||
MT8365_DISP_MS_IN_OUT_MASK, MT8365_DSI0_SEL_IN_DITHER
|
||||
}, {
|
||||
DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
|
||||
MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN,
|
||||
MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_RSZ0_SEL_IN_RDMA0
|
||||
}, {
|
||||
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
|
||||
MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00,
|
||||
MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK, MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK
|
||||
}, {
|
||||
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
|
||||
MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN,
|
||||
MT8365_DISP_MS_IN_OUT_MASK, MT8365_DPI0_SEL_IN_RDMA1
|
||||
}, {
|
||||
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
|
||||
MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL,
|
||||
MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA1_SOUT_DPI0
|
||||
},
|
||||
MMSYS_ROUTE(OVL0, RDMA0,
|
||||
MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN,
|
||||
MT8365_DISP_MS_IN_OUT_MASK, MT8365_OVL0_MOUT_PATH0_SEL),
|
||||
MMSYS_ROUTE(OVL0, RDMA0,
|
||||
MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN,
|
||||
MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_SEL_IN_OVL0),
|
||||
MMSYS_ROUTE(RDMA0, COLOR0,
|
||||
MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL,
|
||||
MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_SOUT_COLOR0),
|
||||
MMSYS_ROUTE(COLOR0, CCORR,
|
||||
MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN,
|
||||
MT8365_DISP_MS_IN_OUT_MASK, MT8365_DISP_COLOR_SEL_IN_COLOR0),
|
||||
MMSYS_ROUTE(DITHER0, DSI0,
|
||||
MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN,
|
||||
MT8365_DISP_MS_IN_OUT_MASK, MT8365_DITHER_MOUT_EN_DSI0),
|
||||
MMSYS_ROUTE(DITHER0, DSI0,
|
||||
MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
|
||||
MT8365_DISP_MS_IN_OUT_MASK, MT8365_DSI0_SEL_IN_DITHER),
|
||||
MMSYS_ROUTE(RDMA0, COLOR0,
|
||||
MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN,
|
||||
MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_RSZ0_SEL_IN_RDMA0),
|
||||
MMSYS_ROUTE(RDMA1, DPI0,
|
||||
MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00,
|
||||
MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK,
|
||||
MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK),
|
||||
MMSYS_ROUTE(RDMA1, DPI0,
|
||||
MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN,
|
||||
MT8365_DISP_MS_IN_OUT_MASK, MT8365_DPI0_SEL_IN_RDMA1),
|
||||
MMSYS_ROUTE(RDMA1, DPI0,
|
||||
MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL,
|
||||
MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA1_SOUT_DPI0),
|
||||
};
|
||||
|
||||
#endif /* __SOC_MEDIATEK_MT8365_MMSYS_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user