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drm/xe/guc: Add support for G2G communications
Some features require inter-GuC communication channels on multi-tile devices. So allocate and enable such. v2: Correct use of xe_bo_get/put (review feedback from Matthew Brost) Add extra assert, re-order a calculation for better clarity and add comments to slot calculation (review feedback from Daniele). Also slightly re-work the slot calc to avoid code duplication. Signed-off-by: John Harrison <John.C.Harrison@Intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241120000222.204095-3-John.C.Harrison@Intel.com
This commit is contained in:
John Harrison
parent
5a3b0df25d
commit
a9f7b97dda
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@ -134,6 +134,8 @@ enum xe_guc_action {
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XE_GUC_ACTION_DEREGISTER_CONTEXT = 0x4503,
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XE_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505,
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XE_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506,
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XE_GUC_ACTION_REGISTER_G2G = 0x4507,
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XE_GUC_ACTION_DEREGISTER_G2G = 0x4508,
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XE_GUC_ACTION_DEREGISTER_CONTEXT_DONE = 0x4600,
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XE_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC = 0x4601,
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XE_GUC_ACTION_CLIENT_SOFT_RESET = 0x5507,
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@ -218,4 +220,22 @@ enum xe_guc_tlb_inval_mode {
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XE_GUC_TLB_INVAL_MODE_LITE = 0x1,
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};
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/*
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* GuC to GuC communication (de-)registration fields:
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*/
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enum xe_guc_g2g_type {
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XE_G2G_TYPE_IN = 0x0,
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XE_G2G_TYPE_OUT,
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XE_G2G_TYPE_LIMIT,
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};
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#define XE_G2G_REGISTER_DEVICE REG_GENMASK(16, 16)
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#define XE_G2G_REGISTER_TILE REG_GENMASK(15, 12)
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#define XE_G2G_REGISTER_TYPE REG_GENMASK(11, 8)
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#define XE_G2G_REGISTER_SIZE REG_GENMASK(7, 0)
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#define XE_G2G_DEREGISTER_DEVICE REG_GENMASK(16, 16)
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#define XE_G2G_DEREGISTER_TILE REG_GENMASK(15, 12)
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#define XE_G2G_DEREGISTER_TYPE REG_GENMASK(11, 8)
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#endif
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@ -44,7 +44,15 @@ static u32 guc_bo_ggtt_addr(struct xe_guc *guc,
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struct xe_bo *bo)
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{
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struct xe_device *xe = guc_to_xe(guc);
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u32 addr = xe_bo_ggtt_addr(bo);
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u32 addr;
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/*
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* For most BOs, the address on the allocating tile is fine. However for
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* some, e.g. G2G CTB, the address on a specific tile is required as it
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* might be different for each tile. So, just always ask for the address
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* on the target GuC.
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*/
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addr = __xe_bo_ggtt_addr(bo, gt_to_tile(guc_to_gt(guc))->id);
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/* GuC addresses above GUC_GGTT_TOP don't map through the GTT */
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xe_assert(xe, addr >= xe_wopcm_size(guc_to_xe(guc)));
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@ -244,6 +252,293 @@ static void guc_write_params(struct xe_guc *guc)
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xe_mmio_write32(>->mmio, SOFT_SCRATCH(1 + i), guc->params[i]);
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}
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static int guc_action_register_g2g_buffer(struct xe_guc *guc, u32 type, u32 dst_tile, u32 dst_dev,
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u32 desc_addr, u32 buff_addr, u32 size)
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{
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struct xe_gt *gt = guc_to_gt(guc);
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struct xe_device *xe = gt_to_xe(gt);
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u32 action[] = {
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XE_GUC_ACTION_REGISTER_G2G,
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FIELD_PREP(XE_G2G_REGISTER_SIZE, size / SZ_4K - 1) |
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FIELD_PREP(XE_G2G_REGISTER_TYPE, type) |
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FIELD_PREP(XE_G2G_REGISTER_TILE, dst_tile) |
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FIELD_PREP(XE_G2G_REGISTER_DEVICE, dst_dev),
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desc_addr,
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buff_addr,
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};
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xe_assert(xe, (type == XE_G2G_TYPE_IN) || (type == XE_G2G_TYPE_OUT));
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xe_assert(xe, !(size % SZ_4K));
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return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action));
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}
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static int guc_action_deregister_g2g_buffer(struct xe_guc *guc, u32 type, u32 dst_tile, u32 dst_dev)
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{
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struct xe_gt *gt = guc_to_gt(guc);
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struct xe_device *xe = gt_to_xe(gt);
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u32 action[] = {
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XE_GUC_ACTION_DEREGISTER_G2G,
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FIELD_PREP(XE_G2G_DEREGISTER_TYPE, type) |
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FIELD_PREP(XE_G2G_DEREGISTER_TILE, dst_tile) |
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FIELD_PREP(XE_G2G_DEREGISTER_DEVICE, dst_dev),
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};
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xe_assert(xe, (type == XE_G2G_TYPE_IN) || (type == XE_G2G_TYPE_OUT));
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return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action));
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}
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#define G2G_DEV(gt) (((gt)->info.type == XE_GT_TYPE_MAIN) ? 0 : 1)
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#define G2G_BUFFER_SIZE (SZ_4K)
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#define G2G_DESC_SIZE (64)
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#define G2G_DESC_AREA_SIZE (SZ_4K)
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/*
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* Generate a unique id for each bi-directional CTB for each pair of
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* near and far tiles/devices. The id can then be used as an index into
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* a single allocation that is sub-divided into multiple CTBs.
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*
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* For example, with two devices per tile and two tiles, the table should
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* look like:
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* Far <tile>.<dev>
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* 0.0 0.1 1.0 1.1
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* N 0.0 --/-- 00/01 02/03 04/05
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* e 0.1 01/00 --/-- 06/07 08/09
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* a 1.0 03/02 07/06 --/-- 10/11
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* r 1.1 05/04 09/08 11/10 --/--
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*
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* Where each entry is Rx/Tx channel id.
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*
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* So GuC #3 (tile 1, dev 1) talking to GuC #2 (tile 1, dev 0) would
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* be reading from channel #11 and writing to channel #10. Whereas,
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* GuC #2 talking to GuC #3 would be read on #10 and write to #11.
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*/
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static unsigned int g2g_slot(u32 near_tile, u32 near_dev, u32 far_tile, u32 far_dev,
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u32 type, u32 max_inst, bool have_dev)
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{
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u32 near = near_tile, far = far_tile;
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u32 idx = 0, x, y, direction;
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int i;
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if (have_dev) {
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near = (near << 1) | near_dev;
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far = (far << 1) | far_dev;
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}
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/* No need to send to one's self */
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if (far == near)
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return -1;
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if (far > near) {
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/* Top right table half */
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x = far;
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y = near;
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/* T/R is 'forwards' direction */
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direction = type;
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} else {
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/* Bottom left table half */
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x = near;
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y = far;
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/* B/L is 'backwards' direction */
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direction = (1 - type);
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}
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/* Count the rows prior to the target */
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for (i = y; i > 0; i--)
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idx += max_inst - i;
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/* Count this row up to the target */
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idx += (x - 1 - y);
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/* Slots are in Rx/Tx pairs */
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idx *= 2;
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/* Pick Rx/Tx direction */
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idx += direction;
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return idx;
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}
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static int guc_g2g_register(struct xe_guc *near_guc, struct xe_gt *far_gt, u32 type, bool have_dev)
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{
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struct xe_gt *near_gt = guc_to_gt(near_guc);
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struct xe_device *xe = gt_to_xe(near_gt);
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struct xe_bo *g2g_bo;
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u32 near_tile = gt_to_tile(near_gt)->id;
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u32 near_dev = G2G_DEV(near_gt);
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u32 far_tile = gt_to_tile(far_gt)->id;
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u32 far_dev = G2G_DEV(far_gt);
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u32 max = xe->info.gt_count;
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u32 base, desc, buf;
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int slot;
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/* G2G is not allowed between different cards */
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xe_assert(xe, xe == gt_to_xe(far_gt));
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g2g_bo = near_guc->g2g.bo;
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xe_assert(xe, g2g_bo);
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slot = g2g_slot(near_tile, near_dev, far_tile, far_dev, type, max, have_dev);
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xe_assert(xe, slot >= 0);
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base = guc_bo_ggtt_addr(near_guc, g2g_bo);
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desc = base + slot * G2G_DESC_SIZE;
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buf = base + G2G_DESC_AREA_SIZE + slot * G2G_BUFFER_SIZE;
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xe_assert(xe, (desc - base + G2G_DESC_SIZE) <= G2G_DESC_AREA_SIZE);
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xe_assert(xe, (buf - base + G2G_BUFFER_SIZE) <= g2g_bo->size);
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return guc_action_register_g2g_buffer(near_guc, type, far_tile, far_dev,
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desc, buf, G2G_BUFFER_SIZE);
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}
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static void guc_g2g_deregister(struct xe_guc *guc, u32 far_tile, u32 far_dev, u32 type)
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{
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guc_action_deregister_g2g_buffer(guc, type, far_tile, far_dev);
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}
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static u32 guc_g2g_size(struct xe_guc *guc)
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{
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struct xe_gt *gt = guc_to_gt(guc);
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struct xe_device *xe = gt_to_xe(gt);
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unsigned int count = xe->info.gt_count;
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u32 num_channels = (count * (count - 1)) / 2;
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xe_assert(xe, num_channels * XE_G2G_TYPE_LIMIT * G2G_DESC_SIZE <= G2G_DESC_AREA_SIZE);
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return num_channels * XE_G2G_TYPE_LIMIT * G2G_BUFFER_SIZE + G2G_DESC_AREA_SIZE;
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}
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static bool xe_guc_g2g_wanted(struct xe_device *xe)
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{
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/* Can't do GuC to GuC communication if there is only one GuC */
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if (xe->info.gt_count <= 1)
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return false;
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/* No current user */
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return false;
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}
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static int guc_g2g_alloc(struct xe_guc *guc)
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{
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struct xe_gt *gt = guc_to_gt(guc);
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struct xe_device *xe = gt_to_xe(gt);
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struct xe_tile *tile = gt_to_tile(gt);
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struct xe_bo *bo;
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u32 g2g_size;
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if (guc->g2g.bo)
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return 0;
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if (gt->info.id != 0) {
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struct xe_gt *root_gt = xe_device_get_gt(xe, 0);
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struct xe_guc *root_guc = &root_gt->uc.guc;
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struct xe_bo *bo;
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bo = xe_bo_get(root_guc->g2g.bo);
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if (!bo)
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return -ENODEV;
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guc->g2g.bo = bo;
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guc->g2g.owned = false;
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return 0;
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}
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g2g_size = guc_g2g_size(guc);
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bo = xe_managed_bo_create_pin_map(xe, tile, g2g_size,
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XE_BO_FLAG_VRAM_IF_DGFX(tile) |
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XE_BO_FLAG_GGTT |
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XE_BO_FLAG_GGTT_ALL |
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XE_BO_FLAG_GGTT_INVALIDATE);
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if (IS_ERR(bo))
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return PTR_ERR(bo);
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xe_map_memset(xe, &bo->vmap, 0, 0, g2g_size);
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guc->g2g.bo = bo;
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guc->g2g.owned = true;
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return 0;
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}
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static void guc_g2g_fini(struct xe_guc *guc)
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{
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if (!guc->g2g.bo)
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return;
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/* Unpinning the owned object is handled by generic shutdown */
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if (!guc->g2g.owned)
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xe_bo_put(guc->g2g.bo);
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guc->g2g.bo = NULL;
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}
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static int guc_g2g_start(struct xe_guc *guc)
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{
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struct xe_gt *far_gt, *gt = guc_to_gt(guc);
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struct xe_device *xe = gt_to_xe(gt);
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unsigned int i, j;
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int t, err;
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bool have_dev;
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if (!guc->g2g.bo) {
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int ret;
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ret = guc_g2g_alloc(guc);
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if (ret)
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return ret;
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}
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/* GuC interface will need extending if more GT device types are ever created. */
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xe_gt_assert(gt, (gt->info.type == XE_GT_TYPE_MAIN) || (gt->info.type == XE_GT_TYPE_MEDIA));
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/* Channel numbering depends on whether there are multiple GTs per tile */
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have_dev = xe->info.gt_count > xe->info.tile_count;
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for_each_gt(far_gt, xe, i) {
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u32 far_tile, far_dev;
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if (far_gt->info.id == gt->info.id)
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continue;
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far_tile = gt_to_tile(far_gt)->id;
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far_dev = G2G_DEV(far_gt);
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for (t = 0; t < XE_G2G_TYPE_LIMIT; t++) {
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err = guc_g2g_register(guc, far_gt, t, have_dev);
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if (err) {
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while (--t >= 0)
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guc_g2g_deregister(guc, far_tile, far_dev, t);
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goto err_deregister;
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}
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}
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}
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return 0;
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err_deregister:
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for_each_gt(far_gt, xe, j) {
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u32 tile, dev;
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if (far_gt->info.id == gt->info.id)
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continue;
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if (j >= i)
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break;
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tile = gt_to_tile(far_gt)->id;
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dev = G2G_DEV(far_gt);
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for (t = 0; t < XE_G2G_TYPE_LIMIT; t++)
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guc_g2g_deregister(guc, tile, dev, t);
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}
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return err;
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}
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static void guc_fini_hw(void *arg)
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{
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struct xe_guc *guc = arg;
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@ -253,6 +548,8 @@ static void guc_fini_hw(void *arg)
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fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL);
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xe_uc_fini_hw(&guc_to_gt(guc)->uc);
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xe_force_wake_put(gt_to_fw(gt), fw_ref);
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guc_g2g_fini(guc);
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}
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/**
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@ -423,7 +720,16 @@ int xe_guc_init_post_hwconfig(struct xe_guc *guc)
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int xe_guc_post_load_init(struct xe_guc *guc)
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{
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int ret;
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xe_guc_ads_populate_post_load(&guc->ads);
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if (xe_guc_g2g_wanted(guc_to_xe(guc))) {
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ret = guc_g2g_start(guc);
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if (ret)
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return ret;
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}
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guc->submission_state.enabled = true;
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return 0;
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@ -64,6 +64,15 @@ struct xe_guc {
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struct xe_guc_pc pc;
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/** @dbm: GuC Doorbell Manager */
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struct xe_guc_db_mgr dbm;
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/** @g2g: GuC to GuC communication state */
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struct {
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/** @g2g.bo: Storage for GuC to GuC communication channels */
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struct xe_bo *bo;
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/** @g2g.owned: Is the BO owned by this GT or just mapped in */
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bool owned;
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} g2g;
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/** @submission_state: GuC submission state */
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struct {
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/** @submission_state.idm: GuC context ID Manager */
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@ -79,6 +88,7 @@ struct xe_guc {
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/** @submission_state.fini_wq: submit fini wait queue */
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wait_queue_head_t fini_wq;
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} submission_state;
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/** @hwconfig: Hardware config state */
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struct {
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/** @hwconfig.bo: buffer object of the hardware config */
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