From ccb935d44e72172ef34c3459362350e4de64265c Mon Sep 17 00:00:00 2001 From: Phani Kumar Uppalapati Date: Tue, 5 Jul 2022 14:36:46 -0700 Subject: [PATCH] wcd939x-usbss: Add i2c driver for wcd939x usbss Add i2c driver for wcd939x usb subsystem for analog audio, dp aux and usb functionality. Change-Id: I799ea6ff9207bd88b5846d44e894d07f2d0b53c5 Signed-off-by: Phani Kumar Uppalapati Signed-off-by: Mayank Rana Signed-off-by: Rajkumar Subbiah Signed-off-by: Prasad Kumpatla --- drivers/soc/qcom/Kconfig | 10 + drivers/soc/qcom/Makefile | 6 +- drivers/soc/qcom/wcd-usbss-priv.h | 39 + drivers/soc/qcom/wcd-usbss-reg-masks.h | 1792 +++++++++++++++++++++++ drivers/soc/qcom/wcd-usbss-reg-shifts.h | 1792 +++++++++++++++++++++++ drivers/soc/qcom/wcd-usbss-registers.h | 501 +++++++ drivers/soc/qcom/wcd-usbss-regmap.c | 503 +++++++ drivers/soc/qcom/wcd-usbss-tables.c | 463 ++++++ drivers/soc/qcom/wcd-usbss-utils.c | 272 ++++ drivers/soc/qcom/wcd939x-i2c.c | 588 ++++++++ include/linux/soc/qcom/wcd939x-i2c.h | 59 + 11 files changed, 6024 insertions(+), 1 deletion(-) create mode 100644 drivers/soc/qcom/wcd-usbss-priv.h create mode 100644 drivers/soc/qcom/wcd-usbss-reg-masks.h create mode 100644 drivers/soc/qcom/wcd-usbss-reg-shifts.h create mode 100644 drivers/soc/qcom/wcd-usbss-registers.h create mode 100644 drivers/soc/qcom/wcd-usbss-regmap.c create mode 100644 drivers/soc/qcom/wcd-usbss-tables.c create mode 100644 drivers/soc/qcom/wcd-usbss-utils.c create mode 100644 drivers/soc/qcom/wcd939x-i2c.c create mode 100644 include/linux/soc/qcom/wcd939x-i2c.h diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index 68c026d5e784..8aa1439bb6b5 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -667,6 +667,16 @@ config QTI_HW_KEY_MANAGER HWKM hardware to perform key operations from the kernel which will be used for storage encryption. +config QCOM_WCD_USBSS_I2C + tristate "WCD USBSS chip with I2C" + select REGMAP + depends on I2C + help + Support for the WCD939X USBSS IC switch chip controlled + using I2C. This driver provides common support + for accessing the device, switching between USB and Audio + modes, changing orientation. + config QCOM_MINIDUMP tristate "QCOM Minidump Support" depends on QCOM_SMEM || ARCH_QTI_VM diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index e506399206ba..0a7ea3833436 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -71,4 +71,8 @@ obj-$(CONFIG_QCOM_CPUCP) += qcom_cpucp.o obj-$(CONFIG_QTI_CPUCP_LOG) += cpucp_log.o obj-$(CONFIG_QTI_SYS_PM_VX) += sys_pm_vx.o obj-$(CONFIG_MSM_PERFORMANCE) += msm_performance.o - +obj-$(CONFIG_QCOM_WCD_USBSS_I2C) += wcd_usbss_i2c.o +wcd_usbss_i2c-y += wcd-usbss-regmap.o +wcd_usbss_i2c-y += wcd-usbss-tables.o +wcd_usbss_i2c-y += wcd-usbss-utils.o +wcd_usbss_i2c-y += wcd939x-i2c.o diff --git a/drivers/soc/qcom/wcd-usbss-priv.h b/drivers/soc/qcom/wcd-usbss-priv.h new file mode 100644 index 000000000000..cb9e2013e745 --- /dev/null +++ b/drivers/soc/qcom/wcd-usbss-priv.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ +#ifndef WCD_USBSS_PRIV_H +#define WCD_USBSS_PRIV_H + +#include +#include +#include +#include +#include +#include +#include +#include + +#define WCD_USBSS_SUPPLY_MAX 4 +struct wcd_usbss_ctxt { + struct regmap *regmap; + struct device *dev; + struct i2c_client *client; + struct notifier_block ucsi_nb; + atomic_t usbc_mode; + struct work_struct usbc_analog_work; + struct blocking_notifier_head wcd_usbss_notifier; + struct mutex notification_lock; + struct regulator_bulk_data supplies[WCD_USBSS_SUPPLY_MAX]; + struct pinctrl *rst_pins; + struct pinctrl_state *rst_pins_active; + struct pinctrl_state *rst_pins_sleep; + u8 prev_pg; + bool prev_pg_valid; + struct mutex io_lock; +}; + +extern struct regmap *wcd_usbss_regmap_init(struct device *dev, + const struct regmap_config *config); +extern struct regmap_config wcd_usbss_regmap_config; +#endif /* WCD_USBSS_PRIV_H */ diff --git a/drivers/soc/qcom/wcd-usbss-reg-masks.h b/drivers/soc/qcom/wcd-usbss-reg-masks.h new file mode 100644 index 000000000000..0d5ef1a8eeca --- /dev/null +++ b/drivers/soc/qcom/wcd-usbss-reg-masks.h @@ -0,0 +1,1792 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef WCD_USBSS_REG_MASKS_H +#define WCD_USBSS_REG_MASKS_H +#include +#include +#include "wcd-usbss-registers.h" + +/* Use in conjunction with wcd_usbss-reg-shifts.c for field values. */ +/* field_value = (register_value & field_mask) >> field_shift */ + +#define FIELD_MASK(register_name, field_name) \ +WCD_USBSS_##register_name##_##field_name##_MASK + +/* WCD_USBSS_PAGE0_PAGE Fields: */ +#define WCD_USBSS_PAGE0_PAGE_PAGE_REG_MASK 0xff + + +/* WCD_USBSS_PMP_EN Fields: */ +#define WCD_USBSS_PMP_EN_SPARE_BIT_7_MASK 0x80 +#define WCD_USBSS_PMP_EN_PMP_OUT_APD_MASK 0x40 +#define WCD_USBSS_PMP_EN_IBIAS_HALF_MASK 0x20 +#define WCD_USBSS_PMP_EN_PFM_MODE_MASK 0x10 +#define WCD_USBSS_PMP_EN_VREFGEN_MASK 0x08 +#define WCD_USBSS_PMP_EN_REGULATE_OUT_MASK 0x04 +#define WCD_USBSS_PMP_EN_CLK_PMP_MASK 0x02 +#define WCD_USBSS_PMP_EN_LOC_CTRL_EN_MASK 0x01 + +/* WCD_USBSS_PMP_OUT1 Fields: */ +#define WCD_USBSS_PMP_OUT1_SPARE_BITS_7_5_MASK 0xe0 +#define WCD_USBSS_PMP_OUT1_LOC_CTRL_TRIM_MASK 0x10 +#define WCD_USBSS_PMP_OUT1_PMP_OUT_PCT_MASK 0x0f + +/* WCD_USBSS_PMP_OUT2 Fields: */ +#define WCD_USBSS_PMP_OUT2_SPARE_BITS_7_6_MASK 0xc0 +#define WCD_USBSS_PMP_OUT2_VDWN_AUD_MASK 0x20 +#define WCD_USBSS_PMP_OUT2_VUP_PFM_MASK 0x10 +#define WCD_USBSS_PMP_OUT2_PMP_OUT_HYST_MASK 0x0c +#define WCD_USBSS_PMP_OUT2_PMP_OUT_MIN_MAX_MASK 0x03 + +/* WCD_USBSS_PMP_CLK Fields: */ +#define WCD_USBSS_PMP_CLK_SPARE_BITS_7_6_MASK 0xc0 +#define WCD_USBSS_PMP_CLK_DLY_NOV_MASK 0x30 +#define WCD_USBSS_PMP_CLK_LOC_CTRL_CLK_DIV_MASK 0x08 +#define WCD_USBSS_PMP_CLK_CLK_DIV_MASK 0x04 +#define WCD_USBSS_PMP_CLK_CLK_DIV_VAL_MASK 0x03 + +/* WCD_USBSS_PMP_MISC1 Fields: */ +#define WCD_USBSS_PMP_MISC1_SPARE_BITS_7_6_MASK 0xc0 +#define WCD_USBSS_PMP_MISC1_LOC_CTRL_ALL_MASK 0x20 +#define WCD_USBSS_PMP_MISC1_LOC_CTRL_VREF_MASK 0x10 +#define WCD_USBSS_PMP_MISC1_VREF_SEL_MASK 0x0c +#define WCD_USBSS_PMP_MISC1_VREF2ATEST_MASK 0x02 +#define WCD_USBSS_PMP_MISC1_CLEAR_PMP_RDY_MASK 0x01 + +/* WCD_USBSS_PMP_MISC2 Fields: */ +#define WCD_USBSS_PMP_MISC2_SPARE_BITS_7_3_MASK 0xf8 +#define WCD_USBSS_PMP_MISC2_PFM_MODE_STATUS_MASK 0x04 +#define WCD_USBSS_PMP_MISC2_PMP_ENABLE_STATUS_MASK 0x02 +#define WCD_USBSS_PMP_MISC2_PMP_RDY_STATUS_MASK 0x01 + + +/* WCD_USBSS_RCO_EN Fields: */ +#define WCD_USBSS_RCO_EN_SPARE_BITS_7_3_MASK 0xf8 +#define WCD_USBSS_RCO_EN_OTA_OPTION_MASK 0x04 +#define WCD_USBSS_RCO_EN_ENABLE_RCO_MASK 0x02 +#define WCD_USBSS_RCO_EN_LOC_CTRL_EN_MASK 0x01 + +/* WCD_USBSS_RCO_RST Fields: */ +#define WCD_USBSS_RCO_RST_SPARE_BITS_7_2_MASK 0xfc +#define WCD_USBSS_RCO_RST_LOC_CTRL_RST_MASK 0x02 +#define WCD_USBSS_RCO_RST_RESET_MASK 0x01 + +/* WCD_USBSS_RCO_CLK Fields: */ +#define WCD_USBSS_RCO_CLK_SPARE_BITS_7_3_MASK 0xf8 +#define WCD_USBSS_RCO_CLK_RCO_FREQ_C_ICBIAS_MASK 0x07 + +/* WCD_USBSS_RCO_IBIAS Fields: */ +#define WCD_USBSS_RCO_IBIAS_SPARE_BITS_7_2_MASK 0xfc +#define WCD_USBSS_RCO_IBIAS_IB2_MASK 0x02 +#define WCD_USBSS_RCO_IBIAS_IB1_MASK 0x01 + +/* WCD_USBSS_RCO_MISC1 Fields: */ +#define WCD_USBSS_RCO_MISC1_SPARE_BITS_7_3_MASK 0xf8 +#define WCD_USBSS_RCO_MISC1_ATEST_CLK_MASK 0x04 +#define WCD_USBSS_RCO_MISC1_ATEST_COMP_MASK 0x02 +#define WCD_USBSS_RCO_MISC1_ATEST_VIR_MASK 0x01 + +/* WCD_USBSS_RCO_MISC2 Fields: */ +#define WCD_USBSS_RCO_MISC2_SPARE_BITS_7_2_MASK 0xfc +#define WCD_USBSS_RCO_MISC2_COMP_OUT_MASK 0x02 +#define WCD_USBSS_RCO_MISC2_RESET_INT_MASK 0x01 + + +/* WCD_USBSS_DP_EN Fields: */ +#define WCD_USBSS_DP_EN_EN_PATH_MASK 0x80 +#define WCD_USBSS_DP_EN_EN_BIAS_MASK 0x40 +#define WCD_USBSS_DP_EN_EN_PSURGE_MASK 0x20 +#define WCD_USBSS_DP_EN_EN_NSURGE_MASK 0x10 +#define WCD_USBSS_DP_EN_P_THRESH_SEL_MASK 0x0e +#define WCD_USBSS_DP_EN_RED_POFF_THRESH_2X_MASK 0x01 + +/* WCD_USBSS_DP_BIAS Fields: */ +#define WCD_USBSS_DP_BIAS_PCOMP_BIAS_SEL_MASK 0xc0 +#define WCD_USBSS_DP_BIAS_NCOMP_BIAS_SEL_MASK 0x30 +#define WCD_USBSS_DP_BIAS_PCOMP_DYN_BST_EN_MASK 0x08 +#define WCD_USBSS_DP_BIAS_NCOMP_DYN_BST_EN_MASK 0x04 +#define WCD_USBSS_DP_BIAS_EN_CMP_GAIN_RED_MASK 0x02 +#define WCD_USBSS_DP_BIAS_ASSERT_PLDN_ON_PWRDN_MASK 0x01 + +/* WCD_USBSS_DP_DN_MISC1 Fields: */ +#define WCD_USBSS_DP_DN_MISC1_EN_NS_AUD_THRESH_M2P2_DP_MASK 0x80 +#define WCD_USBSS_DP_DN_MISC1_EN_NS_AUD_THRESH_M2P2_DN_MASK 0x40 +#define WCD_USBSS_DP_DN_MISC1_DP_NCOMP_2X_DYN_BST_EN_MASK 0x20 +#define WCD_USBSS_DP_DN_MISC1_DP_PCOMP_2X_DYN_BST_OFF_EN_MASK 0x10 +#define WCD_USBSS_DP_DN_MISC1_DP_PCOMP_2X_DYN_BST_ON_EN_MASK 0x08 +#define WCD_USBSS_DP_DN_MISC1_DN_NCOMP_2X_DYN_BST_EN_MASK 0x04 +#define WCD_USBSS_DP_DN_MISC1_DN_PCOMP_2X_DYN_BST_OFF_EN_MASK 0x02 +#define WCD_USBSS_DP_DN_MISC1_DN_PCOMP_2X_DYN_BST_ON_EN_MASK 0x01 + +/* WCD_USBSS_DN_EN Fields: */ +#define WCD_USBSS_DN_EN_EN_PATH_MASK 0x80 +#define WCD_USBSS_DN_EN_EN_BIAS_MASK 0x40 +#define WCD_USBSS_DN_EN_EN_PSURGE_MASK 0x20 +#define WCD_USBSS_DN_EN_EN_NSURGE_MASK 0x10 +#define WCD_USBSS_DN_EN_P_THRESH_SEL_MASK 0x0e +#define WCD_USBSS_DN_EN_RED_POFF_THRESH_2X_MASK 0x01 + +/* WCD_USBSS_DN_BIAS Fields: */ +#define WCD_USBSS_DN_BIAS_PCOMP_BIAS_SEL_MASK 0xc0 +#define WCD_USBSS_DN_BIAS_NCOMP_BIAS_SEL_MASK 0x30 +#define WCD_USBSS_DN_BIAS_PCOMP_DYN_BST_EN_MASK 0x08 +#define WCD_USBSS_DN_BIAS_NCOMP_DYN_BST_EN_MASK 0x04 +#define WCD_USBSS_DN_BIAS_EN_CMP_GAIN_RED_MASK 0x02 +#define WCD_USBSS_DN_BIAS_ASSERT_PLDN_ON_PWRDN_MASK 0x01 + +/* WCD_USBSS_DP_DN_MISC2 Fields: */ +#define WCD_USBSS_DP_DN_MISC2_RED_POFF_THRESH_3X_DP_MASK 0x80 +#define WCD_USBSS_DP_DN_MISC2_RED_POFF_THRESH_3X_DN_MASK 0x40 +#define WCD_USBSS_DP_DN_MISC2_INC_PON_THRESH_AUDMD_DP_MASK 0x20 +#define WCD_USBSS_DP_DN_MISC2_INC_PON_THRESH_AUDMD_DN_MASK 0x10 +#define WCD_USBSS_DP_DN_MISC2_EN_EXTRA_NCLAMP_MASK 0x0c +#define WCD_USBSS_DP_DN_MISC2_EN_NCLAMP_ALWAYS_MASK 0x02 +#define WCD_USBSS_DP_DN_MISC2_OVERRIDE_EN_NCLAMP_WHEN_DPDN_OVP_OFF_MASK 0x01 + +/* WCD_USBSS_MG1_EN Fields: */ +#define WCD_USBSS_MG1_EN_EN_PATH_MASK 0x80 +#define WCD_USBSS_MG1_EN_EN_BIAS_MASK 0x40 +#define WCD_USBSS_MG1_EN_EN_PSURGE_MASK 0x20 +#define WCD_USBSS_MG1_EN_EN_NSURGE_MASK 0x10 +#define WCD_USBSS_MG1_EN_P_THRESH_SEL_MASK 0x0c +#define WCD_USBSS_MG1_EN_CT_SNS_EN_MASK 0x02 +#define WCD_USBSS_MG1_EN_RED_POFF_THRESH_2X_MASK 0x01 + +/* WCD_USBSS_MG1_BIAS Fields: */ +#define WCD_USBSS_MG1_BIAS_PCOMP_BIAS_SEL_MASK 0xc0 +#define WCD_USBSS_MG1_BIAS_NCOMP_BIAS_SEL_MASK 0x30 +#define WCD_USBSS_MG1_BIAS_PCOMP_DYN_BST_EN_MASK 0x08 +#define WCD_USBSS_MG1_BIAS_NCOMP_DYN_BST_EN_MASK 0x04 +#define WCD_USBSS_MG1_BIAS_EN_CMP_GAIN_RED_MASK 0x02 +#define WCD_USBSS_MG1_BIAS_ASSERT_PLDN_ON_PWRDN_MASK 0x01 + +/* WCD_USBSS_MG1_CTSNS_CTL Fields: */ +#define WCD_USBSS_MG1_CTSNS_CTL_CT_SNS_HP_EN_MASK 0x80 +#define WCD_USBSS_MG1_CTSNS_CTL_OVERRIDE_CTSNS_DYN_DISABLE_MASK 0x40 +#define WCD_USBSS_MG1_CTSNS_CTL_CT_SNS_LP_EN_MASK 0x20 +#define WCD_USBSS_MG1_CTSNS_CTL_GND_PIN_VMODE_THRESH_MASK 0x18 +#define WCD_USBSS_MG1_CTSNS_CTL_D_REG_RST_MASK 0x04 +#define WCD_USBSS_MG1_CTSNS_CTL_ITHRESH_BST_EN_MASK 0x03 + +/* WCD_USBSS_MG1_MISC Fields: */ +#define WCD_USBSS_MG1_MISC_NCOMP_2X_DYN_BST_EN_MASK 0x80 +#define WCD_USBSS_MG1_MISC_PCOMP_2X_DYN_BST_OFF_EN_MASK 0x40 +#define WCD_USBSS_MG1_MISC_PCOMP_2X_DYN_BST_ON_EN_MASK 0x20 +#define WCD_USBSS_MG1_MISC_RED_POFF_THRESH_3X_MASK 0x10 +#define WCD_USBSS_MG1_MISC_ASSERT_PLDN_ON_PWRDN_GSBU1_MASK 0x08 +#define WCD_USBSS_MG1_MISC_INC_NEG_SURGE_THRESH_MG1_MASK 0x04 +#define WCD_USBSS_MG1_MISC_MG1_GNDPIN_EN_OVERRIDE_MASK 0x02 +#define WCD_USBSS_MG1_MISC_MG1_GNDPIN_EN_MASK 0x01 + +/* WCD_USBSS_MG2_EN Fields: */ +#define WCD_USBSS_MG2_EN_EN_PATH_MASK 0x80 +#define WCD_USBSS_MG2_EN_EN_BIAS_MASK 0x40 +#define WCD_USBSS_MG2_EN_EN_PSURGE_MASK 0x20 +#define WCD_USBSS_MG2_EN_EN_NSURGE_MASK 0x10 +#define WCD_USBSS_MG2_EN_P_THRESH_SEL_MASK 0x0c +#define WCD_USBSS_MG2_EN_CT_SNS_EN_MASK 0x02 +#define WCD_USBSS_MG2_EN_RED_POFF_THRESH_2X_MASK 0x01 + +/* WCD_USBSS_MG2_BIAS Fields: */ +#define WCD_USBSS_MG2_BIAS_PCOMP_BIAS_SEL_MASK 0xc0 +#define WCD_USBSS_MG2_BIAS_NCOMP_BIAS_SEL_MASK 0x30 +#define WCD_USBSS_MG2_BIAS_PCOMP_DYN_BST_EN_MASK 0x08 +#define WCD_USBSS_MG2_BIAS_NCOMP_DYN_BST_EN_MASK 0x04 +#define WCD_USBSS_MG2_BIAS_EN_CMP_GAIN_RED_MASK 0x02 +#define WCD_USBSS_MG2_BIAS_ASSERT_PLDN_ON_PWRDN_MASK 0x01 + +/* WCD_USBSS_MG2_CTSNS_CTL Fields: */ +#define WCD_USBSS_MG2_CTSNS_CTL_CT_SNS_HP_EN_MASK 0x80 +#define WCD_USBSS_MG2_CTSNS_CTL_OVERRIDE_CTSNS_DYN_DISABLE_MASK 0x40 +#define WCD_USBSS_MG2_CTSNS_CTL_CT_SNS_LP_EN_MASK 0x20 +#define WCD_USBSS_MG2_CTSNS_CTL_GND_PIN_VMODE_THRESH_MASK 0x18 +#define WCD_USBSS_MG2_CTSNS_CTL_D_REG_RST_MASK 0x04 +#define WCD_USBSS_MG2_CTSNS_CTL_ITHRESH_BST_EN_MASK 0x03 + +/* WCD_USBSS_MG2_MISC Fields: */ +#define WCD_USBSS_MG2_MISC_NCOMP_2X_DYN_BST_EN_MASK 0x80 +#define WCD_USBSS_MG2_MISC_PCOMP_2X_DYN_BST_OFF_EN_MASK 0x40 +#define WCD_USBSS_MG2_MISC_PCOMP_2X_DYN_BST_ON_EN_MASK 0x20 +#define WCD_USBSS_MG2_MISC_RED_POFF_THRESH_3X_MASK 0x10 +#define WCD_USBSS_MG2_MISC_ASSERT_PLDN_ON_PWRDN_GSBU2_MASK 0x08 +#define WCD_USBSS_MG2_MISC_INC_NEG_SURGE_THRESH_MG2_MASK 0x04 +#define WCD_USBSS_MG2_MISC_MG2_GNDPIN_EN_OVERRIDE_MASK 0x02 +#define WCD_USBSS_MG2_MISC_MG2_GNDPIN_EN_MASK 0x01 + +/* WCD_USBSS_BIAS_TOP Fields: */ +#define WCD_USBSS_BIAS_TOP_EN_BIAS_TOP_MASK 0x80 +#define WCD_USBSS_BIAS_TOP_VREF_AMP_BIAS_BST_MASK 0x40 +#define WCD_USBSS_BIAS_TOP_OVP_EN_DPDN_OVERRIDE_MASK 0x20 +#define WCD_USBSS_BIAS_TOP_DIS_NCLAMP_DPDN_MASK 0x10 +#define WCD_USBSS_BIAS_TOP_SPARE_BITS_3_0_MASK 0x0f + +/* WCD_USBSS_VREF_CTRL Fields: */ +#define WCD_USBSS_VREF_CTRL_EN_VREF_AMP_MASK 0x80 +#define WCD_USBSS_VREF_CTRL_VREF_AMP_TUNE_MASK 0x78 +#define WCD_USBSS_VREF_CTRL_VREF_AMP_TUNE_REG_EN_MASK 0x04 +#define WCD_USBSS_VREF_CTRL_HIGH_CAP_DRV_EN_MASK 0x02 +#define WCD_USBSS_VREF_CTRL_SPARE_BITS_0_MASK 0x01 + +/* WCD_USBSS_TOP_MISC1 Fields: */ +#define WCD_USBSS_TOP_MISC1_EN_PLDN_GSBU12_MASK 0x80 +#define WCD_USBSS_TOP_MISC1_D_REG_RST_OVP_INTR_MASK 0x40 +#define WCD_USBSS_TOP_MISC1_SPARE_BITS_5_MASK 0x20 +#define WCD_USBSS_TOP_MISC1_SPARE_BITS_4_3_MASK 0x18 +#define WCD_USBSS_TOP_MISC1_OVP_EN_SBU12_OVERRIDE_MASK 0x04 +#define WCD_USBSS_TOP_MISC1_ATEST_SEL_MASK 0x03 + +/* WCD_USBSS_TOP_MISC2 Fields: */ +#define WCD_USBSS_TOP_MISC2_EN_ADD_PLDN_DP_MASK 0x80 +#define WCD_USBSS_TOP_MISC2_EN_ADD_PLDN_DN_MASK 0x40 +#define WCD_USBSS_TOP_MISC2_EN_ADD_PLDN_MG1_MASK 0x20 +#define WCD_USBSS_TOP_MISC2_EN_ADD_PLDN_MG2_MASK 0x10 +#define WCD_USBSS_TOP_MISC2_EN_PWRUP_CMP_GATE_DP_MASK 0x08 +#define WCD_USBSS_TOP_MISC2_EN_PWRUP_CMP_GATE_DN_MASK 0x04 +#define WCD_USBSS_TOP_MISC2_EN_PWRUP_CMP_GATE_MG1_MASK 0x02 +#define WCD_USBSS_TOP_MISC2_EN_PWRUP_CMP_GATE_MG2_MASK 0x01 + +/* WCD_USBSS_STATUS_1 Fields: */ +#define WCD_USBSS_STATUS_1_CMP_OUT_PS_DP_MASK 0x80 +#define WCD_USBSS_STATUS_1_CMP_OUT_NS_DP_MASK 0x40 +#define WCD_USBSS_STATUS_1_CMP_OUT_PSNS_DP_MASK 0x20 +#define WCD_USBSS_STATUS_1_CMP_OUT_PS_DN_MASK 0x10 +#define WCD_USBSS_STATUS_1_CMP_OUT_NS_DN_MASK 0x08 +#define WCD_USBSS_STATUS_1_CMP_OUT_PSNS_DN_MASK 0x04 +#define WCD_USBSS_STATUS_1_OVP_DP_EN_MASK 0x02 +#define WCD_USBSS_STATUS_1_OVP_DN_EN_MASK 0x01 + +/* WCD_USBSS_STATUS_2 Fields: */ +#define WCD_USBSS_STATUS_2_CMP_OUT_PSNS_MG1_MASK 0x80 +#define WCD_USBSS_STATUS_2_CMP_OUT_GNDSW_OFF_MG1_MASK 0x40 +#define WCD_USBSS_STATUS_2_CT_SNS_OVP_DET_LAT_MG1_MASK 0x20 +#define WCD_USBSS_STATUS_2_CMP_OUT_PS_MG2_MASK 0x10 +#define WCD_USBSS_STATUS_2_CMP_OUT_NS_MG2_MASK 0x08 +#define WCD_USBSS_STATUS_2_CMP_OUT_PSNS_MG2_MASK 0x04 +#define WCD_USBSS_STATUS_2_CMP_OUT_GNDSW_OFF_MG2_MASK 0x02 +#define WCD_USBSS_STATUS_2_CT_SNS_OVP_DET_LAT_MG2_MASK 0x01 + +/* WCD_USBSS_STATUS_3 Fields: */ +#define WCD_USBSS_STATUS_3_VREF_EN_MASK 0x80 +#define WCD_USBSS_STATUS_3_BIAS_TOP_EN_MASK 0x40 +#define WCD_USBSS_STATUS_3_CMP_OUT_PS_MG1_MASK 0x20 +#define WCD_USBSS_STATUS_3_CMP_OUT_NS_MG1_MASK 0x10 +#define WCD_USBSS_STATUS_3_OVP_MG1_EN_MASK 0x08 +#define WCD_USBSS_STATUS_3_OVP_MG2_EN_MASK 0x04 +#define WCD_USBSS_STATUS_3_SPARE_BITS_1_0_MASK 0x03 + + +/* WCD_USBSS_EXT_LIN_EN Fields: */ +#define WCD_USBSS_EXT_LIN_EN_EXT_LIN_EN_OVR_MASK 0x80 +#define WCD_USBSS_EXT_LIN_EN_EXT_GNDL_LIN_EN_REG_MASK 0x40 +#define WCD_USBSS_EXT_LIN_EN_EXT_L_LIN_EN_REG_MASK 0x20 +#define WCD_USBSS_EXT_LIN_EN_EXT_R_LIN_EN_REG_MASK 0x10 +#define WCD_USBSS_EXT_LIN_EN_EXTSW_LIN_PWR_OVR_EN_MASK 0x08 +#define WCD_USBSS_EXT_LIN_EN_EXT_GNDR_LIN_EN_REG_MASK 0x04 +#define WCD_USBSS_EXT_LIN_EN_CP_SWR_MG12_REG_MASK 0x02 +#define WCD_USBSS_EXT_LIN_EN_D_EXT_GND_LIN_BYP_MASK 0x01 + +/* WCD_USBSS_INT_LIN_EN Fields: */ +#define WCD_USBSS_INT_LIN_EN_INT_LIN_EN_OVR_MASK 0x80 +#define WCD_USBSS_INT_LIN_EN_INT_L_LIN_EN_REG_MASK 0x40 +#define WCD_USBSS_INT_LIN_EN_INT_R_LIN_EN_REG_MASK 0x20 +#define WCD_USBSS_INT_LIN_EN_INTSW_LIN_PWR_OVR_EN_MASK 0x10 +#define WCD_USBSS_INT_LIN_EN_LDO_SWR_MG12_REG_MASK 0x08 +#define WCD_USBSS_INT_LIN_EN_OVP_SWR_MG12_REG_MASK 0x04 +#define WCD_USBSS_INT_LIN_EN_INT_L_2ND_COMP_EN_REG_MASK 0x02 +#define WCD_USBSS_INT_LIN_EN_INT_R_2ND_COMP_EN_REG_MASK 0x01 + +/* WCD_USBSS_COMBINER_IREF_PROG_1 Fields: */ +#define WCD_USBSS_COMBINER_IREF_PROG_1_ACDC_COMBINER_AUD_L_IREF_MASK 0xf0 +#define WCD_USBSS_COMBINER_IREF_PROG_1_ACDC_COMBINER_AUD_R_IREF_MASK 0x0f + +/* WCD_USBSS_COMBINER_IREF_PROG_2 Fields: */ +#define WCD_USBSS_COMBINER_IREF_PROG_2_ACDC_COMBINER_GND_L_IREF_MASK 0xf0 +#define WCD_USBSS_COMBINER_IREF_PROG_2_ACDC_COMBINER_GND_R_IREF_MASK 0x0f + +/* WCD_USBSS_EXTSW_AMP_BIAS Fields: */ +#define WCD_USBSS_EXTSW_AMP_BIAS_EXTSW_AMP_BIAS_1_MASK 0xf0 +#define WCD_USBSS_EXTSW_AMP_BIAS_EXTSW_AMP_BIAS_2_MASK 0x0f + +/* WCD_USBSS_INTSW_ILIFT Fields: */ +#define WCD_USBSS_INTSW_ILIFT_INTSW_ILIFT_L_MASK 0xf0 +#define WCD_USBSS_INTSW_ILIFT_INTSW_ILIFT_R_MASK 0x0f + +/* WCD_USBSS_EXT_SW_CTRL_1 Fields: */ +#define WCD_USBSS_EXT_SW_CTRL_1_CP_SW_OVR_MASK 0x80 +#define WCD_USBSS_EXT_SW_CTRL_1_CP_SW_DNL_REG_MASK 0x40 +#define WCD_USBSS_EXT_SW_CTRL_1_CP_SW_DPR_REG_MASK 0x20 +#define WCD_USBSS_EXT_SW_CTRL_1_CP_SWL_MG12_REG_MASK 0x10 +#define WCD_USBSS_EXT_SW_CTRL_1_LDO_SW_OVR_MASK 0x08 +#define WCD_USBSS_EXT_SW_CTRL_1_LDO_SW_DNL_REG_MASK 0x04 +#define WCD_USBSS_EXT_SW_CTRL_1_LDO_SW_DPR_REG_MASK 0x02 +#define WCD_USBSS_EXT_SW_CTRL_1_LDO_SWL_MG12_REG_MASK 0x01 + +/* WCD_USBSS_EXT_SW_CTRL_2 Fields: */ +#define WCD_USBSS_EXT_SW_CTRL_2_OVP_SW_OVR_MASK 0x80 +#define WCD_USBSS_EXT_SW_CTRL_2_OVP_SW_DNL_REG_MASK 0x40 +#define WCD_USBSS_EXT_SW_CTRL_2_OVP_SW_DPR_REG_MASK 0x20 +#define WCD_USBSS_EXT_SW_CTRL_2_OVP_SWL_MG12_REG_MASK 0x10 +#define WCD_USBSS_EXT_SW_CTRL_2_VNEGDAC_LDO_BUF_IBIAS_PROG_MASK 0x0f + +/* WCD_USBSS_INT_SW_CTRL_1 Fields: */ +#define WCD_USBSS_INT_SW_CTRL_1_SW_MIC_EN_OVR_MASK 0x80 +#define WCD_USBSS_INT_SW_CTRL_1_SW_MIC_MG1_EN_REG_MASK 0x40 +#define WCD_USBSS_INT_SW_CTRL_1_SW_MIC_MG2_EN_REG_MASK 0x20 +#define WCD_USBSS_INT_SW_CTRL_1_SW_AGND_EN_OVR_MASK 0x10 +#define WCD_USBSS_INT_SW_CTRL_1_SW_AGND_MG1_EN_REG_MASK 0x08 +#define WCD_USBSS_INT_SW_CTRL_1_SW_AGND_MG2_EN_REG_MASK 0x04 +#define WCD_USBSS_INT_SW_CTRL_1_INT_L_2ND_COMP_EN_OVR_MASK 0x02 +#define WCD_USBSS_INT_SW_CTRL_1_INT_R_2ND_COMP_EN_OVR_MASK 0x01 + +/* WCD_USBSS_INT_SW_CTRL_2 Fields: */ +#define WCD_USBSS_INT_SW_CTRL_2_SW_SENSE_GSBU1_EN_REG_MASK 0x80 +#define WCD_USBSS_INT_SW_CTRL_2_SW_SENSE_GSBU2_EN_REG_MASK 0x40 +#define WCD_USBSS_INT_SW_CTRL_2_INTSW_L_RDC_PRG_MASK 0x38 +#define WCD_USBSS_INT_SW_CTRL_2_INTSW_R_RDC_PRG_MASK 0x07 + +/* WCD_USBSS_INT_SW_CTRL_3 Fields: */ +#define WCD_USBSS_INT_SW_CTRL_3_D_INTSW_2NDCOMP_PRG_L_MASK 0xe0 +#define WCD_USBSS_INT_SW_CTRL_3_D_INTSW_2NDCOMP_PRG_R_MASK 0x1c +#define WCD_USBSS_INT_SW_CTRL_3_SW_SENSE_EN_OVR_MASK 0x02 +#define WCD_USBSS_INT_SW_CTRL_3_VNEGDAC_LDO_BUF_OVR_EN_MASK 0x01 + +/* WCD_USBSS_ATEST_CTRL Fields: */ +#define WCD_USBSS_ATEST_CTRL_ATEST7_MASK 0x80 +#define WCD_USBSS_ATEST_CTRL_ATEST6_MASK 0x40 +#define WCD_USBSS_ATEST_CTRL_ATEST5_MASK 0x20 +#define WCD_USBSS_ATEST_CTRL_ATEST4_MASK 0x10 +#define WCD_USBSS_ATEST_CTRL_ATEST3_MASK 0x08 +#define WCD_USBSS_ATEST_CTRL_ATEST2_MASK 0x04 +#define WCD_USBSS_ATEST_CTRL_ATEST1_MASK 0x02 +#define WCD_USBSS_ATEST_CTRL_ATEST0_MASK 0x01 + +/* WCD_USBSS_EXT_LIN_AUD_CEQ_PRG Fields: */ +#define WCD_USBSS_EXT_LIN_AUD_CEQ_PRG_EXT_AUD_LINL_AUD_CEQ_MASK 0xf0 +#define WCD_USBSS_EXT_LIN_AUD_CEQ_PRG_EXT_AUD_LINR_AUD_CEQ_MASK 0x0f + +/* WCD_USBSS_EXT_LIN_GND_CEQ_PRG Fields: */ +#define WCD_USBSS_EXT_LIN_GND_CEQ_PRG_EXT_GND_LINL_AUD_CEQ_MASK 0xf0 +#define WCD_USBSS_EXT_LIN_GND_CEQ_PRG_EXT_GND_LINR_AUD_CEQ_MASK 0x0f + +/* WCD_USBSS_LIN_STATUS_1 Fields: */ +#define WCD_USBSS_LIN_STATUS_1_D_EXT_AUDSW_VRATIO_L_MASK 0xff + +/* WCD_USBSS_LIN_STATUS_2 Fields: */ +#define WCD_USBSS_LIN_STATUS_2_D_EXT_AUDSW_VRATIO_R_MASK 0xff + +/* WCD_USBSS_LIN_STATUS_3 Fields: */ +#define WCD_USBSS_LIN_STATUS_3_D_EXT_GNDSW_VRATIO_L_MASK 0xff + +/* WCD_USBSS_LIN_STATUS_4 Fields: */ +#define WCD_USBSS_LIN_STATUS_4_D_EXT_GNDSW_VRATIO_R_MASK 0xff + +/* WCD_USBSS_SW_LIN_CTRL Fields: */ +#define WCD_USBSS_SW_LIN_CTRL_D_INTSW_LEGACY_PULL_VNEGDAC_REG_MASK 0x80 +#define WCD_USBSS_SW_LIN_CTRL_INTSW_LEGACY_PULL_VNEGDAC_OVR_MASK 0x40 +#define WCD_USBSS_SW_LIN_CTRL_D_INTSW_PULL_GND_REG_MASK 0x20 +#define WCD_USBSS_SW_LIN_CTRL_INTSW_PULL_GND_OVR_MASK 0x10 +#define WCD_USBSS_SW_LIN_CTRL_D_RDAC_CEQ_EN_MASK 0x08 +#define WCD_USBSS_SW_LIN_CTRL_D_INTSW_LEGACY_EN_REG_MASK 0x04 +#define WCD_USBSS_SW_LIN_CTRL_D_INTSW_LEGACY_EN_OVR_MASK 0x02 +#define WCD_USBSS_SW_LIN_CTRL_LIN_TOP_ATEST_EN_MASK 0x01 + +/* WCD_USBSS_SW_LIN_CTRL_1 Fields: */ +#define WCD_USBSS_SW_LIN_CTRL_1_AC_TRIMCODE_OVR_EN_MASK 0x02 +#define WCD_USBSS_SW_LIN_CTRL_1_DC_TRIMCODE_OVR_EN_MASK 0x01 + + +/* WCD_USBSS_LDO_3P6 Fields: */ +#define WCD_USBSS_LDO_3P6_D_INT_AUDSW_DNW_DBG_MASK 0x80 +#define WCD_USBSS_LDO_3P6_D_USB_PMIC_USB_DNW_DBG_MASK 0x40 +#define WCD_USBSS_LDO_3P6_NOT_USED_MASK 0x3f + +/* WCD_USBSS_SWITCH_BANK_ATEST Fields: */ +#define WCD_USBSS_SWITCH_BANK_ATEST_ATEST_SWBANK_EN_MASK 0x80 +#define WCD_USBSS_SWITCH_BANK_ATEST_ATEST_DPRDNL_SWBANK_MASK 0x70 +#define WCD_USBSS_SWITCH_BANK_ATEST_ATEST_GSBU_SWBANK_MASK 0x0e +#define WCD_USBSS_SWITCH_BANK_ATEST_NOT_USED_MASK 0x01 + +/* WCD_USBSS_EQ_EN Fields: */ +#define WCD_USBSS_EQ_EN_D_REG_CTL_OVERRIDE_MASK 0x80 +#define WCD_USBSS_EQ_EN_D_REG_EN_EQUALIZER_MASK 0x40 +#define WCD_USBSS_EQ_EN_D_REG_EQ_REF_SEL_MASK 0x30 +#define WCD_USBSS_EQ_EN_D_REG_EQ_SEG_SEL_MASK 0x0f + +/* WCD_USBSS_EQ_MISC Fields: */ +#define WCD_USBSS_EQ_MISC_ATEST_SEL_MASK 0xc0 +#define WCD_USBSS_EQ_MISC_D_REG_EQ_BIAS_SEL_MASK 0x30 +#define WCD_USBSS_EQ_MISC_D_REG_EQ_RC_SEL_MASK 0x0c +#define WCD_USBSS_EQ_MISC_D_REG_EQ_VREF_BIAS_SEL_MASK 0x03 + +/* WCD_USBSS_STATUS_MISC Fields: */ +#define WCD_USBSS_STATUS_MISC_NOT_USED_MASK 0xff + + +/* WCD_USBSS_FSM_DELAYS1 Fields: */ +#define WCD_USBSS_FSM_DELAYS1_DELTA_T2_MASK 0xc0 +#define WCD_USBSS_FSM_DELAYS1_SPARE_BITS_5_0_MASK 0x3f + +/* WCD_USBSS_FSM_DELAYS2 Fields: */ +#define WCD_USBSS_FSM_DELAYS2_DELTA_T4_MASK 0xf0 +#define WCD_USBSS_FSM_DELAYS2_DELTA_T3_MASK 0x0f + +/* WCD_USBSS_FSM_DELAYS3 Fields: */ +#define WCD_USBSS_FSM_DELAYS3_DELTA_T5_MASK 0xf8 +#define WCD_USBSS_FSM_DELAYS3_SPARE_BITS_2_0_MASK 0x07 + +/* WCD_USBSS_FSM_DELAYS4 Fields: */ +#define WCD_USBSS_FSM_DELAYS4_DELTA_T6_MASK 0xf8 +#define WCD_USBSS_FSM_DELAYS4_SPARE_BITS_2_0_MASK 0x07 + +/* WCD_USBSS_FSM_DELAYS5 Fields: */ +#define WCD_USBSS_FSM_DELAYS5_DELTA_T8_MASK 0xf0 +#define WCD_USBSS_FSM_DELAYS5_DELTA_T7_MASK 0x0c +#define WCD_USBSS_FSM_DELAYS5_SPARE_BITS_1_0_MASK 0x03 + +/* WCD_USBSS_FSM_DELAYS6 Fields: */ +#define WCD_USBSS_FSM_DELAYS6_DELTA_T11_MASK 0xf0 +#define WCD_USBSS_FSM_DELAYS6_DELTA_T9_MASK 0x0f + +/* WCD_USBSS_FSM_DELAYS7 Fields: */ +#define WCD_USBSS_FSM_DELAYS7_DELTA_T14_MASK 0xf0 +#define WCD_USBSS_FSM_DELAYS7_DELTA_T12_MASK 0x0f + +/* WCD_USBSS_FSM_DELAYS8 Fields: */ +#define WCD_USBSS_FSM_DELAYS8_DELTA_T13_MASK 0xf8 +#define WCD_USBSS_FSM_DELAYS8_D_REG_EN_SUP_SW_OVPREF_MASK 0x04 +#define WCD_USBSS_FSM_DELAYS8_SPARE_BITS_1_0_MASK 0x03 + +/* WCD_USBSS_FSM_DEBUG_SIGNALS Fields: */ +#define WCD_USBSS_FSM_DEBUG_SIGNALS_D_EN_OVPREF_REG_MASK 0x80 +#define WCD_USBSS_FSM_DEBUG_SIGNALS_D_EN_CP_REG_MASK 0x40 +#define WCD_USBSS_FSM_DEBUG_SIGNALS_D_EN_LDO_REG_MASK 0x20 +#define WCD_USBSS_FSM_DEBUG_SIGNALS_D_USB_STANDBY_STATE_EN_DELAYED1_REG_MASK 0x10 +#define WCD_USBSS_FSM_DEBUG_SIGNALS_D_USB_STANDBY_STATE_EN_DELAYED2_REG_MASK 0x08 +#define WCD_USBSS_FSM_DEBUG_SIGNALS_D_REG_FIX_MICGND_SWAP_ENB_MASK 0x04 +#define WCD_USBSS_FSM_DEBUG_SIGNALS_D_REG_OVERRIDE_SUPPLY_SWITCH_MASK 0x02 +#define WCD_USBSS_FSM_DEBUG_SIGNALS_D_REG_FIX_REDUCEPAVNEGCURRENT_ENB_MASK 0x01 + +/* WCD_USBSS_FSM_OVERRIDE Fields: */ +#define WCD_USBSS_FSM_OVERRIDE_D_FSM_EN_OVERRIDE_MASK 0x80 +#define WCD_USBSS_FSM_OVERRIDE_D_VNEG_PULLDN_MASK_MASK 0x40 +#define WCD_USBSS_FSM_OVERRIDE_EQ_ENABLE_GATED_BY_OVP_MASK 0x20 +#define WCD_USBSS_FSM_OVERRIDE_RCO_FAST_RATE_EFUSE_OVERRIDE_MASK 0x10 +#define WCD_USBSS_FSM_OVERRIDE_OVP_THRESHOLD_EFUSE_OVERRIDE_MASK 0x08 +#define WCD_USBSS_FSM_OVERRIDE_EQ_SEG_SEL_EFUSE_OVERRIDE_MASK 0x04 +#define WCD_USBSS_FSM_OVERRIDE_CP_PFM_EFUSE_OVERRIDE_MASK 0x02 +#define WCD_USBSS_FSM_OVERRIDE_EQ_EN_EFUSE_OVERRIDE_MASK 0x01 + +/* WCD_USBSS_ENABLE_STATUS Fields: */ +#define WCD_USBSS_ENABLE_STATUS_D_EN_OVPREF_MASK 0x80 +#define WCD_USBSS_ENABLE_STATUS_D_EN_CP_MASK 0x40 +#define WCD_USBSS_ENABLE_STATUS_D_EN_LDO_MASK 0x20 +#define WCD_USBSS_ENABLE_STATUS_D_USB_STANDBY_STATE_EXTENDED1_MASK 0x10 +#define WCD_USBSS_ENABLE_STATUS_D_USB_STANDBY_STATE_EXTENDED2_MASK 0x08 +#define WCD_USBSS_ENABLE_STATUS_TIE_LOW_MASK 0x07 + +/* WCD_USBSS_FRZ_STATUS Fields: */ +#define WCD_USBSS_FRZ_STATUS_D_FRZ_N_SWITCHES_EQ_MASK 0x80 +#define WCD_USBSS_FRZ_STATUS_D_FRZ_ALL_MASK 0x40 +#define WCD_USBSS_FRZ_STATUS_D_FRZ_OVPREF_MASK 0x20 +#define WCD_USBSS_FRZ_STATUS_D_FSM_RESET_MASK 0x10 +#define WCD_USBSS_FRZ_STATUS_TIE_LOW_MASK 0x0f + + +/* WCD_USBSS_DPR_DNL_SWITCH_ENABLE_STATUS Fields: */ +#define WCD_USBSS_DPR_DNL_SWITCH_ENABLE_STATUS_D_SW_DP_DPR_ENABLE_MASK 0x80 +#define WCD_USBSS_DPR_DNL_SWITCH_ENABLE_STATUS_D_SW_DP2_DPR_ENABLE_MASK 0x40 +#define WCD_USBSS_DPR_DNL_SWITCH_ENABLE_STATUS_D_SW_R_DPR_ENABLE_MASK 0x20 +#define WCD_USBSS_DPR_DNL_SWITCH_ENABLE_STATUS_D_SW_DN_DNL_ENABLE_MASK 0x10 +#define WCD_USBSS_DPR_DNL_SWITCH_ENABLE_STATUS_D_SW_DN2_DNL_ENABLE_MASK 0x08 +#define WCD_USBSS_DPR_DNL_SWITCH_ENABLE_STATUS_D_SW_L_DNL_ENABLE_MASK 0x04 +#define WCD_USBSS_DPR_DNL_SWITCH_ENABLE_STATUS_TIE_LOW_MASK 0x03 + +/* WCD_USBSS_SBU_GSBU_SWITCH_ENABLE_STATUS Fields: */ +#define WCD_USBSS_SBU_GSBU_SWITCH_ENABLE_STATUS_D_SW_MIC_MG1_ENABLE_MASK 0x80 +#define WCD_USBSS_SBU_GSBU_SWITCH_ENABLE_STATUS_D_SW_MIC_MG2_ENABLE_MASK 0x40 +#define WCD_USBSS_SBU_GSBU_SWITCH_ENABLE_STATUS_D_SW_AGND_MG1_ENABLE_MASK 0x20 +#define WCD_USBSS_SBU_GSBU_SWITCH_ENABLE_STATUS_D_SW_AGND_MG2_ENABLE_MASK 0x10 +#define WCD_USBSS_SBU_GSBU_SWITCH_ENABLE_STATUS_D_SW_SENSE_GSBU1_ENABLE_MASK 0x08 +#define WCD_USBSS_SBU_GSBU_SWITCH_ENABLE_STATUS_D_SW_SENSE_GSBU2_ENABLE_MASK 0x04 +#define WCD_USBSS_SBU_GSBU_SWITCH_ENABLE_STATUS_TIE_LOW_MASK 0x03 + +/* WCD_USBSS_DPAUX_SWITCH_ENABLE_STATUS Fields: */ +#define WCD_USBSS_DPAUX_SWITCH_ENABLE_STATUS_D_SW_DPAUXM_MG1_ENABLE_MASK 0x80 +#define WCD_USBSS_DPAUX_SWITCH_ENABLE_STATUS_D_SW_DPAUXM_MG2_ENABLE_MASK 0x40 +#define WCD_USBSS_DPAUX_SWITCH_ENABLE_STATUS_D_SW_DPAUXP_MG1_ENABLE_MASK 0x20 +#define WCD_USBSS_DPAUX_SWITCH_ENABLE_STATUS_D_SW_DPAUXP_MG2_ENABLE_MASK 0x10 +#define WCD_USBSS_DPAUX_SWITCH_ENABLE_STATUS_TIE_LOW_MASK 0x0f + +/* WCD_USBSS_DPR_DNL_EXTFET_GATE_MUX_STATUS Fields: */ +#define WCD_USBSS_DPR_DNL_EXTFET_GATE_MUX_STATUS_D_LIN_EN_DNL_MASK 0x80 +#define WCD_USBSS_DPR_DNL_EXTFET_GATE_MUX_STATUS_D_CP_SW_EN_DNL_MASK 0x40 +#define WCD_USBSS_DPR_DNL_EXTFET_GATE_MUX_STATUS_D_OVP_SW_EN_DNL_MASK 0x20 +#define WCD_USBSS_DPR_DNL_EXTFET_GATE_MUX_STATUS_D_LDO_SW_EN_DNL_MASK 0x10 +#define WCD_USBSS_DPR_DNL_EXTFET_GATE_MUX_STATUS_D_LIN_EN_DPR_MASK 0x08 +#define WCD_USBSS_DPR_DNL_EXTFET_GATE_MUX_STATUS_D_CP_SW_EN_DPR_MASK 0x04 +#define WCD_USBSS_DPR_DNL_EXTFET_GATE_MUX_STATUS_D_OVP_SW_EN_DPR_MASK 0x02 +#define WCD_USBSS_DPR_DNL_EXTFET_GATE_MUX_STATUS_D_LDO_SW_EN_DPR_MASK 0x01 + +/* WCD_USBSS_SBU_EXTFET_GATE_MUX_OVP_STATUS Fields: */ +#define WCD_USBSS_SBU_EXTFET_GATE_MUX_OVP_STATUS_D_LIN_EN_MG12_MASK 0x80 +#define WCD_USBSS_SBU_EXTFET_GATE_MUX_OVP_STATUS_D_CP_SW_EN_MG12_MASK 0x40 +#define WCD_USBSS_SBU_EXTFET_GATE_MUX_OVP_STATUS_D_OVP_SW_EN_MG12_MASK 0x20 +#define WCD_USBSS_SBU_EXTFET_GATE_MUX_OVP_STATUS_D_LDO_SW_EN_MG12_MASK 0x10 +#define WCD_USBSS_SBU_EXTFET_GATE_MUX_OVP_STATUS_D_EQ_EN_MASK 0x08 +#define WCD_USBSS_SBU_EXTFET_GATE_MUX_OVP_STATUS_D_OVP_MG12_ENABLE_MASK 0x04 +#define WCD_USBSS_SBU_EXTFET_GATE_MUX_OVP_STATUS_D_OVP_DPR_ENABLE_MASK 0x02 +#define WCD_USBSS_SBU_EXTFET_GATE_MUX_OVP_STATUS_D_OVP_DNL_ENABLE_MASK 0x01 + +/* WCD_USBSS_CP_LIN_CNTL_STATUS Fields: */ +#define WCD_USBSS_CP_LIN_CNTL_STATUS_D_CP_ENABLE_MASK 0x80 +#define WCD_USBSS_CP_LIN_CNTL_STATUS_D_CP_PFM_ENABLE_MASK 0x40 +#define WCD_USBSS_CP_LIN_CNTL_STATUS_D_CP_CLK_DIV_MASK 0x30 +#define WCD_USBSS_CP_LIN_CNTL_STATUS_D_LIN_MODE_MASK 0x0c +#define WCD_USBSS_CP_LIN_CNTL_STATUS_D_AUDIO_EN_OVP_MASK 0x02 +#define WCD_USBSS_CP_LIN_CNTL_STATUS_TIE_LOW_MASK 0x01 + + +/* WCD_USBSS_DISP_AUXP_THRESH Fields: */ +#define WCD_USBSS_DISP_AUXP_THRESH_DISP_AUXP_OVPON_CM_MASK 0xe0 +#define WCD_USBSS_DISP_AUXP_THRESH_DISP_AUXP_OVPON_INCNEG_CM_MASK 0x1c +#define WCD_USBSS_DISP_AUXP_THRESH_SPARE_BITS_1_0_MASK 0x03 + +/* WCD_USBSS_DISP_AUXP_CTL Fields: */ +#define WCD_USBSS_DISP_AUXP_CTL_GNDSW_LK_TRK_EN_MASK 0x80 +#define WCD_USBSS_DISP_AUXP_CTL_DISP_CM_MOD_EN_MASK 0x40 +#define WCD_USBSS_DISP_AUXP_CTL_DISP_MODE_OVERRIDE_EN_MASK 0x20 +#define WCD_USBSS_DISP_AUXP_CTL_OVP_NEG_THRESH_INC_OVERRIDE_EN_MASK 0x10 +#define WCD_USBSS_DISP_AUXP_CTL_OVP_OVERRIDE_EN_MASK 0x08 +#define WCD_USBSS_DISP_AUXP_CTL_LK_CANCEL_TRK_COEFF_MASK 0x07 + +/* WCD_USBSS_DISP_AUXM_THRESH Fields: */ +#define WCD_USBSS_DISP_AUXM_THRESH_SBU1_DISP_AUXM_OVPON_CM_MASK 0xe0 +#define WCD_USBSS_DISP_AUXM_THRESH_SPARE_BITS_4_0_MASK 0x1f + +/* WCD_USBSS_DISP_AUXM_CTL Fields: */ +#define WCD_USBSS_DISP_AUXM_CTL_GNDSW_LK_TRK_EN_MASK 0x80 +#define WCD_USBSS_DISP_AUXM_CTL_DISP_CM_MOD_EN_MASK 0x40 +#define WCD_USBSS_DISP_AUXM_CTL_DISP_MODE_OVERRIDE_EN_MASK 0x20 +#define WCD_USBSS_DISP_AUXM_CTL_SPARE_BITS_4_MASK 0x10 +#define WCD_USBSS_DISP_AUXM_CTL_OVP_OVERRIDE_EN_MASK 0x08 +#define WCD_USBSS_DISP_AUXM_CTL_LK_CANCEL_TRK_COEFF_MASK 0x07 + + +/* WCD_USBSS_CTRL_0 Fields: */ +#define WCD_USBSS_CTRL_0_PWDN_CTL_MASK 0x80 +#define WCD_USBSS_CTRL_0_CAL_CTL_MASK 0x40 +#define WCD_USBSS_CTRL_0_IBIAS_ERRAMP_MASK 0x30 +#define WCD_USBSS_CTRL_0_RES_LOAD_CTL_MASK 0x0c +#define WCD_USBSS_CTRL_0_FB_GNDSW_OVERRIDE_MASK 0x02 + +/* WCD_USBSS_CTRL_1 Fields: */ +#define WCD_USBSS_CTRL_1_VOUT_PROG_MASK 0xf0 +#define WCD_USBSS_CTRL_1_VOUT_CAL_MASK 0x0f + + +/* WCD_USBSS_DC_TRIMCODE_1 Fields: */ +#define WCD_USBSS_DC_TRIMCODE_1_AUDSW_R_OFFSET_TRIM_4_2_MASK 0xe0 +#define WCD_USBSS_DC_TRIMCODE_1_AUDSW_L_OFFSET_TRIM_4_0_MASK 0x1f + +/* WCD_USBSS_DC_TRIMCODE_2 Fields: */ +#define WCD_USBSS_DC_TRIMCODE_2_SPARE_MASK 0x80 +#define WCD_USBSS_DC_TRIMCODE_2_GNDSW_L_OFFSET_TRIM_4_0_MASK 0x7c +#define WCD_USBSS_DC_TRIMCODE_2_AUDSW_R_OFFSET_TRIM_1_0_MASK 0x03 + +/* WCD_USBSS_DC_TRIMCODE_3 Fields: */ +#define WCD_USBSS_DC_TRIMCODE_3_SPARE_MASK 0x80 +#define WCD_USBSS_DC_TRIMCODE_3_AUDSW_R_GAIN_TRIM_1_0_MASK 0x60 +#define WCD_USBSS_DC_TRIMCODE_3_GNDSW_R_OFFSET_TRIM_4_0_MASK 0x1f + +/* WCD_USBSS_AC_TRIMCODE_1 Fields: */ +#define WCD_USBSS_AC_TRIMCODE_1_AUDSW_R_GAIN_TRIM_4_2_MASK 0xe0 +#define WCD_USBSS_AC_TRIMCODE_1_AUDSW_L_GAIN_TRIM_4_0_MASK 0x1f + +/* WCD_USBSS_AC_TRIMCODE_2 Fields: */ +#define WCD_USBSS_AC_TRIMCODE_2_GNDSW_R_GAIN_TRIM_3_0_MASK 0xe0 +#define WCD_USBSS_AC_TRIMCODE_2_GNDSW_L_GAIN_TRIM_3_0_MASK 0x1f + + +/* WCD_USBSS_CPLDO_CTL1 Fields: */ +#define WCD_USBSS_CPLDO_CTL1_CPLDO_EN_MASK 0x80 +#define WCD_USBSS_CPLDO_CTL1_CPLDO_TOP_EN_OVRRD_MASK 0x40 +#define WCD_USBSS_CPLDO_CTL1_BYPASS_EN_OVERRIDE_MASK 0x20 +#define WCD_USBSS_CPLDO_CTL1_LDO_TUNE_MASK 0x18 +#define WCD_USBSS_CPLDO_CTL1_LDO_IQ_INC_MASK 0x04 +#define WCD_USBSS_CPLDO_CTL1_SPARE_BITS_2_0_MASK 0x03 + +/* WCD_USBSS_CPLDO_CTL2 Fields: */ +#define WCD_USBSS_CPLDO_CTL2_SPARE_BITS_7_0_MASK 0xff + + +/* WCD_USBSS_LUT_REG0 Fields: */ +#define WCD_USBSS_LUT_REG0_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG1 Fields: */ +#define WCD_USBSS_LUT_REG1_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG2 Fields: */ +#define WCD_USBSS_LUT_REG2_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG3 Fields: */ +#define WCD_USBSS_LUT_REG3_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG4 Fields: */ +#define WCD_USBSS_LUT_REG4_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG5 Fields: */ +#define WCD_USBSS_LUT_REG5_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG6 Fields: */ +#define WCD_USBSS_LUT_REG6_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG7 Fields: */ +#define WCD_USBSS_LUT_REG7_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG8 Fields: */ +#define WCD_USBSS_LUT_REG8_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG9 Fields: */ +#define WCD_USBSS_LUT_REG9_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG10 Fields: */ +#define WCD_USBSS_LUT_REG10_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG11 Fields: */ +#define WCD_USBSS_LUT_REG11_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG12 Fields: */ +#define WCD_USBSS_LUT_REG12_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG13 Fields: */ +#define WCD_USBSS_LUT_REG13_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG14 Fields: */ +#define WCD_USBSS_LUT_REG14_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG15 Fields: */ +#define WCD_USBSS_LUT_REG15_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG16 Fields: */ +#define WCD_USBSS_LUT_REG16_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG17 Fields: */ +#define WCD_USBSS_LUT_REG17_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG18 Fields: */ +#define WCD_USBSS_LUT_REG18_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG19 Fields: */ +#define WCD_USBSS_LUT_REG19_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG20 Fields: */ +#define WCD_USBSS_LUT_REG20_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG21 Fields: */ +#define WCD_USBSS_LUT_REG21_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG22 Fields: */ +#define WCD_USBSS_LUT_REG22_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG23 Fields: */ +#define WCD_USBSS_LUT_REG23_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG24 Fields: */ +#define WCD_USBSS_LUT_REG24_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG25 Fields: */ +#define WCD_USBSS_LUT_REG25_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG26 Fields: */ +#define WCD_USBSS_LUT_REG26_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG27 Fields: */ +#define WCD_USBSS_LUT_REG27_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG28 Fields: */ +#define WCD_USBSS_LUT_REG28_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG29 Fields: */ +#define WCD_USBSS_LUT_REG29_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG30 Fields: */ +#define WCD_USBSS_LUT_REG30_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG31 Fields: */ +#define WCD_USBSS_LUT_REG31_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG32 Fields: */ +#define WCD_USBSS_LUT_REG32_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG33 Fields: */ +#define WCD_USBSS_LUT_REG33_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG34 Fields: */ +#define WCD_USBSS_LUT_REG34_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG35 Fields: */ +#define WCD_USBSS_LUT_REG35_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG36 Fields: */ +#define WCD_USBSS_LUT_REG36_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG37 Fields: */ +#define WCD_USBSS_LUT_REG37_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG38 Fields: */ +#define WCD_USBSS_LUT_REG38_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG39 Fields: */ +#define WCD_USBSS_LUT_REG39_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG40 Fields: */ +#define WCD_USBSS_LUT_REG40_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG41 Fields: */ +#define WCD_USBSS_LUT_REG41_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG42 Fields: */ +#define WCD_USBSS_LUT_REG42_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG43 Fields: */ +#define WCD_USBSS_LUT_REG43_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG44 Fields: */ +#define WCD_USBSS_LUT_REG44_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG45 Fields: */ +#define WCD_USBSS_LUT_REG45_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG46 Fields: */ +#define WCD_USBSS_LUT_REG46_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG47 Fields: */ +#define WCD_USBSS_LUT_REG47_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG48 Fields: */ +#define WCD_USBSS_LUT_REG48_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG49 Fields: */ +#define WCD_USBSS_LUT_REG49_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG50 Fields: */ +#define WCD_USBSS_LUT_REG50_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG51 Fields: */ +#define WCD_USBSS_LUT_REG51_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG52 Fields: */ +#define WCD_USBSS_LUT_REG52_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG53 Fields: */ +#define WCD_USBSS_LUT_REG53_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG54 Fields: */ +#define WCD_USBSS_LUT_REG54_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG55 Fields: */ +#define WCD_USBSS_LUT_REG55_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG56 Fields: */ +#define WCD_USBSS_LUT_REG56_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG57 Fields: */ +#define WCD_USBSS_LUT_REG57_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG58 Fields: */ +#define WCD_USBSS_LUT_REG58_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG59 Fields: */ +#define WCD_USBSS_LUT_REG59_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG60 Fields: */ +#define WCD_USBSS_LUT_REG60_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG61 Fields: */ +#define WCD_USBSS_LUT_REG61_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG62 Fields: */ +#define WCD_USBSS_LUT_REG62_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG63 Fields: */ +#define WCD_USBSS_LUT_REG63_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG64 Fields: */ +#define WCD_USBSS_LUT_REG64_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG65 Fields: */ +#define WCD_USBSS_LUT_REG65_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG66 Fields: */ +#define WCD_USBSS_LUT_REG66_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG67 Fields: */ +#define WCD_USBSS_LUT_REG67_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG68 Fields: */ +#define WCD_USBSS_LUT_REG68_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG69 Fields: */ +#define WCD_USBSS_LUT_REG69_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG70 Fields: */ +#define WCD_USBSS_LUT_REG70_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG71 Fields: */ +#define WCD_USBSS_LUT_REG71_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG72 Fields: */ +#define WCD_USBSS_LUT_REG72_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG73 Fields: */ +#define WCD_USBSS_LUT_REG73_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG74 Fields: */ +#define WCD_USBSS_LUT_REG74_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG75 Fields: */ +#define WCD_USBSS_LUT_REG75_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG76 Fields: */ +#define WCD_USBSS_LUT_REG76_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG77 Fields: */ +#define WCD_USBSS_LUT_REG77_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG78 Fields: */ +#define WCD_USBSS_LUT_REG78_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG79 Fields: */ +#define WCD_USBSS_LUT_REG79_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG80 Fields: */ +#define WCD_USBSS_LUT_REG80_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG81 Fields: */ +#define WCD_USBSS_LUT_REG81_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG82 Fields: */ +#define WCD_USBSS_LUT_REG82_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG83 Fields: */ +#define WCD_USBSS_LUT_REG83_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG84 Fields: */ +#define WCD_USBSS_LUT_REG84_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG85 Fields: */ +#define WCD_USBSS_LUT_REG85_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG86 Fields: */ +#define WCD_USBSS_LUT_REG86_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG87 Fields: */ +#define WCD_USBSS_LUT_REG87_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG88 Fields: */ +#define WCD_USBSS_LUT_REG88_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG89 Fields: */ +#define WCD_USBSS_LUT_REG89_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG90 Fields: */ +#define WCD_USBSS_LUT_REG90_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG91 Fields: */ +#define WCD_USBSS_LUT_REG91_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG92 Fields: */ +#define WCD_USBSS_LUT_REG92_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG93 Fields: */ +#define WCD_USBSS_LUT_REG93_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG94 Fields: */ +#define WCD_USBSS_LUT_REG94_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG95 Fields: */ +#define WCD_USBSS_LUT_REG95_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG96 Fields: */ +#define WCD_USBSS_LUT_REG96_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG97 Fields: */ +#define WCD_USBSS_LUT_REG97_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG98 Fields: */ +#define WCD_USBSS_LUT_REG98_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG99 Fields: */ +#define WCD_USBSS_LUT_REG99_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG100 Fields: */ +#define WCD_USBSS_LUT_REG100_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG101 Fields: */ +#define WCD_USBSS_LUT_REG101_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG102 Fields: */ +#define WCD_USBSS_LUT_REG102_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG103 Fields: */ +#define WCD_USBSS_LUT_REG103_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG104 Fields: */ +#define WCD_USBSS_LUT_REG104_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG105 Fields: */ +#define WCD_USBSS_LUT_REG105_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG106 Fields: */ +#define WCD_USBSS_LUT_REG106_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG107 Fields: */ +#define WCD_USBSS_LUT_REG107_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG108 Fields: */ +#define WCD_USBSS_LUT_REG108_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG109 Fields: */ +#define WCD_USBSS_LUT_REG109_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG110 Fields: */ +#define WCD_USBSS_LUT_REG110_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG111 Fields: */ +#define WCD_USBSS_LUT_REG111_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG112 Fields: */ +#define WCD_USBSS_LUT_REG112_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG113 Fields: */ +#define WCD_USBSS_LUT_REG113_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG114 Fields: */ +#define WCD_USBSS_LUT_REG114_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG115 Fields: */ +#define WCD_USBSS_LUT_REG115_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG116 Fields: */ +#define WCD_USBSS_LUT_REG116_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG117 Fields: */ +#define WCD_USBSS_LUT_REG117_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG118 Fields: */ +#define WCD_USBSS_LUT_REG118_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG119 Fields: */ +#define WCD_USBSS_LUT_REG119_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG120 Fields: */ +#define WCD_USBSS_LUT_REG120_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG121 Fields: */ +#define WCD_USBSS_LUT_REG121_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG122 Fields: */ +#define WCD_USBSS_LUT_REG122_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG123 Fields: */ +#define WCD_USBSS_LUT_REG123_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG124 Fields: */ +#define WCD_USBSS_LUT_REG124_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG125 Fields: */ +#define WCD_USBSS_LUT_REG125_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG126 Fields: */ +#define WCD_USBSS_LUT_REG126_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG127 Fields: */ +#define WCD_USBSS_LUT_REG127_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG128 Fields: */ +#define WCD_USBSS_LUT_REG128_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG129 Fields: */ +#define WCD_USBSS_LUT_REG129_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG130 Fields: */ +#define WCD_USBSS_LUT_REG130_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG131 Fields: */ +#define WCD_USBSS_LUT_REG131_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG132 Fields: */ +#define WCD_USBSS_LUT_REG132_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG133 Fields: */ +#define WCD_USBSS_LUT_REG133_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG134 Fields: */ +#define WCD_USBSS_LUT_REG134_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG135 Fields: */ +#define WCD_USBSS_LUT_REG135_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG136 Fields: */ +#define WCD_USBSS_LUT_REG136_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG137 Fields: */ +#define WCD_USBSS_LUT_REG137_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG138 Fields: */ +#define WCD_USBSS_LUT_REG138_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG139 Fields: */ +#define WCD_USBSS_LUT_REG139_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG140 Fields: */ +#define WCD_USBSS_LUT_REG140_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG141 Fields: */ +#define WCD_USBSS_LUT_REG141_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG142 Fields: */ +#define WCD_USBSS_LUT_REG142_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG143 Fields: */ +#define WCD_USBSS_LUT_REG143_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG144 Fields: */ +#define WCD_USBSS_LUT_REG144_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG145 Fields: */ +#define WCD_USBSS_LUT_REG145_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG146 Fields: */ +#define WCD_USBSS_LUT_REG146_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG147 Fields: */ +#define WCD_USBSS_LUT_REG147_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG148 Fields: */ +#define WCD_USBSS_LUT_REG148_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG149 Fields: */ +#define WCD_USBSS_LUT_REG149_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG150 Fields: */ +#define WCD_USBSS_LUT_REG150_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG151 Fields: */ +#define WCD_USBSS_LUT_REG151_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG152 Fields: */ +#define WCD_USBSS_LUT_REG152_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG153 Fields: */ +#define WCD_USBSS_LUT_REG153_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG154 Fields: */ +#define WCD_USBSS_LUT_REG154_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG155 Fields: */ +#define WCD_USBSS_LUT_REG155_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG156 Fields: */ +#define WCD_USBSS_LUT_REG156_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG157 Fields: */ +#define WCD_USBSS_LUT_REG157_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG158 Fields: */ +#define WCD_USBSS_LUT_REG158_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG159 Fields: */ +#define WCD_USBSS_LUT_REG159_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG160 Fields: */ +#define WCD_USBSS_LUT_REG160_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG161 Fields: */ +#define WCD_USBSS_LUT_REG161_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG162 Fields: */ +#define WCD_USBSS_LUT_REG162_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG163 Fields: */ +#define WCD_USBSS_LUT_REG163_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG164 Fields: */ +#define WCD_USBSS_LUT_REG164_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG165 Fields: */ +#define WCD_USBSS_LUT_REG165_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG166 Fields: */ +#define WCD_USBSS_LUT_REG166_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG167 Fields: */ +#define WCD_USBSS_LUT_REG167_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG168 Fields: */ +#define WCD_USBSS_LUT_REG168_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG169 Fields: */ +#define WCD_USBSS_LUT_REG169_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG170 Fields: */ +#define WCD_USBSS_LUT_REG170_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG171 Fields: */ +#define WCD_USBSS_LUT_REG171_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG172 Fields: */ +#define WCD_USBSS_LUT_REG172_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG173 Fields: */ +#define WCD_USBSS_LUT_REG173_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG174 Fields: */ +#define WCD_USBSS_LUT_REG174_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG175 Fields: */ +#define WCD_USBSS_LUT_REG175_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG176 Fields: */ +#define WCD_USBSS_LUT_REG176_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG177 Fields: */ +#define WCD_USBSS_LUT_REG177_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG178 Fields: */ +#define WCD_USBSS_LUT_REG178_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG179 Fields: */ +#define WCD_USBSS_LUT_REG179_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG180 Fields: */ +#define WCD_USBSS_LUT_REG180_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG181 Fields: */ +#define WCD_USBSS_LUT_REG181_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG182 Fields: */ +#define WCD_USBSS_LUT_REG182_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG183 Fields: */ +#define WCD_USBSS_LUT_REG183_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG184 Fields: */ +#define WCD_USBSS_LUT_REG184_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG185 Fields: */ +#define WCD_USBSS_LUT_REG185_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG186 Fields: */ +#define WCD_USBSS_LUT_REG186_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG187 Fields: */ +#define WCD_USBSS_LUT_REG187_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG188 Fields: */ +#define WCD_USBSS_LUT_REG188_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG189 Fields: */ +#define WCD_USBSS_LUT_REG189_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG190 Fields: */ +#define WCD_USBSS_LUT_REG190_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG191 Fields: */ +#define WCD_USBSS_LUT_REG191_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG192 Fields: */ +#define WCD_USBSS_LUT_REG192_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG193 Fields: */ +#define WCD_USBSS_LUT_REG193_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG194 Fields: */ +#define WCD_USBSS_LUT_REG194_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG195 Fields: */ +#define WCD_USBSS_LUT_REG195_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG196 Fields: */ +#define WCD_USBSS_LUT_REG196_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG197 Fields: */ +#define WCD_USBSS_LUT_REG197_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG198 Fields: */ +#define WCD_USBSS_LUT_REG198_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG199 Fields: */ +#define WCD_USBSS_LUT_REG199_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG200 Fields: */ +#define WCD_USBSS_LUT_REG200_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG201 Fields: */ +#define WCD_USBSS_LUT_REG201_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG202 Fields: */ +#define WCD_USBSS_LUT_REG202_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG203 Fields: */ +#define WCD_USBSS_LUT_REG203_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG204 Fields: */ +#define WCD_USBSS_LUT_REG204_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG205 Fields: */ +#define WCD_USBSS_LUT_REG205_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG206 Fields: */ +#define WCD_USBSS_LUT_REG206_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG207 Fields: */ +#define WCD_USBSS_LUT_REG207_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG208 Fields: */ +#define WCD_USBSS_LUT_REG208_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG209 Fields: */ +#define WCD_USBSS_LUT_REG209_REG_MASK 0xff + +/* WCD_USBSS_LUT_REG210 Fields: */ +#define WCD_USBSS_LUT_REG210_REG_MASK 0xff + +/* WCD_USBSS_DATA_SEL Fields: */ +#define WCD_USBSS_DATA_SEL_SEL3_MASK 0x30 +#define WCD_USBSS_DATA_SEL_SEL2_MASK 0x0c +#define WCD_USBSS_DATA_SEL_SEL1_MASK 0x02 +#define WCD_USBSS_DATA_SEL_SEL0_MASK 0x01 + +/* WCD_USBSS_OFF3 Fields: */ +#define WCD_USBSS_OFF3_REG_MASK 0xff + +/* WCD_USBSS_OFF2_LSB Fields: */ +#define WCD_USBSS_OFF2_LSB_REG_MASK 0xff + +/* WCD_USBSS_OFF2_MSB Fields: */ +#define WCD_USBSS_OFF2_MSB_REG_MASK 0xff + +/* WCD_USBSS_OFF1_LSB Fields: */ +#define WCD_USBSS_OFF1_LSB_REG_MASK 0xff + +/* WCD_USBSS_OFF1_MSB Fields: */ +#define WCD_USBSS_OFF1_MSB_REG_MASK 0xff + +/* WCD_USBSS_AUD_L Fields: */ +#define WCD_USBSS_AUD_L_STATUS_MASK 0xff + +/* WCD_USBSS_AUD_R Fields: */ +#define WCD_USBSS_AUD_R_STATUS_MASK 0xff + +/* WCD_USBSS_GND_L Fields: */ +#define WCD_USBSS_GND_L_STATUS_MASK 0xff + +/* WCD_USBSS_GND_R Fields: */ +#define WCD_USBSS_GND_R_STATUS_MASK 0xff + + +/* WCD_USBSS_USB_DIG_PAGE Fields: */ +#define WCD_USBSS_USB_DIG_PAGE_PAGE_REG_MASK 0xff + +/* WCD_USBSS_OVP_STATUS_SELF_CLEARING Fields: */ +#define WCD_USBSS_OVP_STATUS_SELF_CLEARING_OVP_DPR_MASK 0x80 +#define WCD_USBSS_OVP_STATUS_SELF_CLEARING_OVP_DNL_MASK 0x40 +#define WCD_USBSS_OVP_STATUS_SELF_CLEARING_OVP_MG1_MASK 0x20 +#define WCD_USBSS_OVP_STATUS_SELF_CLEARING_OVP_MG2_MASK 0x10 + +/* WCD_USBSS_OVP_STATUS Fields: */ +#define WCD_USBSS_OVP_STATUS_OVP_DPR_MASK 0x80 +#define WCD_USBSS_OVP_STATUS_OVP_DNL_MASK 0x40 +#define WCD_USBSS_OVP_STATUS_OVP_MG1_MASK 0x20 +#define WCD_USBSS_OVP_STATUS_OVP_MG2_MASK 0x10 + +/* WCD_USBSS_SWITCH_SETTINGS_ENABLE Fields: */ +#define WCD_USBSS_SWITCH_SETTINGS_ENABLE_DEVICE_ENABLE_MASK 0x80 +#define WCD_USBSS_SWITCH_SETTINGS_ENABLE_DP_AUXP_TO_MGX_SWITCHES_MASK 0x40 +#define WCD_USBSS_SWITCH_SETTINGS_ENABLE_DP_AUXM_TO_MGX_SWITCHES_MASK 0x20 +#define WCD_USBSS_SWITCH_SETTINGS_ENABLE_DNL_SWITCHES_MASK 0x10 +#define WCD_USBSS_SWITCH_SETTINGS_ENABLE_DPR_SWITCHES_MASK 0x08 +#define WCD_USBSS_SWITCH_SETTINGS_ENABLE_SENSE_SWITCHES_MASK 0x04 +#define WCD_USBSS_SWITCH_SETTINGS_ENABLE_MIC_SWITCHES_MASK 0x02 +#define WCD_USBSS_SWITCH_SETTINGS_ENABLE_AGND_SWITCHES_MASK 0x01 + +/* WCD_USBSS_SWITCH_SELECT0 Fields: */ +#define WCD_USBSS_SWITCH_SELECT0_DP_AUXP_SWITCHES_MASK 0x80 +#define WCD_USBSS_SWITCH_SELECT0_DP_AUXM_SWITCHES_MASK 0x40 +#define WCD_USBSS_SWITCH_SELECT0_DNL_SWITCHES_MASK 0x30 +#define WCD_USBSS_SWITCH_SELECT0_DPR_SWITCHES_MASK 0x0c +#define WCD_USBSS_SWITCH_SELECT0_SENSE_SWITCHES_MASK 0x02 +#define WCD_USBSS_SWITCH_SELECT0_MIC_SWITCHES_MASK 0x01 + +/* WCD_USBSS_SWITCH_SELECT1 Fields: */ +#define WCD_USBSS_SWITCH_SELECT1_AGND_SWITCHES_MASK 0x01 + +/* WCD_USBSS_SWITCH_STATUS0 Fields: */ +#define WCD_USBSS_SWITCH_STATUS0_SENSE_GSBU2_STATUS_MASK 0x80 +#define WCD_USBSS_SWITCH_STATUS0_SENSE_GSBU1_STATUS_MASK 0x40 +#define WCD_USBSS_SWITCH_STATUS0_L_DNL_STATUS_MASK 0x20 +#define WCD_USBSS_SWITCH_STATUS0_DN2_DNL_STATUS_MASK 0x10 +#define WCD_USBSS_SWITCH_STATUS0_DN_DNL_STATUS_MASK 0x08 +#define WCD_USBSS_SWITCH_STATUS0_R_DPR_STATUS_MASK 0x04 +#define WCD_USBSS_SWITCH_STATUS0_DP2_DPR_STATUS_MASK 0x02 +#define WCD_USBSS_SWITCH_STATUS0_DP_DPR_STATUS_MASK 0x01 + +/* WCD_USBSS_SWITCH_STATUS1 Fields: */ +#define WCD_USBSS_SWITCH_STATUS1_DPAUXP_MG2_STATUS_MASK 0x80 +#define WCD_USBSS_SWITCH_STATUS1_DPAUXM_MG2_STATUS_MASK 0x40 +#define WCD_USBSS_SWITCH_STATUS1_AGND_MG2_STATUS_MASK 0x20 +#define WCD_USBSS_SWITCH_STATUS1_MIC_MG2_STATUS_MASK 0x10 +#define WCD_USBSS_SWITCH_STATUS1_DPAUXP_MG1_STATUS_MASK 0x08 +#define WCD_USBSS_SWITCH_STATUS1_DPAUXM_MG1_STATUS_MASK 0x04 +#define WCD_USBSS_SWITCH_STATUS1_AGND_MG1_STATUS_MASK 0x02 +#define WCD_USBSS_SWITCH_STATUS1_MIC_MG1_STATUS_MASK 0x01 + +/* WCD_USBSS_AUD_LEFT_SW_SLOW Fields: */ +#define WCD_USBSS_AUD_LEFT_SW_SLOW_SWITCH_TURN_ON_RISE_TIME_MASK 0xff + +/* WCD_USBSS_AUD_RIGHT_SW_SLOW Fields: */ +#define WCD_USBSS_AUD_RIGHT_SW_SLOW_SWITCH_TURN_ON_RISE_TIME_MASK 0xff + +/* WCD_USBSS_AUD_MIC_SW_SLOW Fields: */ +#define WCD_USBSS_AUD_MIC_SW_SLOW_SWITCH_TURN_ON_RISE_TIME_MASK 0xff + +/* WCD_USBSS_AUD_SENSE_SW_SLOW Fields: */ +#define WCD_USBSS_AUD_SENSE_SW_SLOW_SWITCH_TURN_ON_RISE_TIME_MASK 0xff + +/* WCD_USBSS_AUD_GND_SW_SLOW Fields: */ +#define WCD_USBSS_AUD_GND_SW_SLOW_SWITCH_TURN_ON_RISE_TIME_MASK 0xff + +/* WCD_USBSS_DELAY_R_SW Fields: */ +#define WCD_USBSS_DELAY_R_SW_DELAY_TIME_MASK 0xff + +/* WCD_USBSS_DELAY_MIC_SW Fields: */ +#define WCD_USBSS_DELAY_MIC_SW_DELAY_TIME_MASK 0xff + +/* WCD_USBSS_DELAY_SENSE_SW Fields: */ +#define WCD_USBSS_DELAY_SENSE_SW_DELAY_TIME_MASK 0xff + +/* WCD_USBSS_DELAY_GND_SW Fields: */ +#define WCD_USBSS_DELAY_GND_SW_DELAY_TIME_MASK 0xff + +/* WCD_USBSS_DELAY_L_SW Fields: */ +#define WCD_USBSS_DELAY_L_SW_DELAY_TIME_MASK 0xff + +/* WCD_USBSS_EXT_FET_ENABLE_DELAY Fields: */ +#define WCD_USBSS_EXT_FET_ENABLE_DELAY_DELAY_TIME_MASK 0xff + +/* WCD_USBSS_FUNCTION_ENABLE Fields: */ +#define WCD_USBSS_FUNCTION_ENABLE_SEL_CSR_SLEEP_BG_PROG_MASK 0x80 +#define WCD_USBSS_FUNCTION_ENABLE_PER_PIN_OVP_ENABLE_MASK 0x40 +#define WCD_USBSS_FUNCTION_ENABLE_SW_OVP_ENABLE_MASK 0x20 +#define WCD_USBSS_FUNCTION_ENABLE_SW_CONNECTION_DISABLE_MASK 0x10 +#define WCD_USBSS_FUNCTION_ENABLE_SLOW_TURN_ON_ENABLE_MASK 0x08 +#define WCD_USBSS_FUNCTION_ENABLE_RDAC_CAL_CODE_SELECT_MASK 0x04 +#define WCD_USBSS_FUNCTION_ENABLE_SWITCH_SOURCE_SELECT_MASK 0x03 + +/* WCD_USBSS_USB_RST_CTL Fields: */ +#define WCD_USBSS_USB_RST_CTL_USB_ANA_SW_RST_N_MASK 0x02 +#define WCD_USBSS_USB_RST_CTL_USB_DIG_SW_RST_N_MASK 0x01 + +/* WCD_USBSS_EQUALIZER1 Fields: */ +#define WCD_USBSS_EQUALIZER1_EQ_EN_MASK 0x80 +#define WCD_USBSS_EQUALIZER1_BW_SETTINGS_MASK 0x78 + +/* WCD_USBSS_SPARE_0 Fields: */ +#define WCD_USBSS_SPARE_0_SPARE_BITS_MASK 0xff + +/* WCD_USBSS_DIG_FUNCTIONS_STATUS Fields: */ +#define WCD_USBSS_DIG_FUNCTIONS_STATUS_EQ_ENABLE_STATUS_MASK 0x40 +#define WCD_USBSS_DIG_FUNCTIONS_STATUS_OVP_DNL_ENABLE_STATUS_MASK 0x20 +#define WCD_USBSS_DIG_FUNCTIONS_STATUS_OVP_DPR_ENABLE_STATUS_MASK 0x10 +#define WCD_USBSS_DIG_FUNCTIONS_STATUS_OVP_MG12_ENABLE_STATUS_MASK 0x08 +#define WCD_USBSS_DIG_FUNCTIONS_STATUS_EXTFET_DNL_ENABLE_STATUS_MASK 0x04 +#define WCD_USBSS_DIG_FUNCTIONS_STATUS_EXTFET_DPR_ENABLE_STATUS_MASK 0x02 +#define WCD_USBSS_DIG_FUNCTIONS_STATUS_EXTFET_MG12_ENABLE_STATUS_MASK 0x01 + +/* WCD_USBSS_CLK_SOURCE Fields: */ +#define WCD_USBSS_CLK_SOURCE_CP_CLK_SEL_MASK 0xc0 +#define WCD_USBSS_CLK_SOURCE_FSM_CLK_SEL_MASK 0x20 + +/* WCD_USBSS_USB_SS_CNTL Fields: */ +#define WCD_USBSS_USB_SS_CNTL_STANDBY_STATE_MASK 0x10 +#define WCD_USBSS_USB_SS_CNTL_RCO_EN_MASK 0x08 +#define WCD_USBSS_USB_SS_CNTL_USB_SS_MODE_MASK 0x07 + +/* WCD_USBSS_SPARE_1 Fields: */ +#define WCD_USBSS_SPARE_1_SPARE_BITS_MASK 0xff + +/* WCD_USBSS_ANA_FUNCTIONS_STATUS Fields: */ +#define WCD_USBSS_ANA_FUNCTIONS_STATUS_CP_READY_MASK 0x80 + +/* WCD_USBSS_FSM_STATUS Fields: */ +#define WCD_USBSS_FSM_STATUS_LINEARIZER_FSM_DONE_MASK 0x02 +#define WCD_USBSS_FSM_STATUS_SWITCH_FSM_DONE_MASK 0x01 + +/* WCD_USBSS_SPARE_14 Fields: */ +#define WCD_USBSS_SPARE_14_SPARE_BITS_MASK 0xff + +/* WCD_USBSS_SAFE_STATE_PD_DPAUX Fields: */ +#define WCD_USBSS_SAFE_STATE_PD_DPAUX_DP_SBU1_SAFE_STATE_PD_MASK 0x0c +#define WCD_USBSS_SAFE_STATE_PD_DPAUX_DP_SBU2_SAFE_STATE_PD_MASK 0x03 + +/* WCD_USBSS_AUDIO_FSM_START Fields: */ +#define WCD_USBSS_AUDIO_FSM_START_AUDIO_FSM_AUDIO_TRIG_MASK 0x01 + +/* WCD_USBSS_FSM_RESET Fields: */ +#define WCD_USBSS_FSM_RESET_AUDIO_FSM_LIN_RESET_MASK 0x02 +#define WCD_USBSS_FSM_RESET_AUDIO_FSM_SWITCH_RESET_MASK 0x01 + +/* WCD_USBSS_CHIP_ID0 Fields: */ +#define WCD_USBSS_CHIP_ID0_BYTE_0_MASK 0xff + +/* WCD_USBSS_CHIP_ID1 Fields: */ +#define WCD_USBSS_CHIP_ID1_BYTE_1_MASK 0xff + +/* WCD_USBSS_CHIP_ID2 Fields: */ +#define WCD_USBSS_CHIP_ID2_BYTE_2_MASK 0xff + +/* WCD_USBSS_CHIP_ID3 Fields: */ +#define WCD_USBSS_CHIP_ID3_BYTE_3_MASK 0xff + +/* WCD_USBSS_LINEARIZER_CFG Fields: */ +#define WCD_USBSS_LINEARIZER_CFG_COEF_CFG_SEL_MASK 0x01 + +/* WCD_USBSS_RATIO_SPKR_REXT_L_LSB Fields: */ +#define WCD_USBSS_RATIO_SPKR_REXT_L_LSB_RATIO_L_LSB_MASK 0xff + +/* WCD_USBSS_RATIO_SPKR_REXT_L_MSB Fields: */ +#define WCD_USBSS_RATIO_SPKR_REXT_L_MSB_RATIO_L_MSB_MASK 0x7f + +/* WCD_USBSS_RATIO_SPKR_REXT_R_LSB Fields: */ +#define WCD_USBSS_RATIO_SPKR_REXT_R_LSB_RATIO_R_LSB_MASK 0xff + +/* WCD_USBSS_RATIO_SPKR_REXT_R_MSB Fields: */ +#define WCD_USBSS_RATIO_SPKR_REXT_R_MSB_RATIO_R_MSB_MASK 0x7f + +/* WCD_USBSS_SW_TAP_AUD_L_LSB Fields: */ +#define WCD_USBSS_SW_TAP_AUD_L_LSB_TCAL1_SW_LEFT_LSB_MASK 0xff + +/* WCD_USBSS_SW_TAP_AUD_L_MSB Fields: */ +#define WCD_USBSS_SW_TAP_AUD_L_MSB_TCAL1_SW_LEFT_MSB_MASK 0x03 + +/* WCD_USBSS_SW_TAP_AUD_R_LSB Fields: */ +#define WCD_USBSS_SW_TAP_AUD_R_LSB_TCAL2_SW_RIGHT_LSB_MASK 0xff + +/* WCD_USBSS_SW_TAP_AUD_R_MSB Fields: */ +#define WCD_USBSS_SW_TAP_AUD_R_MSB_TCAL2_SW_RIGHT_MSB_MASK 0x03 + +/* WCD_USBSS_SW_TAP_GND_L_LSB Fields: */ +#define WCD_USBSS_SW_TAP_GND_L_LSB_TCAL3_SW_GND1_LSB_MASK 0xff + +/* WCD_USBSS_SW_TAP_GND_L_MSB Fields: */ +#define WCD_USBSS_SW_TAP_GND_L_MSB_TCAL3_SW_GND1_MSB_MASK 0x03 + +/* WCD_USBSS_SW_TAP_GND_R_LSB Fields: */ +#define WCD_USBSS_SW_TAP_GND_R_LSB_TCAL4_SW_GND2_LSB_MASK 0xff + +/* WCD_USBSS_SW_TAP_GND_R_MSB Fields: */ +#define WCD_USBSS_SW_TAP_GND_R_MSB_TCAL4_SW_GND2_MSB_MASK 0x03 + +/* WCD_USBSS_HW_TAP_AUD_L_LSB Fields: */ +#define WCD_USBSS_HW_TAP_AUD_L_LSB_TCAL1_HW_LEFT_LSB_MASK 0xff + +/* WCD_USBSS_HW_TAP_AUD_L_MSB Fields: */ +#define WCD_USBSS_HW_TAP_AUD_L_MSB_TCAL1_HW_LEFT_MSB_MASK 0x0f + +/* WCD_USBSS_HW_TAP_AUD_R_LSB Fields: */ +#define WCD_USBSS_HW_TAP_AUD_R_LSB_TCAL2_HW_RIGHT_LSB_MASK 0xff + +/* WCD_USBSS_HW_TAP_AUD_R_MSB Fields: */ +#define WCD_USBSS_HW_TAP_AUD_R_MSB_TCAL2_HW_RIGHT_MSB_MASK 0x0f + +/* WCD_USBSS_HW_TAP_GND_L_LSB Fields: */ +#define WCD_USBSS_HW_TAP_GND_L_LSB_TCAL3_HW_GND1_LSB_MASK 0xff + +/* WCD_USBSS_HW_TAP_GND_L_MSB Fields: */ +#define WCD_USBSS_HW_TAP_GND_L_MSB_TCAL3_HW_GND1_MSB_MASK 0x0f + +/* WCD_USBSS_HW_TAP_GND_R_LSB Fields: */ +#define WCD_USBSS_HW_TAP_GND_R_LSB_TCAL4_HW_GND2_LSB_MASK 0xff + +/* WCD_USBSS_HW_TAP_GND_R_MSB Fields: */ +#define WCD_USBSS_HW_TAP_GND_R_MSB_TCAL4_HW_GND2_MSB_MASK 0x0f + +/* WCD_USBSS_AUD_COEF_L_K0_0 Fields: */ +#define WCD_USBSS_AUD_COEF_L_K0_0_K0_0_MASK 0xff + +/* WCD_USBSS_AUD_COEF_L_K0_1 Fields: */ +#define WCD_USBSS_AUD_COEF_L_K0_1_K0_1_MASK 0xff + +/* WCD_USBSS_AUD_COEF_L_K0_2 Fields: */ +#define WCD_USBSS_AUD_COEF_L_K0_2_K0_2_MASK 0x3f + +/* WCD_USBSS_AUD_COEF_L_K1_0 Fields: */ +#define WCD_USBSS_AUD_COEF_L_K1_0_K1_0_MASK 0xff + +/* WCD_USBSS_AUD_COEF_L_K1_1 Fields: */ +#define WCD_USBSS_AUD_COEF_L_K1_1_K1_1_MASK 0xff + +/* WCD_USBSS_AUD_COEF_L_K2_0 Fields: */ +#define WCD_USBSS_AUD_COEF_L_K2_0_K2_0_MASK 0xff + +/* WCD_USBSS_AUD_COEF_L_K2_1 Fields: */ +#define WCD_USBSS_AUD_COEF_L_K2_1_K2_1_MASK 0xff + +/* WCD_USBSS_AUD_COEF_L_K3_0 Fields: */ +#define WCD_USBSS_AUD_COEF_L_K3_0_K3_0_MASK 0xff + +/* WCD_USBSS_AUD_COEF_L_K3_1 Fields: */ +#define WCD_USBSS_AUD_COEF_L_K3_1_K3_1_MASK 0xff + +/* WCD_USBSS_AUD_COEF_L_K4_0 Fields: */ +#define WCD_USBSS_AUD_COEF_L_K4_0_K4_0_MASK 0xff + +/* WCD_USBSS_AUD_COEF_L_K4_1 Fields: */ +#define WCD_USBSS_AUD_COEF_L_K4_1_K4_1_MASK 0xff + +/* WCD_USBSS_AUD_COEF_L_K5_0 Fields: */ +#define WCD_USBSS_AUD_COEF_L_K5_0_K5_0_MASK 0xff + +/* WCD_USBSS_AUD_COEF_L_K5_1 Fields: */ +#define WCD_USBSS_AUD_COEF_L_K5_1_K5_1_MASK 0xff + +/* WCD_USBSS_AUD_COEF_R_K0_0 Fields: */ +#define WCD_USBSS_AUD_COEF_R_K0_0_K0_0_MASK 0xff + +/* WCD_USBSS_AUD_COEF_R_K0_1 Fields: */ +#define WCD_USBSS_AUD_COEF_R_K0_1_K0_1_MASK 0xff + +/* WCD_USBSS_AUD_COEF_R_K0_2 Fields: */ +#define WCD_USBSS_AUD_COEF_R_K0_2_K0_2_MASK 0x3f + +/* WCD_USBSS_AUD_COEF_R_K1_0 Fields: */ +#define WCD_USBSS_AUD_COEF_R_K1_0_K1_0_MASK 0xff + +/* WCD_USBSS_AUD_COEF_R_K1_1 Fields: */ +#define WCD_USBSS_AUD_COEF_R_K1_1_K1_1_MASK 0xff + +/* WCD_USBSS_AUD_COEF_R_K2_0 Fields: */ +#define WCD_USBSS_AUD_COEF_R_K2_0_K2_0_MASK 0xff + +/* WCD_USBSS_AUD_COEF_R_K2_1 Fields: */ +#define WCD_USBSS_AUD_COEF_R_K2_1_K2_1_MASK 0xff + +/* WCD_USBSS_AUD_COEF_R_K3_0 Fields: */ +#define WCD_USBSS_AUD_COEF_R_K3_0_K3_0_MASK 0xff + +/* WCD_USBSS_AUD_COEF_R_K3_1 Fields: */ +#define WCD_USBSS_AUD_COEF_R_K3_1_K3_1_MASK 0xff + +/* WCD_USBSS_AUD_COEF_R_K4_0 Fields: */ +#define WCD_USBSS_AUD_COEF_R_K4_0_K4_0_MASK 0xff + +/* WCD_USBSS_AUD_COEF_R_K4_1 Fields: */ +#define WCD_USBSS_AUD_COEF_R_K4_1_K4_1_MASK 0xff + +/* WCD_USBSS_AUD_COEF_R_K5_0 Fields: */ +#define WCD_USBSS_AUD_COEF_R_K5_0_K5_0_MASK 0xff + +/* WCD_USBSS_AUD_COEF_R_K5_1 Fields: */ +#define WCD_USBSS_AUD_COEF_R_K5_1_K5_1_MASK 0xff + +/* WCD_USBSS_GND_COEF_L_K0_0 Fields: */ +#define WCD_USBSS_GND_COEF_L_K0_0_K0_0_MASK 0xff + +/* WCD_USBSS_GND_COEF_L_K0_1 Fields: */ +#define WCD_USBSS_GND_COEF_L_K0_1_K0_1_MASK 0xff + +/* WCD_USBSS_GND_COEF_L_K0_2 Fields: */ +#define WCD_USBSS_GND_COEF_L_K0_2_K0_2_MASK 0x3f + +/* WCD_USBSS_GND_COEF_L_K1_0 Fields: */ +#define WCD_USBSS_GND_COEF_L_K1_0_K1_0_MASK 0xff + +/* WCD_USBSS_GND_COEF_L_K1_1 Fields: */ +#define WCD_USBSS_GND_COEF_L_K1_1_K1_1_MASK 0xff + +/* WCD_USBSS_GND_COEF_L_K2_0 Fields: */ +#define WCD_USBSS_GND_COEF_L_K2_0_K2_0_MASK 0xff + +/* WCD_USBSS_GND_COEF_L_K2_1 Fields: */ +#define WCD_USBSS_GND_COEF_L_K2_1_K2_1_MASK 0xff + +/* WCD_USBSS_GND_COEF_L_K3_0 Fields: */ +#define WCD_USBSS_GND_COEF_L_K3_0_K3_0_MASK 0xff + +/* WCD_USBSS_GND_COEF_L_K3_1 Fields: */ +#define WCD_USBSS_GND_COEF_L_K3_1_K3_1_MASK 0xff + +/* WCD_USBSS_GND_COEF_L_K4_0 Fields: */ +#define WCD_USBSS_GND_COEF_L_K4_0_K4_0_MASK 0xff + +/* WCD_USBSS_GND_COEF_L_K4_1 Fields: */ +#define WCD_USBSS_GND_COEF_L_K4_1_K4_1_MASK 0xff + +/* WCD_USBSS_GND_COEF_L_K5_0 Fields: */ +#define WCD_USBSS_GND_COEF_L_K5_0_K5_0_MASK 0xff + +/* WCD_USBSS_GND_COEF_L_K5_1 Fields: */ +#define WCD_USBSS_GND_COEF_L_K5_1_K5_1_MASK 0xff + +/* WCD_USBSS_GND_COEF_R_K0_0 Fields: */ +#define WCD_USBSS_GND_COEF_R_K0_0_K0_0_MASK 0xff + +/* WCD_USBSS_GND_COEF_R_K0_1 Fields: */ +#define WCD_USBSS_GND_COEF_R_K0_1_K0_1_MASK 0xff + +/* WCD_USBSS_GND_COEF_R_K0_2 Fields: */ +#define WCD_USBSS_GND_COEF_R_K0_2_K0_2_MASK 0x3f + +/* WCD_USBSS_GND_COEF_R_K1_0 Fields: */ +#define WCD_USBSS_GND_COEF_R_K1_0_K1_0_MASK 0xff + +/* WCD_USBSS_GND_COEF_R_K1_1 Fields: */ +#define WCD_USBSS_GND_COEF_R_K1_1_K1_1_MASK 0xff + +/* WCD_USBSS_GND_COEF_R_K2_0 Fields: */ +#define WCD_USBSS_GND_COEF_R_K2_0_K2_0_MASK 0xff + +/* WCD_USBSS_GND_COEF_R_K2_1 Fields: */ +#define WCD_USBSS_GND_COEF_R_K2_1_K2_1_MASK 0xff + +/* WCD_USBSS_GND_COEF_R_K3_0 Fields: */ +#define WCD_USBSS_GND_COEF_R_K3_0_K3_0_MASK 0xff + +/* WCD_USBSS_GND_COEF_R_K3_1 Fields: */ +#define WCD_USBSS_GND_COEF_R_K3_1_K3_1_MASK 0xff + +/* WCD_USBSS_GND_COEF_R_K4_0 Fields: */ +#define WCD_USBSS_GND_COEF_R_K4_0_K4_0_MASK 0xff + +/* WCD_USBSS_GND_COEF_R_K4_1 Fields: */ +#define WCD_USBSS_GND_COEF_R_K4_1_K4_1_MASK 0xff + +/* WCD_USBSS_GND_COEF_R_K5_0 Fields: */ +#define WCD_USBSS_GND_COEF_R_K5_0_K5_0_MASK 0xff + +/* WCD_USBSS_GND_COEF_R_K5_1 Fields: */ +#define WCD_USBSS_GND_COEF_R_K5_1_K5_1_MASK 0xff + +/* WCD_USBSS_AUD_L_SLOPE_SCALE_LSB Fields: */ +#define WCD_USBSS_AUD_L_SLOPE_SCALE_LSB_SLOPE_LSB_MASK 0xff + +/* WCD_USBSS_AUD_L_SLOPE_SCALE_MSB Fields: */ +#define WCD_USBSS_AUD_L_SLOPE_SCALE_MSB_SLOPE_MSB_MASK 0x0f + +/* WCD_USBSS_AUD_R_SLOPE_SCALE_LSB Fields: */ +#define WCD_USBSS_AUD_R_SLOPE_SCALE_LSB_SLOPE_LSB_MASK 0xff + +/* WCD_USBSS_AUD_R_SLOPE_SCALE_MSB Fields: */ +#define WCD_USBSS_AUD_R_SLOPE_SCALE_MSB_SLOPE_MSB_MASK 0x0f + +/* WCD_USBSS_GND_L_SLOPE_SCALE_LSB Fields: */ +#define WCD_USBSS_GND_L_SLOPE_SCALE_LSB_SLOPE_LSB_MASK 0xff + +/* WCD_USBSS_GND_L_SLOPE_SCALE_MSB Fields: */ +#define WCD_USBSS_GND_L_SLOPE_SCALE_MSB_SLOPE_MSB_MASK 0x0f + +/* WCD_USBSS_GND_R_SLOPE_SCALE_LSB Fields: */ +#define WCD_USBSS_GND_R_SLOPE_SCALE_LSB_SLOPE_LSB_MASK 0xff + +/* WCD_USBSS_GND_R_SLOPE_SCALE_MSB Fields: */ +#define WCD_USBSS_GND_R_SLOPE_SCALE_MSB_SLOPE_MSB_MASK 0x0f + +/* WCD_USBSS_AUD_L_FIRST_TAP Fields: */ +#define WCD_USBSS_AUD_L_FIRST_TAP_FIRST_TAP_MASK 0xff + +/* WCD_USBSS_AUD_R_FIRST_TAP Fields: */ +#define WCD_USBSS_AUD_R_FIRST_TAP_FIRST_TAP_MASK 0xff + +/* WCD_USBSS_GND_L_FIRST_TAP Fields: */ +#define WCD_USBSS_GND_L_FIRST_TAP_FIRST_TAP_MASK 0xff + +/* WCD_USBSS_GND_R_FIRST_TAP Fields: */ +#define WCD_USBSS_GND_R_FIRST_TAP_FIRST_TAP_MASK 0xff + +/* WCD_USBSS_FEATURE_SELECTION Fields: */ +#define WCD_USBSS_FEATURE_SELECTION_FEATURE_SEL_MASK 0xf0 + +/* WCD_USBSS_EFUSE_REG_0 Fields: */ +#define WCD_USBSS_EFUSE_REG_0_EFUSE_MUX_SEL_MASK 0x20 +#define WCD_USBSS_EFUSE_REG_0_RCO_RATE_MASK 0x10 +#define WCD_USBSS_EFUSE_REG_0_LDOL_TRIM_MASK 0x0f + +/* WCD_USBSS_EFUSE_REG_1 Fields: */ +#define WCD_USBSS_EFUSE_REG_1_OVP_REFERENCE_TRIM_MASK 0xf0 +#define WCD_USBSS_EFUSE_REG_1_CP_OUTPUT_TRIM_MASK 0x0f + +/* WCD_USBSS_EFUSE_REG_2 Fields: */ +#define WCD_USBSS_EFUSE_REG_2_EQ_ENABLE_MASK 0x40 + +/* WCD_USBSS_EFUSE_REG_3 Fields: */ +#define WCD_USBSS_EFUSE_REG_3_DPAUXP_MG1_MASK 0x80 +#define WCD_USBSS_EFUSE_REG_3_DPAUXP_MG2_MASK 0x40 +#define WCD_USBSS_EFUSE_REG_3_DPAUXM_MG1_MASK 0x20 +#define WCD_USBSS_EFUSE_REG_3_DPAUXM_MG2_MASK 0x10 +#define WCD_USBSS_EFUSE_REG_3_DNL_L_MASK 0x08 +#define WCD_USBSS_EFUSE_REG_3_DNL_DN_MASK 0x04 +#define WCD_USBSS_EFUSE_REG_3_DNL_DN2_MASK 0x02 +#define WCD_USBSS_EFUSE_REG_3_DPR_R_MASK 0x01 + +/* WCD_USBSS_EFUSE_REG_4 Fields: */ +#define WCD_USBSS_EFUSE_REG_4_DPR_DP_MASK 0x80 +#define WCD_USBSS_EFUSE_REG_4_DPR_DP2_MASK 0x40 +#define WCD_USBSS_EFUSE_REG_4_SENSE_GSBU1_MASK 0x20 +#define WCD_USBSS_EFUSE_REG_4_SENSE_GSBU2_MASK 0x10 +#define WCD_USBSS_EFUSE_REG_4_MIC_MG1_MASK 0x08 +#define WCD_USBSS_EFUSE_REG_4_MIC_MG2_MASK 0x04 +#define WCD_USBSS_EFUSE_REG_4_AGND_MG1_MASK 0x02 +#define WCD_USBSS_EFUSE_REG_4_AGND_MG2_MASK 0x01 + +/* WCD_USBSS_EFUSE_REG_5 Fields: */ +#define WCD_USBSS_EFUSE_REG_5_OVP_THRESHOLD_MASK 0xc0 +#define WCD_USBSS_EFUSE_REG_5_EQ_SEG_SEL_MASK 0x30 +#define WCD_USBSS_EFUSE_REG_5_EQ_ENABLE_MASK 0x08 +#define WCD_USBSS_EFUSE_REG_5_CP_PFM_EN_MASK 0x04 +#define WCD_USBSS_EFUSE_REG_5_SPARE_BITS_MASK 0x03 + +/* WCD_USBSS_EFUSE_REG_6 Fields: */ +#define WCD_USBSS_EFUSE_REG_6_SPARE_BITS_MASK 0xff + +/* WCD_USBSS_EFUSE_REG_7 Fields: */ +#define WCD_USBSS_EFUSE_REG_7_SPARE_BITS_MASK 0xf8 +#define WCD_USBSS_EFUSE_REG_7_LDOL_TRIM_MASK 0x07 + +/* WCD_USBSS_EFUSE_REG_8 Fields: */ +#define WCD_USBSS_EFUSE_REG_8_GNDSW_L_GAIN_TRIM_MASK 0xf0 +#define WCD_USBSS_EFUSE_REG_8_GNDSW_R_GAIN_TRIM_MASK 0x0f + +/* WCD_USBSS_EFUSE_REG_9 Fields: */ +#define WCD_USBSS_EFUSE_REG_9_AUDSW_L_GAIN_TRIM_MASK 0xff + +/* WCD_USBSS_EFUSE_REG_10 Fields: */ +#define WCD_USBSS_EFUSE_REG_10_AUDSW_R_GAIN_TRIM_MASK 0xff + +/* WCD_USBSS_EFUSE_REG_11 Fields: */ +#define WCD_USBSS_EFUSE_REG_11_SPARE_BITS_MASK 0xe0 +#define WCD_USBSS_EFUSE_REG_11_GNDSW_L_OFFSET_TRIM_MASK 0x1f + +/* WCD_USBSS_EFUSE_REG_12 Fields: */ +#define WCD_USBSS_EFUSE_REG_12_SPARE_BITS_MASK 0xe0 +#define WCD_USBSS_EFUSE_REG_12_GNDSW_R_OFFSET_TRIM_MASK 0x1f + +/* WCD_USBSS_EFUSE_REG_13 Fields: */ +#define WCD_USBSS_EFUSE_REG_13_SPARE_BITS_MASK 0xe0 +#define WCD_USBSS_EFUSE_REG_13_AUDSW_L_OFFSET_TRIM_MASK 0x1f + +/* WCD_USBSS_EFUSE_REG_14 Fields: */ +#define WCD_USBSS_EFUSE_REG_14_SPARE_BITS_MASK 0xe0 +#define WCD_USBSS_EFUSE_REG_14_AUDSW_R_OFFSET_TRIM_MASK 0x1f + +/* WCD_USBSS_EFUSE_REG_15 Fields: */ +#define WCD_USBSS_EFUSE_REG_15_SPARE_BITS_MASK 0xff + +/* WCD_USBSS_EFUSE_PRG_CTL Fields: */ +#define WCD_USBSS_EFUSE_PRG_CTL_PRG_ADDR_MASK 0xff + + +#endif /* WCD_USBSS_REG_MASKS_H */ diff --git a/drivers/soc/qcom/wcd-usbss-reg-shifts.h b/drivers/soc/qcom/wcd-usbss-reg-shifts.h new file mode 100644 index 000000000000..d6dd39478a9a --- /dev/null +++ b/drivers/soc/qcom/wcd-usbss-reg-shifts.h @@ -0,0 +1,1792 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef WCD_USBSS_REG_SHIFTS_H +#define WCD_USBSS_REG_SHIFTS_H +#include +#include +#include "wcd-usbss-registers.h" + +/* Use in conjunction with wcd_usbss-reg-masks.c for field values. */ +/* field_value = (register_value & field_mask) >> field_shift */ + +#define FIELD_SHIFT(register_name, field_name) \ +WCD_USBSS_##register_name##_##field_name##_SHIFT + +/* WCD_USBSS_PAGE0_PAGE Fields: */ +#define WCD_USBSS_PAGE0_PAGE_PAGE_REG_SHIFT 0x00 + + +/* WCD_USBSS_PMP_EN Fields: */ +#define WCD_USBSS_PMP_EN_SPARE_BIT_7_SHIFT 0x07 +#define WCD_USBSS_PMP_EN_PMP_OUT_APD_SHIFT 0x06 +#define WCD_USBSS_PMP_EN_IBIAS_HALF_SHIFT 0x05 +#define WCD_USBSS_PMP_EN_PFM_MODE_SHIFT 0x04 +#define WCD_USBSS_PMP_EN_VREFGEN_SHIFT 0x03 +#define WCD_USBSS_PMP_EN_REGULATE_OUT_SHIFT 0x02 +#define WCD_USBSS_PMP_EN_CLK_PMP_SHIFT 0x01 +#define WCD_USBSS_PMP_EN_LOC_CTRL_EN_SHIFT 0x00 + +/* WCD_USBSS_PMP_OUT1 Fields: */ +#define WCD_USBSS_PMP_OUT1_SPARE_BITS_7_5_SHIFT 0x05 +#define WCD_USBSS_PMP_OUT1_LOC_CTRL_TRIM_SHIFT 0x04 +#define WCD_USBSS_PMP_OUT1_PMP_OUT_PCT_SHIFT 0x00 + +/* WCD_USBSS_PMP_OUT2 Fields: */ +#define WCD_USBSS_PMP_OUT2_SPARE_BITS_7_6_SHIFT 0x06 +#define WCD_USBSS_PMP_OUT2_VDWN_AUD_SHIFT 0x05 +#define WCD_USBSS_PMP_OUT2_VUP_PFM_SHIFT 0x04 +#define WCD_USBSS_PMP_OUT2_PMP_OUT_HYST_SHIFT 0x02 +#define WCD_USBSS_PMP_OUT2_PMP_OUT_MIN_MAX_SHIFT 0x00 + +/* WCD_USBSS_PMP_CLK Fields: */ +#define WCD_USBSS_PMP_CLK_SPARE_BITS_7_6_SHIFT 0x06 +#define WCD_USBSS_PMP_CLK_DLY_NOV_SHIFT 0x04 +#define WCD_USBSS_PMP_CLK_LOC_CTRL_CLK_DIV_SHIFT 0x03 +#define WCD_USBSS_PMP_CLK_CLK_DIV_SHIFT 0x02 +#define WCD_USBSS_PMP_CLK_CLK_DIV_VAL_SHIFT 0x00 + +/* WCD_USBSS_PMP_MISC1 Fields: */ +#define WCD_USBSS_PMP_MISC1_SPARE_BITS_7_6_SHIFT 0x06 +#define WCD_USBSS_PMP_MISC1_LOC_CTRL_ALL_SHIFT 0x05 +#define WCD_USBSS_PMP_MISC1_LOC_CTRL_VREF_SHIFT 0x04 +#define WCD_USBSS_PMP_MISC1_VREF_SEL_SHIFT 0x02 +#define WCD_USBSS_PMP_MISC1_VREF2ATEST_SHIFT 0x01 +#define WCD_USBSS_PMP_MISC1_CLEAR_PMP_RDY_SHIFT 0x00 + +/* WCD_USBSS_PMP_MISC2 Fields: */ +#define WCD_USBSS_PMP_MISC2_SPARE_BITS_7_3_SHIFT 0x03 +#define WCD_USBSS_PMP_MISC2_PFM_MODE_STATUS_SHIFT 0x02 +#define WCD_USBSS_PMP_MISC2_PMP_ENABLE_STATUS_SHIFT 0x01 +#define WCD_USBSS_PMP_MISC2_PMP_RDY_STATUS_SHIFT 0x00 + + +/* WCD_USBSS_RCO_EN Fields: */ +#define WCD_USBSS_RCO_EN_SPARE_BITS_7_3_SHIFT 0x03 +#define WCD_USBSS_RCO_EN_OTA_OPTION_SHIFT 0x02 +#define WCD_USBSS_RCO_EN_ENABLE_RCO_SHIFT 0x01 +#define WCD_USBSS_RCO_EN_LOC_CTRL_EN_SHIFT 0x00 + +/* WCD_USBSS_RCO_RST Fields: */ +#define WCD_USBSS_RCO_RST_SPARE_BITS_7_2_SHIFT 0x02 +#define WCD_USBSS_RCO_RST_LOC_CTRL_RST_SHIFT 0x01 +#define WCD_USBSS_RCO_RST_RESET_SHIFT 0x00 + +/* WCD_USBSS_RCO_CLK Fields: */ +#define WCD_USBSS_RCO_CLK_SPARE_BITS_7_3_SHIFT 0x03 +#define WCD_USBSS_RCO_CLK_RCO_FREQ_C_ICBIAS_SHIFT 0x00 + +/* WCD_USBSS_RCO_IBIAS Fields: */ +#define WCD_USBSS_RCO_IBIAS_SPARE_BITS_7_2_SHIFT 0x02 +#define WCD_USBSS_RCO_IBIAS_IB2_SHIFT 0x01 +#define WCD_USBSS_RCO_IBIAS_IB1_SHIFT 0x00 + +/* WCD_USBSS_RCO_MISC1 Fields: */ +#define WCD_USBSS_RCO_MISC1_SPARE_BITS_7_3_SHIFT 0x03 +#define WCD_USBSS_RCO_MISC1_ATEST_CLK_SHIFT 0x02 +#define WCD_USBSS_RCO_MISC1_ATEST_COMP_SHIFT 0x01 +#define WCD_USBSS_RCO_MISC1_ATEST_VIR_SHIFT 0x00 + +/* WCD_USBSS_RCO_MISC2 Fields: */ +#define WCD_USBSS_RCO_MISC2_SPARE_BITS_7_2_SHIFT 0x02 +#define WCD_USBSS_RCO_MISC2_COMP_OUT_SHIFT 0x01 +#define WCD_USBSS_RCO_MISC2_RESET_INT_SHIFT 0x00 + + +/* WCD_USBSS_DP_EN Fields: */ +#define WCD_USBSS_DP_EN_EN_PATH_SHIFT 0x07 +#define WCD_USBSS_DP_EN_EN_BIAS_SHIFT 0x06 +#define WCD_USBSS_DP_EN_EN_PSURGE_SHIFT 0x05 +#define WCD_USBSS_DP_EN_EN_NSURGE_SHIFT 0x04 +#define WCD_USBSS_DP_EN_P_THRESH_SEL_SHIFT 0x01 +#define WCD_USBSS_DP_EN_RED_POFF_THRESH_2X_SHIFT 0x00 + +/* WCD_USBSS_DP_BIAS Fields: */ +#define WCD_USBSS_DP_BIAS_PCOMP_BIAS_SEL_SHIFT 0x06 +#define WCD_USBSS_DP_BIAS_NCOMP_BIAS_SEL_SHIFT 0x04 +#define WCD_USBSS_DP_BIAS_PCOMP_DYN_BST_EN_SHIFT 0x03 +#define WCD_USBSS_DP_BIAS_NCOMP_DYN_BST_EN_SHIFT 0x02 +#define WCD_USBSS_DP_BIAS_EN_CMP_GAIN_RED_SHIFT 0x01 +#define WCD_USBSS_DP_BIAS_ASSERT_PLDN_ON_PWRDN_SHIFT 0x00 + +/* WCD_USBSS_DP_DN_MISC1 Fields: */ +#define WCD_USBSS_DP_DN_MISC1_EN_NS_AUD_THRESH_M2P2_DP_SHIFT 0x07 +#define WCD_USBSS_DP_DN_MISC1_EN_NS_AUD_THRESH_M2P2_DN_SHIFT 0x06 +#define WCD_USBSS_DP_DN_MISC1_DP_NCOMP_2X_DYN_BST_EN_SHIFT 0x05 +#define WCD_USBSS_DP_DN_MISC1_DP_PCOMP_2X_DYN_BST_OFF_EN_SHIFT 0x04 +#define WCD_USBSS_DP_DN_MISC1_DP_PCOMP_2X_DYN_BST_ON_EN_SHIFT 0x03 +#define WCD_USBSS_DP_DN_MISC1_DN_NCOMP_2X_DYN_BST_EN_SHIFT 0x02 +#define WCD_USBSS_DP_DN_MISC1_DN_PCOMP_2X_DYN_BST_OFF_EN_SHIFT 0x01 +#define WCD_USBSS_DP_DN_MISC1_DN_PCOMP_2X_DYN_BST_ON_EN_SHIFT 0x00 + +/* WCD_USBSS_DN_EN Fields: */ +#define WCD_USBSS_DN_EN_EN_PATH_SHIFT 0x07 +#define WCD_USBSS_DN_EN_EN_BIAS_SHIFT 0x06 +#define WCD_USBSS_DN_EN_EN_PSURGE_SHIFT 0x05 +#define WCD_USBSS_DN_EN_EN_NSURGE_SHIFT 0x04 +#define WCD_USBSS_DN_EN_P_THRESH_SEL_SHIFT 0x01 +#define WCD_USBSS_DN_EN_RED_POFF_THRESH_2X_SHIFT 0x00 + +/* WCD_USBSS_DN_BIAS Fields: */ +#define WCD_USBSS_DN_BIAS_PCOMP_BIAS_SEL_SHIFT 0x06 +#define WCD_USBSS_DN_BIAS_NCOMP_BIAS_SEL_SHIFT 0x04 +#define WCD_USBSS_DN_BIAS_PCOMP_DYN_BST_EN_SHIFT 0x03 +#define WCD_USBSS_DN_BIAS_NCOMP_DYN_BST_EN_SHIFT 0x02 +#define WCD_USBSS_DN_BIAS_EN_CMP_GAIN_RED_SHIFT 0x01 +#define WCD_USBSS_DN_BIAS_ASSERT_PLDN_ON_PWRDN_SHIFT 0x00 + +/* WCD_USBSS_DP_DN_MISC2 Fields: */ +#define WCD_USBSS_DP_DN_MISC2_RED_POFF_THRESH_3X_DP_SHIFT 0x07 +#define WCD_USBSS_DP_DN_MISC2_RED_POFF_THRESH_3X_DN_SHIFT 0x06 +#define WCD_USBSS_DP_DN_MISC2_INC_PON_THRESH_AUDMD_DP_SHIFT 0x05 +#define WCD_USBSS_DP_DN_MISC2_INC_PON_THRESH_AUDMD_DN_SHIFT 0x04 +#define WCD_USBSS_DP_DN_MISC2_EN_EXTRA_NCLAMP_SHIFT 0x02 +#define WCD_USBSS_DP_DN_MISC2_EN_NCLAMP_ALWAYS_SHIFT 0x01 +#define WCD_USBSS_DP_DN_MISC2_OVERRIDE_EN_NCLAMP_WHEN_DPDN_OVP_OFF_SHIFT 0x00 + +/* WCD_USBSS_MG1_EN Fields: */ +#define WCD_USBSS_MG1_EN_EN_PATH_SHIFT 0x07 +#define WCD_USBSS_MG1_EN_EN_BIAS_SHIFT 0x06 +#define WCD_USBSS_MG1_EN_EN_PSURGE_SHIFT 0x05 +#define WCD_USBSS_MG1_EN_EN_NSURGE_SHIFT 0x04 +#define WCD_USBSS_MG1_EN_P_THRESH_SEL_SHIFT 0x02 +#define WCD_USBSS_MG1_EN_CT_SNS_EN_SHIFT 0x01 +#define WCD_USBSS_MG1_EN_RED_POFF_THRESH_2X_SHIFT 0x00 + +/* WCD_USBSS_MG1_BIAS Fields: */ +#define WCD_USBSS_MG1_BIAS_PCOMP_BIAS_SEL_SHIFT 0x06 +#define WCD_USBSS_MG1_BIAS_NCOMP_BIAS_SEL_SHIFT 0x04 +#define WCD_USBSS_MG1_BIAS_PCOMP_DYN_BST_EN_SHIFT 0x03 +#define WCD_USBSS_MG1_BIAS_NCOMP_DYN_BST_EN_SHIFT 0x02 +#define WCD_USBSS_MG1_BIAS_EN_CMP_GAIN_RED_SHIFT 0x01 +#define WCD_USBSS_MG1_BIAS_ASSERT_PLDN_ON_PWRDN_SHIFT 0x00 + +/* WCD_USBSS_MG1_CTSNS_CTL Fields: */ +#define WCD_USBSS_MG1_CTSNS_CTL_CT_SNS_HP_EN_SHIFT 0x07 +#define WCD_USBSS_MG1_CTSNS_CTL_OVERRIDE_CTSNS_DYN_DISABLE_SHIFT 0x06 +#define WCD_USBSS_MG1_CTSNS_CTL_CT_SNS_LP_EN_SHIFT 0x05 +#define WCD_USBSS_MG1_CTSNS_CTL_GND_PIN_VMODE_THRESH_SHIFT 0x03 +#define WCD_USBSS_MG1_CTSNS_CTL_D_REG_RST_SHIFT 0x02 +#define WCD_USBSS_MG1_CTSNS_CTL_ITHRESH_BST_EN_SHIFT 0x00 + +/* WCD_USBSS_MG1_MISC Fields: */ +#define WCD_USBSS_MG1_MISC_NCOMP_2X_DYN_BST_EN_SHIFT 0x07 +#define WCD_USBSS_MG1_MISC_PCOMP_2X_DYN_BST_OFF_EN_SHIFT 0x06 +#define WCD_USBSS_MG1_MISC_PCOMP_2X_DYN_BST_ON_EN_SHIFT 0x05 +#define WCD_USBSS_MG1_MISC_RED_POFF_THRESH_3X_SHIFT 0x04 +#define WCD_USBSS_MG1_MISC_ASSERT_PLDN_ON_PWRDN_GSBU1_SHIFT 0x03 +#define WCD_USBSS_MG1_MISC_INC_NEG_SURGE_THRESH_MG1_SHIFT 0x02 +#define WCD_USBSS_MG1_MISC_MG1_GNDPIN_EN_OVERRIDE_SHIFT 0x01 +#define WCD_USBSS_MG1_MISC_MG1_GNDPIN_EN_SHIFT 0x00 + +/* WCD_USBSS_MG2_EN Fields: */ +#define WCD_USBSS_MG2_EN_EN_PATH_SHIFT 0x07 +#define WCD_USBSS_MG2_EN_EN_BIAS_SHIFT 0x06 +#define WCD_USBSS_MG2_EN_EN_PSURGE_SHIFT 0x05 +#define WCD_USBSS_MG2_EN_EN_NSURGE_SHIFT 0x04 +#define WCD_USBSS_MG2_EN_P_THRESH_SEL_SHIFT 0x02 +#define WCD_USBSS_MG2_EN_CT_SNS_EN_SHIFT 0x01 +#define WCD_USBSS_MG2_EN_RED_POFF_THRESH_2X_SHIFT 0x00 + +/* WCD_USBSS_MG2_BIAS Fields: */ +#define WCD_USBSS_MG2_BIAS_PCOMP_BIAS_SEL_SHIFT 0x06 +#define WCD_USBSS_MG2_BIAS_NCOMP_BIAS_SEL_SHIFT 0x04 +#define WCD_USBSS_MG2_BIAS_PCOMP_DYN_BST_EN_SHIFT 0x03 +#define WCD_USBSS_MG2_BIAS_NCOMP_DYN_BST_EN_SHIFT 0x02 +#define WCD_USBSS_MG2_BIAS_EN_CMP_GAIN_RED_SHIFT 0x01 +#define WCD_USBSS_MG2_BIAS_ASSERT_PLDN_ON_PWRDN_SHIFT 0x00 + +/* WCD_USBSS_MG2_CTSNS_CTL Fields: */ +#define WCD_USBSS_MG2_CTSNS_CTL_CT_SNS_HP_EN_SHIFT 0x07 +#define WCD_USBSS_MG2_CTSNS_CTL_OVERRIDE_CTSNS_DYN_DISABLE_SHIFT 0x06 +#define WCD_USBSS_MG2_CTSNS_CTL_CT_SNS_LP_EN_SHIFT 0x05 +#define WCD_USBSS_MG2_CTSNS_CTL_GND_PIN_VMODE_THRESH_SHIFT 0x03 +#define WCD_USBSS_MG2_CTSNS_CTL_D_REG_RST_SHIFT 0x02 +#define WCD_USBSS_MG2_CTSNS_CTL_ITHRESH_BST_EN_SHIFT 0x00 + +/* WCD_USBSS_MG2_MISC Fields: */ +#define WCD_USBSS_MG2_MISC_NCOMP_2X_DYN_BST_EN_SHIFT 0x07 +#define WCD_USBSS_MG2_MISC_PCOMP_2X_DYN_BST_OFF_EN_SHIFT 0x06 +#define WCD_USBSS_MG2_MISC_PCOMP_2X_DYN_BST_ON_EN_SHIFT 0x05 +#define WCD_USBSS_MG2_MISC_RED_POFF_THRESH_3X_SHIFT 0x04 +#define WCD_USBSS_MG2_MISC_ASSERT_PLDN_ON_PWRDN_GSBU2_SHIFT 0x03 +#define WCD_USBSS_MG2_MISC_INC_NEG_SURGE_THRESH_MG2_SHIFT 0x02 +#define WCD_USBSS_MG2_MISC_MG2_GNDPIN_EN_OVERRIDE_SHIFT 0x01 +#define WCD_USBSS_MG2_MISC_MG2_GNDPIN_EN_SHIFT 0x00 + +/* WCD_USBSS_BIAS_TOP Fields: */ +#define WCD_USBSS_BIAS_TOP_EN_BIAS_TOP_SHIFT 0x07 +#define WCD_USBSS_BIAS_TOP_VREF_AMP_BIAS_BST_SHIFT 0x06 +#define WCD_USBSS_BIAS_TOP_OVP_EN_DPDN_OVERRIDE_SHIFT 0x05 +#define WCD_USBSS_BIAS_TOP_DIS_NCLAMP_DPDN_SHIFT 0x04 +#define WCD_USBSS_BIAS_TOP_SPARE_BITS_3_0_SHIFT 0x00 + +/* WCD_USBSS_VREF_CTRL Fields: */ +#define WCD_USBSS_VREF_CTRL_EN_VREF_AMP_SHIFT 0x07 +#define WCD_USBSS_VREF_CTRL_VREF_AMP_TUNE_SHIFT 0x03 +#define WCD_USBSS_VREF_CTRL_VREF_AMP_TUNE_REG_EN_SHIFT 0x02 +#define WCD_USBSS_VREF_CTRL_HIGH_CAP_DRV_EN_SHIFT 0x01 +#define WCD_USBSS_VREF_CTRL_SPARE_BITS_0_SHIFT 0x00 + +/* WCD_USBSS_TOP_MISC1 Fields: */ +#define WCD_USBSS_TOP_MISC1_EN_PLDN_GSBU12_SHIFT 0x07 +#define WCD_USBSS_TOP_MISC1_D_REG_RST_OVP_INTR_SHIFT 0x06 +#define WCD_USBSS_TOP_MISC1_SPARE_BITS_5_SHIFT 0x05 +#define WCD_USBSS_TOP_MISC1_SPARE_BITS_4_3_SHIFT 0x03 +#define WCD_USBSS_TOP_MISC1_OVP_EN_SBU12_OVERRIDE_SHIFT 0x02 +#define WCD_USBSS_TOP_MISC1_ATEST_SEL_SHIFT 0x00 + +/* WCD_USBSS_TOP_MISC2 Fields: */ +#define WCD_USBSS_TOP_MISC2_EN_ADD_PLDN_DP_SHIFT 0x07 +#define WCD_USBSS_TOP_MISC2_EN_ADD_PLDN_DN_SHIFT 0x06 +#define WCD_USBSS_TOP_MISC2_EN_ADD_PLDN_MG1_SHIFT 0x05 +#define WCD_USBSS_TOP_MISC2_EN_ADD_PLDN_MG2_SHIFT 0x04 +#define WCD_USBSS_TOP_MISC2_EN_PWRUP_CMP_GATE_DP_SHIFT 0x03 +#define WCD_USBSS_TOP_MISC2_EN_PWRUP_CMP_GATE_DN_SHIFT 0x02 +#define WCD_USBSS_TOP_MISC2_EN_PWRUP_CMP_GATE_MG1_SHIFT 0x01 +#define WCD_USBSS_TOP_MISC2_EN_PWRUP_CMP_GATE_MG2_SHIFT 0x00 + +/* WCD_USBSS_STATUS_1 Fields: */ +#define WCD_USBSS_STATUS_1_CMP_OUT_PS_DP_SHIFT 0x07 +#define WCD_USBSS_STATUS_1_CMP_OUT_NS_DP_SHIFT 0x06 +#define WCD_USBSS_STATUS_1_CMP_OUT_PSNS_DP_SHIFT 0x05 +#define WCD_USBSS_STATUS_1_CMP_OUT_PS_DN_SHIFT 0x04 +#define WCD_USBSS_STATUS_1_CMP_OUT_NS_DN_SHIFT 0x03 +#define WCD_USBSS_STATUS_1_CMP_OUT_PSNS_DN_SHIFT 0x02 +#define WCD_USBSS_STATUS_1_OVP_DP_EN_SHIFT 0x01 +#define WCD_USBSS_STATUS_1_OVP_DN_EN_SHIFT 0x00 + +/* WCD_USBSS_STATUS_2 Fields: */ +#define WCD_USBSS_STATUS_2_CMP_OUT_PSNS_MG1_SHIFT 0x07 +#define WCD_USBSS_STATUS_2_CMP_OUT_GNDSW_OFF_MG1_SHIFT 0x06 +#define WCD_USBSS_STATUS_2_CT_SNS_OVP_DET_LAT_MG1_SHIFT 0x05 +#define WCD_USBSS_STATUS_2_CMP_OUT_PS_MG2_SHIFT 0x04 +#define WCD_USBSS_STATUS_2_CMP_OUT_NS_MG2_SHIFT 0x03 +#define WCD_USBSS_STATUS_2_CMP_OUT_PSNS_MG2_SHIFT 0x02 +#define WCD_USBSS_STATUS_2_CMP_OUT_GNDSW_OFF_MG2_SHIFT 0x01 +#define WCD_USBSS_STATUS_2_CT_SNS_OVP_DET_LAT_MG2_SHIFT 0x00 + +/* WCD_USBSS_STATUS_3 Fields: */ +#define WCD_USBSS_STATUS_3_VREF_EN_SHIFT 0x07 +#define WCD_USBSS_STATUS_3_BIAS_TOP_EN_SHIFT 0x06 +#define WCD_USBSS_STATUS_3_CMP_OUT_PS_MG1_SHIFT 0x05 +#define WCD_USBSS_STATUS_3_CMP_OUT_NS_MG1_SHIFT 0x04 +#define WCD_USBSS_STATUS_3_OVP_MG1_EN_SHIFT 0x03 +#define WCD_USBSS_STATUS_3_OVP_MG2_EN_SHIFT 0x02 +#define WCD_USBSS_STATUS_3_SPARE_BITS_1_0_SHIFT 0x00 + + +/* WCD_USBSS_EXT_LIN_EN Fields: */ +#define WCD_USBSS_EXT_LIN_EN_EXT_LIN_EN_OVR_SHIFT 0x07 +#define WCD_USBSS_EXT_LIN_EN_EXT_GNDL_LIN_EN_REG_SHIFT 0x06 +#define WCD_USBSS_EXT_LIN_EN_EXT_L_LIN_EN_REG_SHIFT 0x05 +#define WCD_USBSS_EXT_LIN_EN_EXT_R_LIN_EN_REG_SHIFT 0x04 +#define WCD_USBSS_EXT_LIN_EN_EXTSW_LIN_PWR_OVR_EN_SHIFT 0x03 +#define WCD_USBSS_EXT_LIN_EN_EXT_GNDR_LIN_EN_REG_SHIFT 0x02 +#define WCD_USBSS_EXT_LIN_EN_CP_SWR_MG12_REG_SHIFT 0x01 +#define WCD_USBSS_EXT_LIN_EN_D_EXT_GND_LIN_BYP_SHIFT 0x00 + +/* WCD_USBSS_INT_LIN_EN Fields: */ +#define WCD_USBSS_INT_LIN_EN_INT_LIN_EN_OVR_SHIFT 0x07 +#define WCD_USBSS_INT_LIN_EN_INT_L_LIN_EN_REG_SHIFT 0x06 +#define WCD_USBSS_INT_LIN_EN_INT_R_LIN_EN_REG_SHIFT 0x05 +#define WCD_USBSS_INT_LIN_EN_INTSW_LIN_PWR_OVR_EN_SHIFT 0x04 +#define WCD_USBSS_INT_LIN_EN_LDO_SWR_MG12_REG_SHIFT 0x03 +#define WCD_USBSS_INT_LIN_EN_OVP_SWR_MG12_REG_SHIFT 0x02 +#define WCD_USBSS_INT_LIN_EN_INT_L_2ND_COMP_EN_REG_SHIFT 0x01 +#define WCD_USBSS_INT_LIN_EN_INT_R_2ND_COMP_EN_REG_SHIFT 0x00 + +/* WCD_USBSS_COMBINER_IREF_PROG_1 Fields: */ +#define WCD_USBSS_COMBINER_IREF_PROG_1_ACDC_COMBINER_AUD_L_IREF_SHIFT 0x04 +#define WCD_USBSS_COMBINER_IREF_PROG_1_ACDC_COMBINER_AUD_R_IREF_SHIFT 0x00 + +/* WCD_USBSS_COMBINER_IREF_PROG_2 Fields: */ +#define WCD_USBSS_COMBINER_IREF_PROG_2_ACDC_COMBINER_GND_L_IREF_SHIFT 0x04 +#define WCD_USBSS_COMBINER_IREF_PROG_2_ACDC_COMBINER_GND_R_IREF_SHIFT 0x00 + +/* WCD_USBSS_EXTSW_AMP_BIAS Fields: */ +#define WCD_USBSS_EXTSW_AMP_BIAS_EXTSW_AMP_BIAS_1_SHIFT 0x04 +#define WCD_USBSS_EXTSW_AMP_BIAS_EXTSW_AMP_BIAS_2_SHIFT 0x00 + +/* WCD_USBSS_INTSW_ILIFT Fields: */ +#define WCD_USBSS_INTSW_ILIFT_INTSW_ILIFT_L_SHIFT 0x04 +#define WCD_USBSS_INTSW_ILIFT_INTSW_ILIFT_R_SHIFT 0x00 + +/* WCD_USBSS_EXT_SW_CTRL_1 Fields: */ +#define WCD_USBSS_EXT_SW_CTRL_1_CP_SW_OVR_SHIFT 0x07 +#define WCD_USBSS_EXT_SW_CTRL_1_CP_SW_DNL_REG_SHIFT 0x06 +#define WCD_USBSS_EXT_SW_CTRL_1_CP_SW_DPR_REG_SHIFT 0x05 +#define WCD_USBSS_EXT_SW_CTRL_1_CP_SWL_MG12_REG_SHIFT 0x04 +#define WCD_USBSS_EXT_SW_CTRL_1_LDO_SW_OVR_SHIFT 0x03 +#define WCD_USBSS_EXT_SW_CTRL_1_LDO_SW_DNL_REG_SHIFT 0x02 +#define WCD_USBSS_EXT_SW_CTRL_1_LDO_SW_DPR_REG_SHIFT 0x01 +#define WCD_USBSS_EXT_SW_CTRL_1_LDO_SWL_MG12_REG_SHIFT 0x00 + +/* WCD_USBSS_EXT_SW_CTRL_2 Fields: */ +#define WCD_USBSS_EXT_SW_CTRL_2_OVP_SW_OVR_SHIFT 0x07 +#define WCD_USBSS_EXT_SW_CTRL_2_OVP_SW_DNL_REG_SHIFT 0x06 +#define WCD_USBSS_EXT_SW_CTRL_2_OVP_SW_DPR_REG_SHIFT 0x05 +#define WCD_USBSS_EXT_SW_CTRL_2_OVP_SWL_MG12_REG_SHIFT 0x04 +#define WCD_USBSS_EXT_SW_CTRL_2_VNEGDAC_LDO_BUF_IBIAS_PROG_SHIFT 0x00 + +/* WCD_USBSS_INT_SW_CTRL_1 Fields: */ +#define WCD_USBSS_INT_SW_CTRL_1_SW_MIC_EN_OVR_SHIFT 0x07 +#define WCD_USBSS_INT_SW_CTRL_1_SW_MIC_MG1_EN_REG_SHIFT 0x06 +#define WCD_USBSS_INT_SW_CTRL_1_SW_MIC_MG2_EN_REG_SHIFT 0x05 +#define WCD_USBSS_INT_SW_CTRL_1_SW_AGND_EN_OVR_SHIFT 0x04 +#define WCD_USBSS_INT_SW_CTRL_1_SW_AGND_MG1_EN_REG_SHIFT 0x03 +#define WCD_USBSS_INT_SW_CTRL_1_SW_AGND_MG2_EN_REG_SHIFT 0x02 +#define WCD_USBSS_INT_SW_CTRL_1_INT_L_2ND_COMP_EN_OVR_SHIFT 0x01 +#define WCD_USBSS_INT_SW_CTRL_1_INT_R_2ND_COMP_EN_OVR_SHIFT 0x00 + +/* WCD_USBSS_INT_SW_CTRL_2 Fields: */ +#define WCD_USBSS_INT_SW_CTRL_2_SW_SENSE_GSBU1_EN_REG_SHIFT 0x07 +#define WCD_USBSS_INT_SW_CTRL_2_SW_SENSE_GSBU2_EN_REG_SHIFT 0x06 +#define WCD_USBSS_INT_SW_CTRL_2_INTSW_L_RDC_PRG_SHIFT 0x03 +#define WCD_USBSS_INT_SW_CTRL_2_INTSW_R_RDC_PRG_SHIFT 0x00 + +/* WCD_USBSS_INT_SW_CTRL_3 Fields: */ +#define WCD_USBSS_INT_SW_CTRL_3_D_INTSW_2NDCOMP_PRG_L_SHIFT 0x05 +#define WCD_USBSS_INT_SW_CTRL_3_D_INTSW_2NDCOMP_PRG_R_SHIFT 0x02 +#define WCD_USBSS_INT_SW_CTRL_3_SW_SENSE_EN_OVR_SHIFT 0x01 +#define WCD_USBSS_INT_SW_CTRL_3_VNEGDAC_LDO_BUF_OVR_EN_SHIFT 0x00 + +/* WCD_USBSS_ATEST_CTRL Fields: */ +#define WCD_USBSS_ATEST_CTRL_ATEST7_SHIFT 0x07 +#define WCD_USBSS_ATEST_CTRL_ATEST6_SHIFT 0x06 +#define WCD_USBSS_ATEST_CTRL_ATEST5_SHIFT 0x05 +#define WCD_USBSS_ATEST_CTRL_ATEST4_SHIFT 0x04 +#define WCD_USBSS_ATEST_CTRL_ATEST3_SHIFT 0x03 +#define WCD_USBSS_ATEST_CTRL_ATEST2_SHIFT 0x02 +#define WCD_USBSS_ATEST_CTRL_ATEST1_SHIFT 0x01 +#define WCD_USBSS_ATEST_CTRL_ATEST0_SHIFT 0x00 + +/* WCD_USBSS_EXT_LIN_AUD_CEQ_PRG Fields: */ +#define WCD_USBSS_EXT_LIN_AUD_CEQ_PRG_EXT_AUD_LINL_AUD_CEQ_SHIFT 0x04 +#define WCD_USBSS_EXT_LIN_AUD_CEQ_PRG_EXT_AUD_LINR_AUD_CEQ_SHIFT 0x00 + +/* WCD_USBSS_EXT_LIN_GND_CEQ_PRG Fields: */ +#define WCD_USBSS_EXT_LIN_GND_CEQ_PRG_EXT_GND_LINL_AUD_CEQ_SHIFT 0x04 +#define WCD_USBSS_EXT_LIN_GND_CEQ_PRG_EXT_GND_LINR_AUD_CEQ_SHIFT 0x00 + +/* WCD_USBSS_LIN_STATUS_1 Fields: */ +#define WCD_USBSS_LIN_STATUS_1_D_EXT_AUDSW_VRATIO_L_SHIFT 0x00 + +/* WCD_USBSS_LIN_STATUS_2 Fields: */ +#define WCD_USBSS_LIN_STATUS_2_D_EXT_AUDSW_VRATIO_R_SHIFT 0x00 + +/* WCD_USBSS_LIN_STATUS_3 Fields: */ +#define WCD_USBSS_LIN_STATUS_3_D_EXT_GNDSW_VRATIO_L_SHIFT 0x00 + +/* WCD_USBSS_LIN_STATUS_4 Fields: */ +#define WCD_USBSS_LIN_STATUS_4_D_EXT_GNDSW_VRATIO_R_SHIFT 0x00 + +/* WCD_USBSS_SW_LIN_CTRL Fields: */ +#define WCD_USBSS_SW_LIN_CTRL_D_INTSW_LEGACY_PULL_VNEGDAC_REG_SHIFT 0x07 +#define WCD_USBSS_SW_LIN_CTRL_INTSW_LEGACY_PULL_VNEGDAC_OVR_SHIFT 0x06 +#define WCD_USBSS_SW_LIN_CTRL_D_INTSW_PULL_GND_REG_SHIFT 0x05 +#define WCD_USBSS_SW_LIN_CTRL_INTSW_PULL_GND_OVR_SHIFT 0x04 +#define WCD_USBSS_SW_LIN_CTRL_D_RDAC_CEQ_EN_SHIFT 0x03 +#define WCD_USBSS_SW_LIN_CTRL_D_INTSW_LEGACY_EN_REG_SHIFT 0x02 +#define WCD_USBSS_SW_LIN_CTRL_D_INTSW_LEGACY_EN_OVR_SHIFT 0x01 +#define WCD_USBSS_SW_LIN_CTRL_LIN_TOP_ATEST_EN_SHIFT 0x00 + +/* WCD_USBSS_SW_LIN_CTRL_1 Fields: */ +#define WCD_USBSS_SW_LIN_CTRL_1_AC_TRIMCODE_OVR_EN_SHIFT 0x01 +#define WCD_USBSS_SW_LIN_CTRL_1_DC_TRIMCODE_OVR_EN_SHIFT 0x00 + + +/* WCD_USBSS_LDO_3P6 Fields: */ +#define WCD_USBSS_LDO_3P6_D_INT_AUDSW_DNW_DBG_SHIFT 0x07 +#define WCD_USBSS_LDO_3P6_D_USB_PMIC_USB_DNW_DBG_SHIFT 0x06 +#define WCD_USBSS_LDO_3P6_NOT_USED_SHIFT 0x00 + +/* WCD_USBSS_SWITCH_BANK_ATEST Fields: */ +#define WCD_USBSS_SWITCH_BANK_ATEST_ATEST_SWBANK_EN_SHIFT 0x07 +#define WCD_USBSS_SWITCH_BANK_ATEST_ATEST_DPRDNL_SWBANK_SHIFT 0x04 +#define WCD_USBSS_SWITCH_BANK_ATEST_ATEST_GSBU_SWBANK_SHIFT 0x01 +#define WCD_USBSS_SWITCH_BANK_ATEST_NOT_USED_SHIFT 0x00 + +/* WCD_USBSS_EQ_EN Fields: */ +#define WCD_USBSS_EQ_EN_D_REG_CTL_OVERRIDE_SHIFT 0x07 +#define WCD_USBSS_EQ_EN_D_REG_EN_EQUALIZER_SHIFT 0x06 +#define WCD_USBSS_EQ_EN_D_REG_EQ_REF_SEL_SHIFT 0x04 +#define WCD_USBSS_EQ_EN_D_REG_EQ_SEG_SEL_SHIFT 0x00 + +/* WCD_USBSS_EQ_MISC Fields: */ +#define WCD_USBSS_EQ_MISC_ATEST_SEL_SHIFT 0x06 +#define WCD_USBSS_EQ_MISC_D_REG_EQ_BIAS_SEL_SHIFT 0x04 +#define WCD_USBSS_EQ_MISC_D_REG_EQ_RC_SEL_SHIFT 0x02 +#define WCD_USBSS_EQ_MISC_D_REG_EQ_VREF_BIAS_SEL_SHIFT 0x00 + +/* WCD_USBSS_STATUS_MISC Fields: */ +#define WCD_USBSS_STATUS_MISC_NOT_USED_SHIFT 0x00 + + +/* WCD_USBSS_FSM_DELAYS1 Fields: */ +#define WCD_USBSS_FSM_DELAYS1_DELTA_T2_SHIFT 0x06 +#define WCD_USBSS_FSM_DELAYS1_SPARE_BITS_5_0_SHIFT 0x00 + +/* WCD_USBSS_FSM_DELAYS2 Fields: */ +#define WCD_USBSS_FSM_DELAYS2_DELTA_T4_SHIFT 0x04 +#define WCD_USBSS_FSM_DELAYS2_DELTA_T3_SHIFT 0x00 + +/* WCD_USBSS_FSM_DELAYS3 Fields: */ +#define WCD_USBSS_FSM_DELAYS3_DELTA_T5_SHIFT 0x03 +#define WCD_USBSS_FSM_DELAYS3_SPARE_BITS_2_0_SHIFT 0x00 + +/* WCD_USBSS_FSM_DELAYS4 Fields: */ +#define WCD_USBSS_FSM_DELAYS4_DELTA_T6_SHIFT 0x03 +#define WCD_USBSS_FSM_DELAYS4_SPARE_BITS_2_0_SHIFT 0x00 + +/* WCD_USBSS_FSM_DELAYS5 Fields: */ +#define WCD_USBSS_FSM_DELAYS5_DELTA_T8_SHIFT 0x04 +#define WCD_USBSS_FSM_DELAYS5_DELTA_T7_SHIFT 0x02 +#define WCD_USBSS_FSM_DELAYS5_SPARE_BITS_1_0_SHIFT 0x00 + +/* WCD_USBSS_FSM_DELAYS6 Fields: */ +#define WCD_USBSS_FSM_DELAYS6_DELTA_T11_SHIFT 0x04 +#define WCD_USBSS_FSM_DELAYS6_DELTA_T9_SHIFT 0x00 + +/* WCD_USBSS_FSM_DELAYS7 Fields: */ +#define WCD_USBSS_FSM_DELAYS7_DELTA_T14_SHIFT 0x04 +#define WCD_USBSS_FSM_DELAYS7_DELTA_T12_SHIFT 0x00 + +/* WCD_USBSS_FSM_DELAYS8 Fields: */ +#define WCD_USBSS_FSM_DELAYS8_DELTA_T13_SHIFT 0x03 +#define WCD_USBSS_FSM_DELAYS8_D_REG_EN_SUP_SW_OVPREF_SHIFT 0x02 +#define WCD_USBSS_FSM_DELAYS8_SPARE_BITS_1_0_SHIFT 0x00 + +/* WCD_USBSS_FSM_DEBUG_SIGNALS Fields: */ +#define WCD_USBSS_FSM_DEBUG_SIGNALS_D_EN_OVPREF_REG_SHIFT 0x07 +#define WCD_USBSS_FSM_DEBUG_SIGNALS_D_EN_CP_REG_SHIFT 0x06 +#define WCD_USBSS_FSM_DEBUG_SIGNALS_D_EN_LDO_REG_SHIFT 0x05 +#define WCD_USBSS_FSM_DEBUG_SIGNALS_D_USB_STANDBY_STATE_EN_DELAYED1_REG_SHIFT 0x04 +#define WCD_USBSS_FSM_DEBUG_SIGNALS_D_USB_STANDBY_STATE_EN_DELAYED2_REG_SHIFT 0x03 +#define WCD_USBSS_FSM_DEBUG_SIGNALS_D_REG_FIX_MICGND_SWAP_ENB_SHIFT 0x02 +#define WCD_USBSS_FSM_DEBUG_SIGNALS_D_REG_OVERRIDE_SUPPLY_SWITCH_SHIFT 0x01 +#define WCD_USBSS_FSM_DEBUG_SIGNALS_D_REG_FIX_REDUCEPAVNEGCURRENT_ENB_SHIFT 0x00 + +/* WCD_USBSS_FSM_OVERRIDE Fields: */ +#define WCD_USBSS_FSM_OVERRIDE_D_FSM_EN_OVERRIDE_SHIFT 0x07 +#define WCD_USBSS_FSM_OVERRIDE_D_VNEG_PULLDN_MASK_SHIFT 0x06 +#define WCD_USBSS_FSM_OVERRIDE_EQ_ENABLE_GATED_BY_OVP_SHIFT 0x05 +#define WCD_USBSS_FSM_OVERRIDE_RCO_FAST_RATE_EFUSE_OVERRIDE_SHIFT 0x04 +#define WCD_USBSS_FSM_OVERRIDE_OVP_THRESHOLD_EFUSE_OVERRIDE_SHIFT 0x03 +#define WCD_USBSS_FSM_OVERRIDE_EQ_SEG_SEL_EFUSE_OVERRIDE_SHIFT 0x02 +#define WCD_USBSS_FSM_OVERRIDE_CP_PFM_EFUSE_OVERRIDE_SHIFT 0x01 +#define WCD_USBSS_FSM_OVERRIDE_EQ_EN_EFUSE_OVERRIDE_SHIFT 0x00 + +/* WCD_USBSS_ENABLE_STATUS Fields: */ +#define WCD_USBSS_ENABLE_STATUS_D_EN_OVPREF_SHIFT 0x07 +#define WCD_USBSS_ENABLE_STATUS_D_EN_CP_SHIFT 0x06 +#define WCD_USBSS_ENABLE_STATUS_D_EN_LDO_SHIFT 0x05 +#define WCD_USBSS_ENABLE_STATUS_D_USB_STANDBY_STATE_EXTENDED1_SHIFT 0x04 +#define WCD_USBSS_ENABLE_STATUS_D_USB_STANDBY_STATE_EXTENDED2_SHIFT 0x03 +#define WCD_USBSS_ENABLE_STATUS_TIE_LOW_SHIFT 0x00 + +/* WCD_USBSS_FRZ_STATUS Fields: */ +#define WCD_USBSS_FRZ_STATUS_D_FRZ_N_SWITCHES_EQ_SHIFT 0x07 +#define WCD_USBSS_FRZ_STATUS_D_FRZ_ALL_SHIFT 0x06 +#define WCD_USBSS_FRZ_STATUS_D_FRZ_OVPREF_SHIFT 0x05 +#define WCD_USBSS_FRZ_STATUS_D_FSM_RESET_SHIFT 0x04 +#define WCD_USBSS_FRZ_STATUS_TIE_LOW_SHIFT 0x00 + + +/* WCD_USBSS_DPR_DNL_SWITCH_ENABLE_STATUS Fields: */ +#define WCD_USBSS_DPR_DNL_SWITCH_ENABLE_STATUS_D_SW_DP_DPR_ENABLE_SHIFT 0x07 +#define WCD_USBSS_DPR_DNL_SWITCH_ENABLE_STATUS_D_SW_DP2_DPR_ENABLE_SHIFT 0x06 +#define WCD_USBSS_DPR_DNL_SWITCH_ENABLE_STATUS_D_SW_R_DPR_ENABLE_SHIFT 0x05 +#define WCD_USBSS_DPR_DNL_SWITCH_ENABLE_STATUS_D_SW_DN_DNL_ENABLE_SHIFT 0x04 +#define WCD_USBSS_DPR_DNL_SWITCH_ENABLE_STATUS_D_SW_DN2_DNL_ENABLE_SHIFT 0x03 +#define WCD_USBSS_DPR_DNL_SWITCH_ENABLE_STATUS_D_SW_L_DNL_ENABLE_SHIFT 0x02 +#define WCD_USBSS_DPR_DNL_SWITCH_ENABLE_STATUS_TIE_LOW_SHIFT 0x00 + +/* WCD_USBSS_SBU_GSBU_SWITCH_ENABLE_STATUS Fields: */ +#define WCD_USBSS_SBU_GSBU_SWITCH_ENABLE_STATUS_D_SW_MIC_MG1_ENABLE_SHIFT 0x07 +#define WCD_USBSS_SBU_GSBU_SWITCH_ENABLE_STATUS_D_SW_MIC_MG2_ENABLE_SHIFT 0x06 +#define WCD_USBSS_SBU_GSBU_SWITCH_ENABLE_STATUS_D_SW_AGND_MG1_ENABLE_SHIFT 0x05 +#define WCD_USBSS_SBU_GSBU_SWITCH_ENABLE_STATUS_D_SW_AGND_MG2_ENABLE_SHIFT 0x04 +#define WCD_USBSS_SBU_GSBU_SWITCH_ENABLE_STATUS_D_SW_SENSE_GSBU1_ENABLE_SHIFT 0x03 +#define WCD_USBSS_SBU_GSBU_SWITCH_ENABLE_STATUS_D_SW_SENSE_GSBU2_ENABLE_SHIFT 0x02 +#define WCD_USBSS_SBU_GSBU_SWITCH_ENABLE_STATUS_TIE_LOW_SHIFT 0x00 + +/* WCD_USBSS_DPAUX_SWITCH_ENABLE_STATUS Fields: */ +#define WCD_USBSS_DPAUX_SWITCH_ENABLE_STATUS_D_SW_DPAUXM_MG1_ENABLE_SHIFT 0x07 +#define WCD_USBSS_DPAUX_SWITCH_ENABLE_STATUS_D_SW_DPAUXM_MG2_ENABLE_SHIFT 0x06 +#define WCD_USBSS_DPAUX_SWITCH_ENABLE_STATUS_D_SW_DPAUXP_MG1_ENABLE_SHIFT 0x05 +#define WCD_USBSS_DPAUX_SWITCH_ENABLE_STATUS_D_SW_DPAUXP_MG2_ENABLE_SHIFT 0x04 +#define WCD_USBSS_DPAUX_SWITCH_ENABLE_STATUS_TIE_LOW_SHIFT 0x00 + +/* WCD_USBSS_DPR_DNL_EXTFET_GATE_MUX_STATUS Fields: */ +#define WCD_USBSS_DPR_DNL_EXTFET_GATE_MUX_STATUS_D_LIN_EN_DNL_SHIFT 0x07 +#define WCD_USBSS_DPR_DNL_EXTFET_GATE_MUX_STATUS_D_CP_SW_EN_DNL_SHIFT 0x06 +#define WCD_USBSS_DPR_DNL_EXTFET_GATE_MUX_STATUS_D_OVP_SW_EN_DNL_SHIFT 0x05 +#define WCD_USBSS_DPR_DNL_EXTFET_GATE_MUX_STATUS_D_LDO_SW_EN_DNL_SHIFT 0x04 +#define WCD_USBSS_DPR_DNL_EXTFET_GATE_MUX_STATUS_D_LIN_EN_DPR_SHIFT 0x03 +#define WCD_USBSS_DPR_DNL_EXTFET_GATE_MUX_STATUS_D_CP_SW_EN_DPR_SHIFT 0x02 +#define WCD_USBSS_DPR_DNL_EXTFET_GATE_MUX_STATUS_D_OVP_SW_EN_DPR_SHIFT 0x01 +#define WCD_USBSS_DPR_DNL_EXTFET_GATE_MUX_STATUS_D_LDO_SW_EN_DPR_SHIFT 0x00 + +/* WCD_USBSS_SBU_EXTFET_GATE_MUX_OVP_STATUS Fields: */ +#define WCD_USBSS_SBU_EXTFET_GATE_MUX_OVP_STATUS_D_LIN_EN_MG12_SHIFT 0x07 +#define WCD_USBSS_SBU_EXTFET_GATE_MUX_OVP_STATUS_D_CP_SW_EN_MG12_SHIFT 0x06 +#define WCD_USBSS_SBU_EXTFET_GATE_MUX_OVP_STATUS_D_OVP_SW_EN_MG12_SHIFT 0x05 +#define WCD_USBSS_SBU_EXTFET_GATE_MUX_OVP_STATUS_D_LDO_SW_EN_MG12_SHIFT 0x04 +#define WCD_USBSS_SBU_EXTFET_GATE_MUX_OVP_STATUS_D_EQ_EN_SHIFT 0x03 +#define WCD_USBSS_SBU_EXTFET_GATE_MUX_OVP_STATUS_D_OVP_MG12_ENABLE_SHIFT 0x02 +#define WCD_USBSS_SBU_EXTFET_GATE_MUX_OVP_STATUS_D_OVP_DPR_ENABLE_SHIFT 0x01 +#define WCD_USBSS_SBU_EXTFET_GATE_MUX_OVP_STATUS_D_OVP_DNL_ENABLE_SHIFT 0x00 + +/* WCD_USBSS_CP_LIN_CNTL_STATUS Fields: */ +#define WCD_USBSS_CP_LIN_CNTL_STATUS_D_CP_ENABLE_SHIFT 0x07 +#define WCD_USBSS_CP_LIN_CNTL_STATUS_D_CP_PFM_ENABLE_SHIFT 0x06 +#define WCD_USBSS_CP_LIN_CNTL_STATUS_D_CP_CLK_DIV_SHIFT 0x04 +#define WCD_USBSS_CP_LIN_CNTL_STATUS_D_LIN_MODE_SHIFT 0x02 +#define WCD_USBSS_CP_LIN_CNTL_STATUS_D_AUDIO_EN_OVP_SHIFT 0x01 +#define WCD_USBSS_CP_LIN_CNTL_STATUS_TIE_LOW_SHIFT 0x00 + + +/* WCD_USBSS_DISP_AUXP_THRESH Fields: */ +#define WCD_USBSS_DISP_AUXP_THRESH_DISP_AUXP_OVPON_CM_SHIFT 0x05 +#define WCD_USBSS_DISP_AUXP_THRESH_DISP_AUXP_OVPON_INCNEG_CM_SHIFT 0x02 +#define WCD_USBSS_DISP_AUXP_THRESH_SPARE_BITS_1_0_SHIFT 0x00 + +/* WCD_USBSS_DISP_AUXP_CTL Fields: */ +#define WCD_USBSS_DISP_AUXP_CTL_GNDSW_LK_TRK_EN_SHIFT 0x07 +#define WCD_USBSS_DISP_AUXP_CTL_DISP_CM_MOD_EN_SHIFT 0x06 +#define WCD_USBSS_DISP_AUXP_CTL_DISP_MODE_OVERRIDE_EN_SHIFT 0x05 +#define WCD_USBSS_DISP_AUXP_CTL_OVP_NEG_THRESH_INC_OVERRIDE_EN_SHIFT 0x04 +#define WCD_USBSS_DISP_AUXP_CTL_OVP_OVERRIDE_EN_SHIFT 0x03 +#define WCD_USBSS_DISP_AUXP_CTL_LK_CANCEL_TRK_COEFF_SHIFT 0x00 + +/* WCD_USBSS_DISP_AUXM_THRESH Fields: */ +#define WCD_USBSS_DISP_AUXM_THRESH_SBU1_DISP_AUXM_OVPON_CM_SHIFT 0x05 +#define WCD_USBSS_DISP_AUXM_THRESH_SPARE_BITS_4_0_SHIFT 0x00 + +/* WCD_USBSS_DISP_AUXM_CTL Fields: */ +#define WCD_USBSS_DISP_AUXM_CTL_GNDSW_LK_TRK_EN_SHIFT 0x07 +#define WCD_USBSS_DISP_AUXM_CTL_DISP_CM_MOD_EN_SHIFT 0x06 +#define WCD_USBSS_DISP_AUXM_CTL_DISP_MODE_OVERRIDE_EN_SHIFT 0x05 +#define WCD_USBSS_DISP_AUXM_CTL_SPARE_BITS_4_SHIFT 0x04 +#define WCD_USBSS_DISP_AUXM_CTL_OVP_OVERRIDE_EN_SHIFT 0x03 +#define WCD_USBSS_DISP_AUXM_CTL_LK_CANCEL_TRK_COEFF_SHIFT 0x00 + + +/* WCD_USBSS_CTRL_0 Fields: */ +#define WCD_USBSS_CTRL_0_PWDN_CTL_SHIFT 0x07 +#define WCD_USBSS_CTRL_0_CAL_CTL_SHIFT 0x06 +#define WCD_USBSS_CTRL_0_IBIAS_ERRAMP_SHIFT 0x04 +#define WCD_USBSS_CTRL_0_RES_LOAD_CTL_SHIFT 0x02 +#define WCD_USBSS_CTRL_0_FB_GNDSW_OVERRIDE_SHIFT 0x01 + +/* WCD_USBSS_CTRL_1 Fields: */ +#define WCD_USBSS_CTRL_1_VOUT_PROG_SHIFT 0x04 +#define WCD_USBSS_CTRL_1_VOUT_CAL_SHIFT 0x00 + + +/* WCD_USBSS_DC_TRIMCODE_1 Fields: */ +#define WCD_USBSS_DC_TRIMCODE_1_AUDSW_R_OFFSET_TRIM_4_2_SHIFT 0x05 +#define WCD_USBSS_DC_TRIMCODE_1_AUDSW_L_OFFSET_TRIM_4_0_SHIFT 0x00 + +/* WCD_USBSS_DC_TRIMCODE_2 Fields: */ +#define WCD_USBSS_DC_TRIMCODE_2_SPARE_SHIFT 0x07 +#define WCD_USBSS_DC_TRIMCODE_2_GNDSW_L_OFFSET_TRIM_4_0_SHIFT 0x02 +#define WCD_USBSS_DC_TRIMCODE_2_AUDSW_R_OFFSET_TRIM_1_0_SHIFT 0x00 + +/* WCD_USBSS_DC_TRIMCODE_3 Fields: */ +#define WCD_USBSS_DC_TRIMCODE_3_SPARE_SHIFT 0x07 +#define WCD_USBSS_DC_TRIMCODE_3_AUDSW_R_GAIN_TRIM_1_0_SHIFT 0x05 +#define WCD_USBSS_DC_TRIMCODE_3_GNDSW_R_OFFSET_TRIM_4_0_SHIFT 0x00 + +/* WCD_USBSS_AC_TRIMCODE_1 Fields: */ +#define WCD_USBSS_AC_TRIMCODE_1_AUDSW_R_GAIN_TRIM_4_2_SHIFT 0x05 +#define WCD_USBSS_AC_TRIMCODE_1_AUDSW_L_GAIN_TRIM_4_0_SHIFT 0x00 + +/* WCD_USBSS_AC_TRIMCODE_2 Fields: */ +#define WCD_USBSS_AC_TRIMCODE_2_GNDSW_R_GAIN_TRIM_3_0_SHIFT 0x05 +#define WCD_USBSS_AC_TRIMCODE_2_GNDSW_L_GAIN_TRIM_3_0_SHIFT 0x00 + + +/* WCD_USBSS_CPLDO_CTL1 Fields: */ +#define WCD_USBSS_CPLDO_CTL1_CPLDO_EN_SHIFT 0x07 +#define WCD_USBSS_CPLDO_CTL1_CPLDO_TOP_EN_OVRRD_SHIFT 0x06 +#define WCD_USBSS_CPLDO_CTL1_BYPASS_EN_OVERRIDE_SHIFT 0x05 +#define WCD_USBSS_CPLDO_CTL1_LDO_TUNE_SHIFT 0x03 +#define WCD_USBSS_CPLDO_CTL1_LDO_IQ_INC_SHIFT 0x02 +#define WCD_USBSS_CPLDO_CTL1_SPARE_BITS_2_0_SHIFT 0x00 + +/* WCD_USBSS_CPLDO_CTL2 Fields: */ +#define WCD_USBSS_CPLDO_CTL2_SPARE_BITS_7_0_SHIFT 0x00 + + +/* WCD_USBSS_LUT_REG0 Fields: */ +#define WCD_USBSS_LUT_REG0_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG1 Fields: */ +#define WCD_USBSS_LUT_REG1_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG2 Fields: */ +#define WCD_USBSS_LUT_REG2_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG3 Fields: */ +#define WCD_USBSS_LUT_REG3_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG4 Fields: */ +#define WCD_USBSS_LUT_REG4_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG5 Fields: */ +#define WCD_USBSS_LUT_REG5_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG6 Fields: */ +#define WCD_USBSS_LUT_REG6_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG7 Fields: */ +#define WCD_USBSS_LUT_REG7_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG8 Fields: */ +#define WCD_USBSS_LUT_REG8_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG9 Fields: */ +#define WCD_USBSS_LUT_REG9_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG10 Fields: */ +#define WCD_USBSS_LUT_REG10_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG11 Fields: */ +#define WCD_USBSS_LUT_REG11_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG12 Fields: */ +#define WCD_USBSS_LUT_REG12_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG13 Fields: */ +#define WCD_USBSS_LUT_REG13_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG14 Fields: */ +#define WCD_USBSS_LUT_REG14_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG15 Fields: */ +#define WCD_USBSS_LUT_REG15_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG16 Fields: */ +#define WCD_USBSS_LUT_REG16_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG17 Fields: */ +#define WCD_USBSS_LUT_REG17_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG18 Fields: */ +#define WCD_USBSS_LUT_REG18_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG19 Fields: */ +#define WCD_USBSS_LUT_REG19_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG20 Fields: */ +#define WCD_USBSS_LUT_REG20_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG21 Fields: */ +#define WCD_USBSS_LUT_REG21_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG22 Fields: */ +#define WCD_USBSS_LUT_REG22_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG23 Fields: */ +#define WCD_USBSS_LUT_REG23_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG24 Fields: */ +#define WCD_USBSS_LUT_REG24_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG25 Fields: */ +#define WCD_USBSS_LUT_REG25_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG26 Fields: */ +#define WCD_USBSS_LUT_REG26_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG27 Fields: */ +#define WCD_USBSS_LUT_REG27_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG28 Fields: */ +#define WCD_USBSS_LUT_REG28_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG29 Fields: */ +#define WCD_USBSS_LUT_REG29_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG30 Fields: */ +#define WCD_USBSS_LUT_REG30_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG31 Fields: */ +#define WCD_USBSS_LUT_REG31_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG32 Fields: */ +#define WCD_USBSS_LUT_REG32_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG33 Fields: */ +#define WCD_USBSS_LUT_REG33_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG34 Fields: */ +#define WCD_USBSS_LUT_REG34_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG35 Fields: */ +#define WCD_USBSS_LUT_REG35_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG36 Fields: */ +#define WCD_USBSS_LUT_REG36_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG37 Fields: */ +#define WCD_USBSS_LUT_REG37_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG38 Fields: */ +#define WCD_USBSS_LUT_REG38_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG39 Fields: */ +#define WCD_USBSS_LUT_REG39_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG40 Fields: */ +#define WCD_USBSS_LUT_REG40_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG41 Fields: */ +#define WCD_USBSS_LUT_REG41_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG42 Fields: */ +#define WCD_USBSS_LUT_REG42_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG43 Fields: */ +#define WCD_USBSS_LUT_REG43_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG44 Fields: */ +#define WCD_USBSS_LUT_REG44_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG45 Fields: */ +#define WCD_USBSS_LUT_REG45_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG46 Fields: */ +#define WCD_USBSS_LUT_REG46_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG47 Fields: */ +#define WCD_USBSS_LUT_REG47_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG48 Fields: */ +#define WCD_USBSS_LUT_REG48_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG49 Fields: */ +#define WCD_USBSS_LUT_REG49_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG50 Fields: */ +#define WCD_USBSS_LUT_REG50_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG51 Fields: */ +#define WCD_USBSS_LUT_REG51_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG52 Fields: */ +#define WCD_USBSS_LUT_REG52_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG53 Fields: */ +#define WCD_USBSS_LUT_REG53_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG54 Fields: */ +#define WCD_USBSS_LUT_REG54_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG55 Fields: */ +#define WCD_USBSS_LUT_REG55_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG56 Fields: */ +#define WCD_USBSS_LUT_REG56_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG57 Fields: */ +#define WCD_USBSS_LUT_REG57_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG58 Fields: */ +#define WCD_USBSS_LUT_REG58_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG59 Fields: */ +#define WCD_USBSS_LUT_REG59_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG60 Fields: */ +#define WCD_USBSS_LUT_REG60_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG61 Fields: */ +#define WCD_USBSS_LUT_REG61_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG62 Fields: */ +#define WCD_USBSS_LUT_REG62_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG63 Fields: */ +#define WCD_USBSS_LUT_REG63_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG64 Fields: */ +#define WCD_USBSS_LUT_REG64_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG65 Fields: */ +#define WCD_USBSS_LUT_REG65_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG66 Fields: */ +#define WCD_USBSS_LUT_REG66_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG67 Fields: */ +#define WCD_USBSS_LUT_REG67_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG68 Fields: */ +#define WCD_USBSS_LUT_REG68_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG69 Fields: */ +#define WCD_USBSS_LUT_REG69_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG70 Fields: */ +#define WCD_USBSS_LUT_REG70_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG71 Fields: */ +#define WCD_USBSS_LUT_REG71_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG72 Fields: */ +#define WCD_USBSS_LUT_REG72_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG73 Fields: */ +#define WCD_USBSS_LUT_REG73_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG74 Fields: */ +#define WCD_USBSS_LUT_REG74_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG75 Fields: */ +#define WCD_USBSS_LUT_REG75_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG76 Fields: */ +#define WCD_USBSS_LUT_REG76_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG77 Fields: */ +#define WCD_USBSS_LUT_REG77_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG78 Fields: */ +#define WCD_USBSS_LUT_REG78_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG79 Fields: */ +#define WCD_USBSS_LUT_REG79_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG80 Fields: */ +#define WCD_USBSS_LUT_REG80_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG81 Fields: */ +#define WCD_USBSS_LUT_REG81_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG82 Fields: */ +#define WCD_USBSS_LUT_REG82_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG83 Fields: */ +#define WCD_USBSS_LUT_REG83_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG84 Fields: */ +#define WCD_USBSS_LUT_REG84_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG85 Fields: */ +#define WCD_USBSS_LUT_REG85_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG86 Fields: */ +#define WCD_USBSS_LUT_REG86_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG87 Fields: */ +#define WCD_USBSS_LUT_REG87_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG88 Fields: */ +#define WCD_USBSS_LUT_REG88_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG89 Fields: */ +#define WCD_USBSS_LUT_REG89_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG90 Fields: */ +#define WCD_USBSS_LUT_REG90_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG91 Fields: */ +#define WCD_USBSS_LUT_REG91_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG92 Fields: */ +#define WCD_USBSS_LUT_REG92_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG93 Fields: */ +#define WCD_USBSS_LUT_REG93_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG94 Fields: */ +#define WCD_USBSS_LUT_REG94_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG95 Fields: */ +#define WCD_USBSS_LUT_REG95_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG96 Fields: */ +#define WCD_USBSS_LUT_REG96_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG97 Fields: */ +#define WCD_USBSS_LUT_REG97_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG98 Fields: */ +#define WCD_USBSS_LUT_REG98_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG99 Fields: */ +#define WCD_USBSS_LUT_REG99_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG100 Fields: */ +#define WCD_USBSS_LUT_REG100_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG101 Fields: */ +#define WCD_USBSS_LUT_REG101_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG102 Fields: */ +#define WCD_USBSS_LUT_REG102_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG103 Fields: */ +#define WCD_USBSS_LUT_REG103_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG104 Fields: */ +#define WCD_USBSS_LUT_REG104_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG105 Fields: */ +#define WCD_USBSS_LUT_REG105_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG106 Fields: */ +#define WCD_USBSS_LUT_REG106_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG107 Fields: */ +#define WCD_USBSS_LUT_REG107_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG108 Fields: */ +#define WCD_USBSS_LUT_REG108_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG109 Fields: */ +#define WCD_USBSS_LUT_REG109_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG110 Fields: */ +#define WCD_USBSS_LUT_REG110_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG111 Fields: */ +#define WCD_USBSS_LUT_REG111_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG112 Fields: */ +#define WCD_USBSS_LUT_REG112_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG113 Fields: */ +#define WCD_USBSS_LUT_REG113_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG114 Fields: */ +#define WCD_USBSS_LUT_REG114_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG115 Fields: */ +#define WCD_USBSS_LUT_REG115_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG116 Fields: */ +#define WCD_USBSS_LUT_REG116_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG117 Fields: */ +#define WCD_USBSS_LUT_REG117_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG118 Fields: */ +#define WCD_USBSS_LUT_REG118_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG119 Fields: */ +#define WCD_USBSS_LUT_REG119_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG120 Fields: */ +#define WCD_USBSS_LUT_REG120_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG121 Fields: */ +#define WCD_USBSS_LUT_REG121_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG122 Fields: */ +#define WCD_USBSS_LUT_REG122_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG123 Fields: */ +#define WCD_USBSS_LUT_REG123_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG124 Fields: */ +#define WCD_USBSS_LUT_REG124_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG125 Fields: */ +#define WCD_USBSS_LUT_REG125_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG126 Fields: */ +#define WCD_USBSS_LUT_REG126_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG127 Fields: */ +#define WCD_USBSS_LUT_REG127_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG128 Fields: */ +#define WCD_USBSS_LUT_REG128_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG129 Fields: */ +#define WCD_USBSS_LUT_REG129_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG130 Fields: */ +#define WCD_USBSS_LUT_REG130_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG131 Fields: */ +#define WCD_USBSS_LUT_REG131_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG132 Fields: */ +#define WCD_USBSS_LUT_REG132_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG133 Fields: */ +#define WCD_USBSS_LUT_REG133_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG134 Fields: */ +#define WCD_USBSS_LUT_REG134_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG135 Fields: */ +#define WCD_USBSS_LUT_REG135_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG136 Fields: */ +#define WCD_USBSS_LUT_REG136_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG137 Fields: */ +#define WCD_USBSS_LUT_REG137_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG138 Fields: */ +#define WCD_USBSS_LUT_REG138_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG139 Fields: */ +#define WCD_USBSS_LUT_REG139_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG140 Fields: */ +#define WCD_USBSS_LUT_REG140_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG141 Fields: */ +#define WCD_USBSS_LUT_REG141_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG142 Fields: */ +#define WCD_USBSS_LUT_REG142_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG143 Fields: */ +#define WCD_USBSS_LUT_REG143_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG144 Fields: */ +#define WCD_USBSS_LUT_REG144_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG145 Fields: */ +#define WCD_USBSS_LUT_REG145_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG146 Fields: */ +#define WCD_USBSS_LUT_REG146_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG147 Fields: */ +#define WCD_USBSS_LUT_REG147_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG148 Fields: */ +#define WCD_USBSS_LUT_REG148_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG149 Fields: */ +#define WCD_USBSS_LUT_REG149_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG150 Fields: */ +#define WCD_USBSS_LUT_REG150_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG151 Fields: */ +#define WCD_USBSS_LUT_REG151_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG152 Fields: */ +#define WCD_USBSS_LUT_REG152_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG153 Fields: */ +#define WCD_USBSS_LUT_REG153_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG154 Fields: */ +#define WCD_USBSS_LUT_REG154_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG155 Fields: */ +#define WCD_USBSS_LUT_REG155_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG156 Fields: */ +#define WCD_USBSS_LUT_REG156_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG157 Fields: */ +#define WCD_USBSS_LUT_REG157_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG158 Fields: */ +#define WCD_USBSS_LUT_REG158_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG159 Fields: */ +#define WCD_USBSS_LUT_REG159_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG160 Fields: */ +#define WCD_USBSS_LUT_REG160_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG161 Fields: */ +#define WCD_USBSS_LUT_REG161_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG162 Fields: */ +#define WCD_USBSS_LUT_REG162_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG163 Fields: */ +#define WCD_USBSS_LUT_REG163_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG164 Fields: */ +#define WCD_USBSS_LUT_REG164_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG165 Fields: */ +#define WCD_USBSS_LUT_REG165_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG166 Fields: */ +#define WCD_USBSS_LUT_REG166_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG167 Fields: */ +#define WCD_USBSS_LUT_REG167_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG168 Fields: */ +#define WCD_USBSS_LUT_REG168_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG169 Fields: */ +#define WCD_USBSS_LUT_REG169_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG170 Fields: */ +#define WCD_USBSS_LUT_REG170_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG171 Fields: */ +#define WCD_USBSS_LUT_REG171_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG172 Fields: */ +#define WCD_USBSS_LUT_REG172_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG173 Fields: */ +#define WCD_USBSS_LUT_REG173_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG174 Fields: */ +#define WCD_USBSS_LUT_REG174_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG175 Fields: */ +#define WCD_USBSS_LUT_REG175_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG176 Fields: */ +#define WCD_USBSS_LUT_REG176_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG177 Fields: */ +#define WCD_USBSS_LUT_REG177_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG178 Fields: */ +#define WCD_USBSS_LUT_REG178_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG179 Fields: */ +#define WCD_USBSS_LUT_REG179_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG180 Fields: */ +#define WCD_USBSS_LUT_REG180_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG181 Fields: */ +#define WCD_USBSS_LUT_REG181_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG182 Fields: */ +#define WCD_USBSS_LUT_REG182_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG183 Fields: */ +#define WCD_USBSS_LUT_REG183_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG184 Fields: */ +#define WCD_USBSS_LUT_REG184_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG185 Fields: */ +#define WCD_USBSS_LUT_REG185_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG186 Fields: */ +#define WCD_USBSS_LUT_REG186_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG187 Fields: */ +#define WCD_USBSS_LUT_REG187_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG188 Fields: */ +#define WCD_USBSS_LUT_REG188_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG189 Fields: */ +#define WCD_USBSS_LUT_REG189_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG190 Fields: */ +#define WCD_USBSS_LUT_REG190_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG191 Fields: */ +#define WCD_USBSS_LUT_REG191_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG192 Fields: */ +#define WCD_USBSS_LUT_REG192_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG193 Fields: */ +#define WCD_USBSS_LUT_REG193_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG194 Fields: */ +#define WCD_USBSS_LUT_REG194_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG195 Fields: */ +#define WCD_USBSS_LUT_REG195_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG196 Fields: */ +#define WCD_USBSS_LUT_REG196_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG197 Fields: */ +#define WCD_USBSS_LUT_REG197_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG198 Fields: */ +#define WCD_USBSS_LUT_REG198_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG199 Fields: */ +#define WCD_USBSS_LUT_REG199_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG200 Fields: */ +#define WCD_USBSS_LUT_REG200_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG201 Fields: */ +#define WCD_USBSS_LUT_REG201_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG202 Fields: */ +#define WCD_USBSS_LUT_REG202_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG203 Fields: */ +#define WCD_USBSS_LUT_REG203_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG204 Fields: */ +#define WCD_USBSS_LUT_REG204_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG205 Fields: */ +#define WCD_USBSS_LUT_REG205_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG206 Fields: */ +#define WCD_USBSS_LUT_REG206_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG207 Fields: */ +#define WCD_USBSS_LUT_REG207_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG208 Fields: */ +#define WCD_USBSS_LUT_REG208_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG209 Fields: */ +#define WCD_USBSS_LUT_REG209_REG_SHIFT 0x00 + +/* WCD_USBSS_LUT_REG210 Fields: */ +#define WCD_USBSS_LUT_REG210_REG_SHIFT 0x00 + +/* WCD_USBSS_DATA_SEL Fields: */ +#define WCD_USBSS_DATA_SEL_SEL3_SHIFT 0x04 +#define WCD_USBSS_DATA_SEL_SEL2_SHIFT 0x02 +#define WCD_USBSS_DATA_SEL_SEL1_SHIFT 0x01 +#define WCD_USBSS_DATA_SEL_SEL0_SHIFT 0x00 + +/* WCD_USBSS_OFF3 Fields: */ +#define WCD_USBSS_OFF3_REG_SHIFT 0x00 + +/* WCD_USBSS_OFF2_LSB Fields: */ +#define WCD_USBSS_OFF2_LSB_REG_SHIFT 0x00 + +/* WCD_USBSS_OFF2_MSB Fields: */ +#define WCD_USBSS_OFF2_MSB_REG_SHIFT 0x00 + +/* WCD_USBSS_OFF1_LSB Fields: */ +#define WCD_USBSS_OFF1_LSB_REG_SHIFT 0x00 + +/* WCD_USBSS_OFF1_MSB Fields: */ +#define WCD_USBSS_OFF1_MSB_REG_SHIFT 0x00 + +/* WCD_USBSS_AUD_L Fields: */ +#define WCD_USBSS_AUD_L_STATUS_SHIFT 0x00 + +/* WCD_USBSS_AUD_R Fields: */ +#define WCD_USBSS_AUD_R_STATUS_SHIFT 0x00 + +/* WCD_USBSS_GND_L Fields: */ +#define WCD_USBSS_GND_L_STATUS_SHIFT 0x00 + +/* WCD_USBSS_GND_R Fields: */ +#define WCD_USBSS_GND_R_STATUS_SHIFT 0x00 + + +/* WCD_USBSS_USB_DIG_PAGE Fields: */ +#define WCD_USBSS_USB_DIG_PAGE_PAGE_REG_SHIFT 0x00 + +/* WCD_USBSS_OVP_STATUS_SELF_CLEARING Fields: */ +#define WCD_USBSS_OVP_STATUS_SELF_CLEARING_OVP_DPR_SHIFT 0x07 +#define WCD_USBSS_OVP_STATUS_SELF_CLEARING_OVP_DNL_SHIFT 0x06 +#define WCD_USBSS_OVP_STATUS_SELF_CLEARING_OVP_MG1_SHIFT 0x05 +#define WCD_USBSS_OVP_STATUS_SELF_CLEARING_OVP_MG2_SHIFT 0x04 + +/* WCD_USBSS_OVP_STATUS Fields: */ +#define WCD_USBSS_OVP_STATUS_OVP_DPR_SHIFT 0x07 +#define WCD_USBSS_OVP_STATUS_OVP_DNL_SHIFT 0x06 +#define WCD_USBSS_OVP_STATUS_OVP_MG1_SHIFT 0x05 +#define WCD_USBSS_OVP_STATUS_OVP_MG2_SHIFT 0x04 + +/* WCD_USBSS_SWITCH_SETTINGS_ENABLE Fields: */ +#define WCD_USBSS_SWITCH_SETTINGS_ENABLE_DEVICE_ENABLE_SHIFT 0x07 +#define WCD_USBSS_SWITCH_SETTINGS_ENABLE_DP_AUXP_TO_MGX_SWITCHES_SHIFT 0x06 +#define WCD_USBSS_SWITCH_SETTINGS_ENABLE_DP_AUXM_TO_MGX_SWITCHES_SHIFT 0x05 +#define WCD_USBSS_SWITCH_SETTINGS_ENABLE_DNL_SWITCHES_SHIFT 0x04 +#define WCD_USBSS_SWITCH_SETTINGS_ENABLE_DPR_SWITCHES_SHIFT 0x03 +#define WCD_USBSS_SWITCH_SETTINGS_ENABLE_SENSE_SWITCHES_SHIFT 0x02 +#define WCD_USBSS_SWITCH_SETTINGS_ENABLE_MIC_SWITCHES_SHIFT 0x01 +#define WCD_USBSS_SWITCH_SETTINGS_ENABLE_AGND_SWITCHES_SHIFT 0x00 + +/* WCD_USBSS_SWITCH_SELECT0 Fields: */ +#define WCD_USBSS_SWITCH_SELECT0_DP_AUXP_SWITCHES_SHIFT 0x07 +#define WCD_USBSS_SWITCH_SELECT0_DP_AUXM_SWITCHES_SHIFT 0x06 +#define WCD_USBSS_SWITCH_SELECT0_DNL_SWITCHES_SHIFT 0x04 +#define WCD_USBSS_SWITCH_SELECT0_DPR_SWITCHES_SHIFT 0x02 +#define WCD_USBSS_SWITCH_SELECT0_SENSE_SWITCHES_SHIFT 0x01 +#define WCD_USBSS_SWITCH_SELECT0_MIC_SWITCHES_SHIFT 0x00 + +/* WCD_USBSS_SWITCH_SELECT1 Fields: */ +#define WCD_USBSS_SWITCH_SELECT1_AGND_SWITCHES_SHIFT 0x00 + +/* WCD_USBSS_SWITCH_STATUS0 Fields: */ +#define WCD_USBSS_SWITCH_STATUS0_SENSE_GSBU2_STATUS_SHIFT 0x07 +#define WCD_USBSS_SWITCH_STATUS0_SENSE_GSBU1_STATUS_SHIFT 0x06 +#define WCD_USBSS_SWITCH_STATUS0_L_DNL_STATUS_SHIFT 0x05 +#define WCD_USBSS_SWITCH_STATUS0_DN2_DNL_STATUS_SHIFT 0x04 +#define WCD_USBSS_SWITCH_STATUS0_DN_DNL_STATUS_SHIFT 0x03 +#define WCD_USBSS_SWITCH_STATUS0_R_DPR_STATUS_SHIFT 0x02 +#define WCD_USBSS_SWITCH_STATUS0_DP2_DPR_STATUS_SHIFT 0x01 +#define WCD_USBSS_SWITCH_STATUS0_DP_DPR_STATUS_SHIFT 0x00 + +/* WCD_USBSS_SWITCH_STATUS1 Fields: */ +#define WCD_USBSS_SWITCH_STATUS1_DPAUXP_MG2_STATUS_SHIFT 0x07 +#define WCD_USBSS_SWITCH_STATUS1_DPAUXM_MG2_STATUS_SHIFT 0x06 +#define WCD_USBSS_SWITCH_STATUS1_AGND_MG2_STATUS_SHIFT 0x05 +#define WCD_USBSS_SWITCH_STATUS1_MIC_MG2_STATUS_SHIFT 0x04 +#define WCD_USBSS_SWITCH_STATUS1_DPAUXP_MG1_STATUS_SHIFT 0x03 +#define WCD_USBSS_SWITCH_STATUS1_DPAUXM_MG1_STATUS_SHIFT 0x02 +#define WCD_USBSS_SWITCH_STATUS1_AGND_MG1_STATUS_SHIFT 0x01 +#define WCD_USBSS_SWITCH_STATUS1_MIC_MG1_STATUS_SHIFT 0x00 + +/* WCD_USBSS_AUD_LEFT_SW_SLOW Fields: */ +#define WCD_USBSS_AUD_LEFT_SW_SLOW_SWITCH_TURN_ON_RISE_TIME_SHIFT 0x00 + +/* WCD_USBSS_AUD_RIGHT_SW_SLOW Fields: */ +#define WCD_USBSS_AUD_RIGHT_SW_SLOW_SWITCH_TURN_ON_RISE_TIME_SHIFT 0x00 + +/* WCD_USBSS_AUD_MIC_SW_SLOW Fields: */ +#define WCD_USBSS_AUD_MIC_SW_SLOW_SWITCH_TURN_ON_RISE_TIME_SHIFT 0x00 + +/* WCD_USBSS_AUD_SENSE_SW_SLOW Fields: */ +#define WCD_USBSS_AUD_SENSE_SW_SLOW_SWITCH_TURN_ON_RISE_TIME_SHIFT 0x00 + +/* WCD_USBSS_AUD_GND_SW_SLOW Fields: */ +#define WCD_USBSS_AUD_GND_SW_SLOW_SWITCH_TURN_ON_RISE_TIME_SHIFT 0x00 + +/* WCD_USBSS_DELAY_R_SW Fields: */ +#define WCD_USBSS_DELAY_R_SW_DELAY_TIME_SHIFT 0x00 + +/* WCD_USBSS_DELAY_MIC_SW Fields: */ +#define WCD_USBSS_DELAY_MIC_SW_DELAY_TIME_SHIFT 0x00 + +/* WCD_USBSS_DELAY_SENSE_SW Fields: */ +#define WCD_USBSS_DELAY_SENSE_SW_DELAY_TIME_SHIFT 0x00 + +/* WCD_USBSS_DELAY_GND_SW Fields: */ +#define WCD_USBSS_DELAY_GND_SW_DELAY_TIME_SHIFT 0x00 + +/* WCD_USBSS_DELAY_L_SW Fields: */ +#define WCD_USBSS_DELAY_L_SW_DELAY_TIME_SHIFT 0x00 + +/* WCD_USBSS_EXT_FET_ENABLE_DELAY Fields: */ +#define WCD_USBSS_EXT_FET_ENABLE_DELAY_DELAY_TIME_SHIFT 0x00 + +/* WCD_USBSS_FUNCTION_ENABLE Fields: */ +#define WCD_USBSS_FUNCTION_ENABLE_SEL_CSR_SLEEP_BG_PROG_SHIFT 0x07 +#define WCD_USBSS_FUNCTION_ENABLE_PER_PIN_OVP_ENABLE_SHIFT 0x06 +#define WCD_USBSS_FUNCTION_ENABLE_SW_OVP_ENABLE_SHIFT 0x05 +#define WCD_USBSS_FUNCTION_ENABLE_SW_CONNECTION_DISABLE_SHIFT 0x04 +#define WCD_USBSS_FUNCTION_ENABLE_SLOW_TURN_ON_ENABLE_SHIFT 0x03 +#define WCD_USBSS_FUNCTION_ENABLE_RDAC_CAL_CODE_SELECT_SHIFT 0x02 +#define WCD_USBSS_FUNCTION_ENABLE_SWITCH_SOURCE_SELECT_SHIFT 0x00 + +/* WCD_USBSS_USB_RST_CTL Fields: */ +#define WCD_USBSS_USB_RST_CTL_USB_ANA_SW_RST_N_SHIFT 0x01 +#define WCD_USBSS_USB_RST_CTL_USB_DIG_SW_RST_N_SHIFT 0x00 + +/* WCD_USBSS_EQUALIZER1 Fields: */ +#define WCD_USBSS_EQUALIZER1_EQ_EN_SHIFT 0x07 +#define WCD_USBSS_EQUALIZER1_BW_SETTINGS_SHIFT 0x03 + +/* WCD_USBSS_SPARE_0 Fields: */ +#define WCD_USBSS_SPARE_0_SPARE_BITS_SHIFT 0x00 + +/* WCD_USBSS_DIG_FUNCTIONS_STATUS Fields: */ +#define WCD_USBSS_DIG_FUNCTIONS_STATUS_EQ_ENABLE_STATUS_SHIFT 0x06 +#define WCD_USBSS_DIG_FUNCTIONS_STATUS_OVP_DNL_ENABLE_STATUS_SHIFT 0x05 +#define WCD_USBSS_DIG_FUNCTIONS_STATUS_OVP_DPR_ENABLE_STATUS_SHIFT 0x04 +#define WCD_USBSS_DIG_FUNCTIONS_STATUS_OVP_MG12_ENABLE_STATUS_SHIFT 0x03 +#define WCD_USBSS_DIG_FUNCTIONS_STATUS_EXTFET_DNL_ENABLE_STATUS_SHIFT 0x02 +#define WCD_USBSS_DIG_FUNCTIONS_STATUS_EXTFET_DPR_ENABLE_STATUS_SHIFT 0x01 +#define WCD_USBSS_DIG_FUNCTIONS_STATUS_EXTFET_MG12_ENABLE_STATUS_SHIFT 0x00 + +/* WCD_USBSS_CLK_SOURCE Fields: */ +#define WCD_USBSS_CLK_SOURCE_CP_CLK_SEL_SHIFT 0x06 +#define WCD_USBSS_CLK_SOURCE_FSM_CLK_SEL_SHIFT 0x05 + +/* WCD_USBSS_USB_SS_CNTL Fields: */ +#define WCD_USBSS_USB_SS_CNTL_STANDBY_STATE_SHIFT 0x04 +#define WCD_USBSS_USB_SS_CNTL_RCO_EN_SHIFT 0x03 +#define WCD_USBSS_USB_SS_CNTL_USB_SS_MODE_SHIFT 0x00 + +/* WCD_USBSS_SPARE_1 Fields: */ +#define WCD_USBSS_SPARE_1_SPARE_BITS_SHIFT 0x00 + +/* WCD_USBSS_ANA_FUNCTIONS_STATUS Fields: */ +#define WCD_USBSS_ANA_FUNCTIONS_STATUS_CP_READY_SHIFT 0x07 + +/* WCD_USBSS_FSM_STATUS Fields: */ +#define WCD_USBSS_FSM_STATUS_LINEARIZER_FSM_DONE_SHIFT 0x01 +#define WCD_USBSS_FSM_STATUS_SWITCH_FSM_DONE_SHIFT 0x00 + +/* WCD_USBSS_SPARE_14 Fields: */ +#define WCD_USBSS_SPARE_14_SPARE_BITS_SHIFT 0x00 + +/* WCD_USBSS_SAFE_STATE_PD_DPAUX Fields: */ +#define WCD_USBSS_SAFE_STATE_PD_DPAUX_DP_SBU1_SAFE_STATE_PD_SHIFT 0x02 +#define WCD_USBSS_SAFE_STATE_PD_DPAUX_DP_SBU2_SAFE_STATE_PD_SHIFT 0x00 + +/* WCD_USBSS_AUDIO_FSM_START Fields: */ +#define WCD_USBSS_AUDIO_FSM_START_AUDIO_FSM_AUDIO_TRIG_SHIFT 0x00 + +/* WCD_USBSS_FSM_RESET Fields: */ +#define WCD_USBSS_FSM_RESET_AUDIO_FSM_LIN_RESET_SHIFT 0x01 +#define WCD_USBSS_FSM_RESET_AUDIO_FSM_SWITCH_RESET_SHIFT 0x00 + +/* WCD_USBSS_CHIP_ID0 Fields: */ +#define WCD_USBSS_CHIP_ID0_BYTE_0_SHIFT 0x00 + +/* WCD_USBSS_CHIP_ID1 Fields: */ +#define WCD_USBSS_CHIP_ID1_BYTE_1_SHIFT 0x00 + +/* WCD_USBSS_CHIP_ID2 Fields: */ +#define WCD_USBSS_CHIP_ID2_BYTE_2_SHIFT 0x00 + +/* WCD_USBSS_CHIP_ID3 Fields: */ +#define WCD_USBSS_CHIP_ID3_BYTE_3_SHIFT 0x00 + +/* WCD_USBSS_LINEARIZER_CFG Fields: */ +#define WCD_USBSS_LINEARIZER_CFG_COEF_CFG_SEL_SHIFT 0x00 + +/* WCD_USBSS_RATIO_SPKR_REXT_L_LSB Fields: */ +#define WCD_USBSS_RATIO_SPKR_REXT_L_LSB_RATIO_L_LSB_SHIFT 0x00 + +/* WCD_USBSS_RATIO_SPKR_REXT_L_MSB Fields: */ +#define WCD_USBSS_RATIO_SPKR_REXT_L_MSB_RATIO_L_MSB_SHIFT 0x00 + +/* WCD_USBSS_RATIO_SPKR_REXT_R_LSB Fields: */ +#define WCD_USBSS_RATIO_SPKR_REXT_R_LSB_RATIO_R_LSB_SHIFT 0x00 + +/* WCD_USBSS_RATIO_SPKR_REXT_R_MSB Fields: */ +#define WCD_USBSS_RATIO_SPKR_REXT_R_MSB_RATIO_R_MSB_SHIFT 0x00 + +/* WCD_USBSS_SW_TAP_AUD_L_LSB Fields: */ +#define WCD_USBSS_SW_TAP_AUD_L_LSB_TCAL1_SW_LEFT_LSB_SHIFT 0x00 + +/* WCD_USBSS_SW_TAP_AUD_L_MSB Fields: */ +#define WCD_USBSS_SW_TAP_AUD_L_MSB_TCAL1_SW_LEFT_MSB_SHIFT 0x00 + +/* WCD_USBSS_SW_TAP_AUD_R_LSB Fields: */ +#define WCD_USBSS_SW_TAP_AUD_R_LSB_TCAL2_SW_RIGHT_LSB_SHIFT 0x00 + +/* WCD_USBSS_SW_TAP_AUD_R_MSB Fields: */ +#define WCD_USBSS_SW_TAP_AUD_R_MSB_TCAL2_SW_RIGHT_MSB_SHIFT 0x00 + +/* WCD_USBSS_SW_TAP_GND_L_LSB Fields: */ +#define WCD_USBSS_SW_TAP_GND_L_LSB_TCAL3_SW_GND1_LSB_SHIFT 0x00 + +/* WCD_USBSS_SW_TAP_GND_L_MSB Fields: */ +#define WCD_USBSS_SW_TAP_GND_L_MSB_TCAL3_SW_GND1_MSB_SHIFT 0x00 + +/* WCD_USBSS_SW_TAP_GND_R_LSB Fields: */ +#define WCD_USBSS_SW_TAP_GND_R_LSB_TCAL4_SW_GND2_LSB_SHIFT 0x00 + +/* WCD_USBSS_SW_TAP_GND_R_MSB Fields: */ +#define WCD_USBSS_SW_TAP_GND_R_MSB_TCAL4_SW_GND2_MSB_SHIFT 0x00 + +/* WCD_USBSS_HW_TAP_AUD_L_LSB Fields: */ +#define WCD_USBSS_HW_TAP_AUD_L_LSB_TCAL1_HW_LEFT_LSB_SHIFT 0x00 + +/* WCD_USBSS_HW_TAP_AUD_L_MSB Fields: */ +#define WCD_USBSS_HW_TAP_AUD_L_MSB_TCAL1_HW_LEFT_MSB_SHIFT 0x00 + +/* WCD_USBSS_HW_TAP_AUD_R_LSB Fields: */ +#define WCD_USBSS_HW_TAP_AUD_R_LSB_TCAL2_HW_RIGHT_LSB_SHIFT 0x00 + +/* WCD_USBSS_HW_TAP_AUD_R_MSB Fields: */ +#define WCD_USBSS_HW_TAP_AUD_R_MSB_TCAL2_HW_RIGHT_MSB_SHIFT 0x00 + +/* WCD_USBSS_HW_TAP_GND_L_LSB Fields: */ +#define WCD_USBSS_HW_TAP_GND_L_LSB_TCAL3_HW_GND1_LSB_SHIFT 0x00 + +/* WCD_USBSS_HW_TAP_GND_L_MSB Fields: */ +#define WCD_USBSS_HW_TAP_GND_L_MSB_TCAL3_HW_GND1_MSB_SHIFT 0x00 + +/* WCD_USBSS_HW_TAP_GND_R_LSB Fields: */ +#define WCD_USBSS_HW_TAP_GND_R_LSB_TCAL4_HW_GND2_LSB_SHIFT 0x00 + +/* WCD_USBSS_HW_TAP_GND_R_MSB Fields: */ +#define WCD_USBSS_HW_TAP_GND_R_MSB_TCAL4_HW_GND2_MSB_SHIFT 0x00 + +/* WCD_USBSS_AUD_COEF_L_K0_0 Fields: */ +#define WCD_USBSS_AUD_COEF_L_K0_0_K0_0_SHIFT 0x00 + +/* WCD_USBSS_AUD_COEF_L_K0_1 Fields: */ +#define WCD_USBSS_AUD_COEF_L_K0_1_K0_1_SHIFT 0x00 + +/* WCD_USBSS_AUD_COEF_L_K0_2 Fields: */ +#define WCD_USBSS_AUD_COEF_L_K0_2_K0_2_SHIFT 0x00 + +/* WCD_USBSS_AUD_COEF_L_K1_0 Fields: */ +#define WCD_USBSS_AUD_COEF_L_K1_0_K1_0_SHIFT 0x00 + +/* WCD_USBSS_AUD_COEF_L_K1_1 Fields: */ +#define WCD_USBSS_AUD_COEF_L_K1_1_K1_1_SHIFT 0x00 + +/* WCD_USBSS_AUD_COEF_L_K2_0 Fields: */ +#define WCD_USBSS_AUD_COEF_L_K2_0_K2_0_SHIFT 0x00 + +/* WCD_USBSS_AUD_COEF_L_K2_1 Fields: */ +#define WCD_USBSS_AUD_COEF_L_K2_1_K2_1_SHIFT 0x00 + +/* WCD_USBSS_AUD_COEF_L_K3_0 Fields: */ +#define WCD_USBSS_AUD_COEF_L_K3_0_K3_0_SHIFT 0x00 + +/* WCD_USBSS_AUD_COEF_L_K3_1 Fields: */ +#define WCD_USBSS_AUD_COEF_L_K3_1_K3_1_SHIFT 0x00 + +/* WCD_USBSS_AUD_COEF_L_K4_0 Fields: */ +#define WCD_USBSS_AUD_COEF_L_K4_0_K4_0_SHIFT 0x00 + +/* WCD_USBSS_AUD_COEF_L_K4_1 Fields: */ +#define WCD_USBSS_AUD_COEF_L_K4_1_K4_1_SHIFT 0x00 + +/* WCD_USBSS_AUD_COEF_L_K5_0 Fields: */ +#define WCD_USBSS_AUD_COEF_L_K5_0_K5_0_SHIFT 0x00 + +/* WCD_USBSS_AUD_COEF_L_K5_1 Fields: */ +#define WCD_USBSS_AUD_COEF_L_K5_1_K5_1_SHIFT 0x00 + +/* WCD_USBSS_AUD_COEF_R_K0_0 Fields: */ +#define WCD_USBSS_AUD_COEF_R_K0_0_K0_0_SHIFT 0x00 + +/* WCD_USBSS_AUD_COEF_R_K0_1 Fields: */ +#define WCD_USBSS_AUD_COEF_R_K0_1_K0_1_SHIFT 0x00 + +/* WCD_USBSS_AUD_COEF_R_K0_2 Fields: */ +#define WCD_USBSS_AUD_COEF_R_K0_2_K0_2_SHIFT 0x00 + +/* WCD_USBSS_AUD_COEF_R_K1_0 Fields: */ +#define WCD_USBSS_AUD_COEF_R_K1_0_K1_0_SHIFT 0x00 + +/* WCD_USBSS_AUD_COEF_R_K1_1 Fields: */ +#define WCD_USBSS_AUD_COEF_R_K1_1_K1_1_SHIFT 0x00 + +/* WCD_USBSS_AUD_COEF_R_K2_0 Fields: */ +#define WCD_USBSS_AUD_COEF_R_K2_0_K2_0_SHIFT 0x00 + +/* WCD_USBSS_AUD_COEF_R_K2_1 Fields: */ +#define WCD_USBSS_AUD_COEF_R_K2_1_K2_1_SHIFT 0x00 + +/* WCD_USBSS_AUD_COEF_R_K3_0 Fields: */ +#define WCD_USBSS_AUD_COEF_R_K3_0_K3_0_SHIFT 0x00 + +/* WCD_USBSS_AUD_COEF_R_K3_1 Fields: */ +#define WCD_USBSS_AUD_COEF_R_K3_1_K3_1_SHIFT 0x00 + +/* WCD_USBSS_AUD_COEF_R_K4_0 Fields: */ +#define WCD_USBSS_AUD_COEF_R_K4_0_K4_0_SHIFT 0x00 + +/* WCD_USBSS_AUD_COEF_R_K4_1 Fields: */ +#define WCD_USBSS_AUD_COEF_R_K4_1_K4_1_SHIFT 0x00 + +/* WCD_USBSS_AUD_COEF_R_K5_0 Fields: */ +#define WCD_USBSS_AUD_COEF_R_K5_0_K5_0_SHIFT 0x00 + +/* WCD_USBSS_AUD_COEF_R_K5_1 Fields: */ +#define WCD_USBSS_AUD_COEF_R_K5_1_K5_1_SHIFT 0x00 + +/* WCD_USBSS_GND_COEF_L_K0_0 Fields: */ +#define WCD_USBSS_GND_COEF_L_K0_0_K0_0_SHIFT 0x00 + +/* WCD_USBSS_GND_COEF_L_K0_1 Fields: */ +#define WCD_USBSS_GND_COEF_L_K0_1_K0_1_SHIFT 0x00 + +/* WCD_USBSS_GND_COEF_L_K0_2 Fields: */ +#define WCD_USBSS_GND_COEF_L_K0_2_K0_2_SHIFT 0x00 + +/* WCD_USBSS_GND_COEF_L_K1_0 Fields: */ +#define WCD_USBSS_GND_COEF_L_K1_0_K1_0_SHIFT 0x00 + +/* WCD_USBSS_GND_COEF_L_K1_1 Fields: */ +#define WCD_USBSS_GND_COEF_L_K1_1_K1_1_SHIFT 0x00 + +/* WCD_USBSS_GND_COEF_L_K2_0 Fields: */ +#define WCD_USBSS_GND_COEF_L_K2_0_K2_0_SHIFT 0x00 + +/* WCD_USBSS_GND_COEF_L_K2_1 Fields: */ +#define WCD_USBSS_GND_COEF_L_K2_1_K2_1_SHIFT 0x00 + +/* WCD_USBSS_GND_COEF_L_K3_0 Fields: */ +#define WCD_USBSS_GND_COEF_L_K3_0_K3_0_SHIFT 0x00 + +/* WCD_USBSS_GND_COEF_L_K3_1 Fields: */ +#define WCD_USBSS_GND_COEF_L_K3_1_K3_1_SHIFT 0x00 + +/* WCD_USBSS_GND_COEF_L_K4_0 Fields: */ +#define WCD_USBSS_GND_COEF_L_K4_0_K4_0_SHIFT 0x00 + +/* WCD_USBSS_GND_COEF_L_K4_1 Fields: */ +#define WCD_USBSS_GND_COEF_L_K4_1_K4_1_SHIFT 0x00 + +/* WCD_USBSS_GND_COEF_L_K5_0 Fields: */ +#define WCD_USBSS_GND_COEF_L_K5_0_K5_0_SHIFT 0x00 + +/* WCD_USBSS_GND_COEF_L_K5_1 Fields: */ +#define WCD_USBSS_GND_COEF_L_K5_1_K5_1_SHIFT 0x00 + +/* WCD_USBSS_GND_COEF_R_K0_0 Fields: */ +#define WCD_USBSS_GND_COEF_R_K0_0_K0_0_SHIFT 0x00 + +/* WCD_USBSS_GND_COEF_R_K0_1 Fields: */ +#define WCD_USBSS_GND_COEF_R_K0_1_K0_1_SHIFT 0x00 + +/* WCD_USBSS_GND_COEF_R_K0_2 Fields: */ +#define WCD_USBSS_GND_COEF_R_K0_2_K0_2_SHIFT 0x00 + +/* WCD_USBSS_GND_COEF_R_K1_0 Fields: */ +#define WCD_USBSS_GND_COEF_R_K1_0_K1_0_SHIFT 0x00 + +/* WCD_USBSS_GND_COEF_R_K1_1 Fields: */ +#define WCD_USBSS_GND_COEF_R_K1_1_K1_1_SHIFT 0x00 + +/* WCD_USBSS_GND_COEF_R_K2_0 Fields: */ +#define WCD_USBSS_GND_COEF_R_K2_0_K2_0_SHIFT 0x00 + +/* WCD_USBSS_GND_COEF_R_K2_1 Fields: */ +#define WCD_USBSS_GND_COEF_R_K2_1_K2_1_SHIFT 0x00 + +/* WCD_USBSS_GND_COEF_R_K3_0 Fields: */ +#define WCD_USBSS_GND_COEF_R_K3_0_K3_0_SHIFT 0x00 + +/* WCD_USBSS_GND_COEF_R_K3_1 Fields: */ +#define WCD_USBSS_GND_COEF_R_K3_1_K3_1_SHIFT 0x00 + +/* WCD_USBSS_GND_COEF_R_K4_0 Fields: */ +#define WCD_USBSS_GND_COEF_R_K4_0_K4_0_SHIFT 0x00 + +/* WCD_USBSS_GND_COEF_R_K4_1 Fields: */ +#define WCD_USBSS_GND_COEF_R_K4_1_K4_1_SHIFT 0x00 + +/* WCD_USBSS_GND_COEF_R_K5_0 Fields: */ +#define WCD_USBSS_GND_COEF_R_K5_0_K5_0_SHIFT 0x00 + +/* WCD_USBSS_GND_COEF_R_K5_1 Fields: */ +#define WCD_USBSS_GND_COEF_R_K5_1_K5_1_SHIFT 0x00 + +/* WCD_USBSS_AUD_L_SLOPE_SCALE_LSB Fields: */ +#define WCD_USBSS_AUD_L_SLOPE_SCALE_LSB_SLOPE_LSB_SHIFT 0x00 + +/* WCD_USBSS_AUD_L_SLOPE_SCALE_MSB Fields: */ +#define WCD_USBSS_AUD_L_SLOPE_SCALE_MSB_SLOPE_MSB_SHIFT 0x00 + +/* WCD_USBSS_AUD_R_SLOPE_SCALE_LSB Fields: */ +#define WCD_USBSS_AUD_R_SLOPE_SCALE_LSB_SLOPE_LSB_SHIFT 0x00 + +/* WCD_USBSS_AUD_R_SLOPE_SCALE_MSB Fields: */ +#define WCD_USBSS_AUD_R_SLOPE_SCALE_MSB_SLOPE_MSB_SHIFT 0x00 + +/* WCD_USBSS_GND_L_SLOPE_SCALE_LSB Fields: */ +#define WCD_USBSS_GND_L_SLOPE_SCALE_LSB_SLOPE_LSB_SHIFT 0x00 + +/* WCD_USBSS_GND_L_SLOPE_SCALE_MSB Fields: */ +#define WCD_USBSS_GND_L_SLOPE_SCALE_MSB_SLOPE_MSB_SHIFT 0x00 + +/* WCD_USBSS_GND_R_SLOPE_SCALE_LSB Fields: */ +#define WCD_USBSS_GND_R_SLOPE_SCALE_LSB_SLOPE_LSB_SHIFT 0x00 + +/* WCD_USBSS_GND_R_SLOPE_SCALE_MSB Fields: */ +#define WCD_USBSS_GND_R_SLOPE_SCALE_MSB_SLOPE_MSB_SHIFT 0x00 + +/* WCD_USBSS_AUD_L_FIRST_TAP Fields: */ +#define WCD_USBSS_AUD_L_FIRST_TAP_FIRST_TAP_SHIFT 0x00 + +/* WCD_USBSS_AUD_R_FIRST_TAP Fields: */ +#define WCD_USBSS_AUD_R_FIRST_TAP_FIRST_TAP_SHIFT 0x00 + +/* WCD_USBSS_GND_L_FIRST_TAP Fields: */ +#define WCD_USBSS_GND_L_FIRST_TAP_FIRST_TAP_SHIFT 0x00 + +/* WCD_USBSS_GND_R_FIRST_TAP Fields: */ +#define WCD_USBSS_GND_R_FIRST_TAP_FIRST_TAP_SHIFT 0x00 + +/* WCD_USBSS_FEATURE_SELECTION Fields: */ +#define WCD_USBSS_FEATURE_SELECTION_FEATURE_SEL_SHIFT 0x04 + +/* WCD_USBSS_EFUSE_REG_0 Fields: */ +#define WCD_USBSS_EFUSE_REG_0_EFUSE_MUX_SEL_SHIFT 0x05 +#define WCD_USBSS_EFUSE_REG_0_RCO_RATE_SHIFT 0x04 +#define WCD_USBSS_EFUSE_REG_0_LDOL_TRIM_SHIFT 0x00 + +/* WCD_USBSS_EFUSE_REG_1 Fields: */ +#define WCD_USBSS_EFUSE_REG_1_OVP_REFERENCE_TRIM_SHIFT 0x04 +#define WCD_USBSS_EFUSE_REG_1_CP_OUTPUT_TRIM_SHIFT 0x00 + +/* WCD_USBSS_EFUSE_REG_2 Fields: */ +#define WCD_USBSS_EFUSE_REG_2_EQ_ENABLE_SHIFT 0x06 + +/* WCD_USBSS_EFUSE_REG_3 Fields: */ +#define WCD_USBSS_EFUSE_REG_3_DPAUXP_MG1_SHIFT 0x07 +#define WCD_USBSS_EFUSE_REG_3_DPAUXP_MG2_SHIFT 0x06 +#define WCD_USBSS_EFUSE_REG_3_DPAUXM_MG1_SHIFT 0x05 +#define WCD_USBSS_EFUSE_REG_3_DPAUXM_MG2_SHIFT 0x04 +#define WCD_USBSS_EFUSE_REG_3_DNL_L_SHIFT 0x03 +#define WCD_USBSS_EFUSE_REG_3_DNL_DN_SHIFT 0x02 +#define WCD_USBSS_EFUSE_REG_3_DNL_DN2_SHIFT 0x01 +#define WCD_USBSS_EFUSE_REG_3_DPR_R_SHIFT 0x00 + +/* WCD_USBSS_EFUSE_REG_4 Fields: */ +#define WCD_USBSS_EFUSE_REG_4_DPR_DP_SHIFT 0x07 +#define WCD_USBSS_EFUSE_REG_4_DPR_DP2_SHIFT 0x06 +#define WCD_USBSS_EFUSE_REG_4_SENSE_GSBU1_SHIFT 0x05 +#define WCD_USBSS_EFUSE_REG_4_SENSE_GSBU2_SHIFT 0x04 +#define WCD_USBSS_EFUSE_REG_4_MIC_MG1_SHIFT 0x03 +#define WCD_USBSS_EFUSE_REG_4_MIC_MG2_SHIFT 0x02 +#define WCD_USBSS_EFUSE_REG_4_AGND_MG1_SHIFT 0x01 +#define WCD_USBSS_EFUSE_REG_4_AGND_MG2_SHIFT 0x00 + +/* WCD_USBSS_EFUSE_REG_5 Fields: */ +#define WCD_USBSS_EFUSE_REG_5_OVP_THRESHOLD_SHIFT 0x06 +#define WCD_USBSS_EFUSE_REG_5_EQ_SEG_SEL_SHIFT 0x04 +#define WCD_USBSS_EFUSE_REG_5_EQ_ENABLE_SHIFT 0x03 +#define WCD_USBSS_EFUSE_REG_5_CP_PFM_EN_SHIFT 0x02 +#define WCD_USBSS_EFUSE_REG_5_SPARE_BITS_SHIFT 0x00 + +/* WCD_USBSS_EFUSE_REG_6 Fields: */ +#define WCD_USBSS_EFUSE_REG_6_SPARE_BITS_SHIFT 0x00 + +/* WCD_USBSS_EFUSE_REG_7 Fields: */ +#define WCD_USBSS_EFUSE_REG_7_SPARE_BITS_SHIFT 0x03 +#define WCD_USBSS_EFUSE_REG_7_LDOL_TRIM_SHIFT 0x00 + +/* WCD_USBSS_EFUSE_REG_8 Fields: */ +#define WCD_USBSS_EFUSE_REG_8_GNDSW_L_GAIN_TRIM_SHIFT 0x04 +#define WCD_USBSS_EFUSE_REG_8_GNDSW_R_GAIN_TRIM_SHIFT 0x00 + +/* WCD_USBSS_EFUSE_REG_9 Fields: */ +#define WCD_USBSS_EFUSE_REG_9_AUDSW_L_GAIN_TRIM_SHIFT 0x00 + +/* WCD_USBSS_EFUSE_REG_10 Fields: */ +#define WCD_USBSS_EFUSE_REG_10_AUDSW_R_GAIN_TRIM_SHIFT 0x00 + +/* WCD_USBSS_EFUSE_REG_11 Fields: */ +#define WCD_USBSS_EFUSE_REG_11_SPARE_BITS_SHIFT 0x05 +#define WCD_USBSS_EFUSE_REG_11_GNDSW_L_OFFSET_TRIM_SHIFT 0x00 + +/* WCD_USBSS_EFUSE_REG_12 Fields: */ +#define WCD_USBSS_EFUSE_REG_12_SPARE_BITS_SHIFT 0x05 +#define WCD_USBSS_EFUSE_REG_12_GNDSW_R_OFFSET_TRIM_SHIFT 0x00 + +/* WCD_USBSS_EFUSE_REG_13 Fields: */ +#define WCD_USBSS_EFUSE_REG_13_SPARE_BITS_SHIFT 0x05 +#define WCD_USBSS_EFUSE_REG_13_AUDSW_L_OFFSET_TRIM_SHIFT 0x00 + +/* WCD_USBSS_EFUSE_REG_14 Fields: */ +#define WCD_USBSS_EFUSE_REG_14_SPARE_BITS_SHIFT 0x05 +#define WCD_USBSS_EFUSE_REG_14_AUDSW_R_OFFSET_TRIM_SHIFT 0x00 + +/* WCD_USBSS_EFUSE_REG_15 Fields: */ +#define WCD_USBSS_EFUSE_REG_15_SPARE_BITS_SHIFT 0x00 + +/* WCD_USBSS_EFUSE_PRG_CTL Fields: */ +#define WCD_USBSS_EFUSE_PRG_CTL_PRG_ADDR_SHIFT 0x00 + + +#endif /* WCD_USBSS_REG_SHIFTS_H */ diff --git a/drivers/soc/qcom/wcd-usbss-registers.h b/drivers/soc/qcom/wcd-usbss-registers.h new file mode 100644 index 000000000000..517caee1fa0e --- /dev/null +++ b/drivers/soc/qcom/wcd-usbss-registers.h @@ -0,0 +1,501 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef WCD_USBSS_REGISTERS_H +#define WCD_USBSS_REGISTERS_H + +enum { + REG_NO_ACCESS, + RD_REG, + WR_REG, + RD_WR_REG, +}; + +#define WCD_USBSS_BASE (-1) +#define WCD_USBSS_REG(reg) (reg - WCD_USBSS_BASE - 1) + +#define WCD_USBSS_PAGE0_BASE (WCD_USBSS_BASE+0x01) +#define WCD_USBSS_PAGE0_PAGE (WCD_USBSS_PAGE0_BASE+0x00) + +#define WCD_USBSS_CP_BASE (WCD_USBSS_BASE+0x02) +#define WCD_USBSS_PMP_EN (WCD_USBSS_CP_BASE+0x00) +#define WCD_USBSS_PMP_OUT1 (WCD_USBSS_CP_BASE+0x01) +#define WCD_USBSS_PMP_OUT2 (WCD_USBSS_CP_BASE+0x02) +#define WCD_USBSS_PMP_CLK (WCD_USBSS_CP_BASE+0x03) +#define WCD_USBSS_PMP_MISC1 (WCD_USBSS_CP_BASE+0x04) +#define WCD_USBSS_PMP_MISC2 (WCD_USBSS_CP_BASE+0x05) + +#define WCD_USBSS_RCO_BASE (WCD_USBSS_BASE+0x11) +#define WCD_USBSS_RCO_EN (WCD_USBSS_RCO_BASE+0x00) +#define WCD_USBSS_RCO_RST (WCD_USBSS_RCO_BASE+0x01) +#define WCD_USBSS_RCO_CLK (WCD_USBSS_RCO_BASE+0x02) +#define WCD_USBSS_RCO_IBIAS (WCD_USBSS_RCO_BASE+0x03) +#define WCD_USBSS_RCO_MISC1 (WCD_USBSS_RCO_BASE+0x04) +#define WCD_USBSS_RCO_MISC2 (WCD_USBSS_RCO_BASE+0x05) + +#define WCD_USBSS_OVP_BASE (WCD_USBSS_BASE+0x1f) +#define WCD_USBSS_DP_EN (WCD_USBSS_OVP_BASE+0x00) +#define WCD_USBSS_DP_BIAS (WCD_USBSS_OVP_BASE+0x01) +#define WCD_USBSS_DP_DN_MISC1 (WCD_USBSS_OVP_BASE+0x02) +#define WCD_USBSS_DN_EN (WCD_USBSS_OVP_BASE+0x03) +#define WCD_USBSS_DN_BIAS (WCD_USBSS_OVP_BASE+0x04) +#define WCD_USBSS_DP_DN_MISC2 (WCD_USBSS_OVP_BASE+0x05) +#define WCD_USBSS_MG1_EN (WCD_USBSS_OVP_BASE+0x06) +#define WCD_USBSS_MG1_BIAS (WCD_USBSS_OVP_BASE+0x07) +#define WCD_USBSS_MG1_CTSNS_CTL (WCD_USBSS_OVP_BASE+0x08) +#define WCD_USBSS_MG1_MISC (WCD_USBSS_OVP_BASE+0x09) +#define WCD_USBSS_MG2_EN (WCD_USBSS_OVP_BASE+0x0a) +#define WCD_USBSS_MG2_BIAS (WCD_USBSS_OVP_BASE+0x0b) +#define WCD_USBSS_MG2_CTSNS_CTL (WCD_USBSS_OVP_BASE+0x0c) +#define WCD_USBSS_MG2_MISC (WCD_USBSS_OVP_BASE+0x0d) +#define WCD_USBSS_BIAS_TOP (WCD_USBSS_OVP_BASE+0x0e) +#define WCD_USBSS_VREF_CTRL (WCD_USBSS_OVP_BASE+0x0f) +#define WCD_USBSS_TOP_MISC1 (WCD_USBSS_OVP_BASE+0x10) +#define WCD_USBSS_TOP_MISC2 (WCD_USBSS_OVP_BASE+0x11) +#define WCD_USBSS_STATUS_1 (WCD_USBSS_OVP_BASE+0x12) +#define WCD_USBSS_STATUS_2 (WCD_USBSS_OVP_BASE+0x13) +#define WCD_USBSS_STATUS_3 (WCD_USBSS_OVP_BASE+0x14) + +#define WCD_USBSS_LINEARIZER_BASE (WCD_USBSS_BASE+0x3e) +#define WCD_USBSS_EXT_LIN_EN (WCD_USBSS_LINEARIZER_BASE+0x00) +#define WCD_USBSS_INT_LIN_EN (WCD_USBSS_LINEARIZER_BASE+0x01) +#define WCD_USBSS_COMBINER_IREF_PROG_1 (WCD_USBSS_LINEARIZER_BASE+0x02) +#define WCD_USBSS_COMBINER_IREF_PROG_2 (WCD_USBSS_LINEARIZER_BASE+0x03) +#define WCD_USBSS_EXTSW_AMP_BIAS (WCD_USBSS_LINEARIZER_BASE+0x04) +#define WCD_USBSS_INTSW_ILIFT (WCD_USBSS_LINEARIZER_BASE+0x05) +#define WCD_USBSS_EXT_SW_CTRL_1 (WCD_USBSS_LINEARIZER_BASE+0x06) +#define WCD_USBSS_EXT_SW_CTRL_2 (WCD_USBSS_LINEARIZER_BASE+0x07) +#define WCD_USBSS_INT_SW_CTRL_1 (WCD_USBSS_LINEARIZER_BASE+0x08) +#define WCD_USBSS_INT_SW_CTRL_2 (WCD_USBSS_LINEARIZER_BASE+0x09) +#define WCD_USBSS_INT_SW_CTRL_3 (WCD_USBSS_LINEARIZER_BASE+0x0a) +#define WCD_USBSS_ATEST_CTRL (WCD_USBSS_LINEARIZER_BASE+0x0b) +#define WCD_USBSS_EXT_LIN_AUD_CEQ_PRG (WCD_USBSS_LINEARIZER_BASE+0x0c) +#define WCD_USBSS_EXT_LIN_GND_CEQ_PRG (WCD_USBSS_LINEARIZER_BASE+0x0d) +#define WCD_USBSS_LIN_STATUS_1 (WCD_USBSS_LINEARIZER_BASE+0x0e) +#define WCD_USBSS_LIN_STATUS_2 (WCD_USBSS_LINEARIZER_BASE+0x0f) +#define WCD_USBSS_LIN_STATUS_3 (WCD_USBSS_LINEARIZER_BASE+0x10) +#define WCD_USBSS_LIN_STATUS_4 (WCD_USBSS_LINEARIZER_BASE+0x11) +#define WCD_USBSS_SW_LIN_CTRL (WCD_USBSS_LINEARIZER_BASE+0x12) +#define WCD_USBSS_SW_LIN_CTRL_1 (WCD_USBSS_LINEARIZER_BASE+0x13) + +#define WCD_USBSS_NON_AUDIO_BASE (WCD_USBSS_BASE+0x52) +#define WCD_USBSS_LDO_3P6 (WCD_USBSS_NON_AUDIO_BASE+0x00) +#define WCD_USBSS_SWITCH_BANK_ATEST (WCD_USBSS_NON_AUDIO_BASE+0x01) +#define WCD_USBSS_EQ_EN (WCD_USBSS_NON_AUDIO_BASE+0x02) +#define WCD_USBSS_EQ_MISC (WCD_USBSS_NON_AUDIO_BASE+0x03) +#define WCD_USBSS_STATUS_MISC (WCD_USBSS_NON_AUDIO_BASE+0x04) + +#define WCD_USBSS_SEQUENCER_BASE (WCD_USBSS_BASE+0x5b) +#define WCD_USBSS_FSM_DELAYS1 (WCD_USBSS_SEQUENCER_BASE+0x00) +#define WCD_USBSS_FSM_DELAYS2 (WCD_USBSS_SEQUENCER_BASE+0x01) +#define WCD_USBSS_FSM_DELAYS3 (WCD_USBSS_SEQUENCER_BASE+0x02) +#define WCD_USBSS_FSM_DELAYS4 (WCD_USBSS_SEQUENCER_BASE+0x03) +#define WCD_USBSS_FSM_DELAYS5 (WCD_USBSS_SEQUENCER_BASE+0x04) +#define WCD_USBSS_FSM_DELAYS6 (WCD_USBSS_SEQUENCER_BASE+0x05) +#define WCD_USBSS_FSM_DELAYS7 (WCD_USBSS_SEQUENCER_BASE+0x06) +#define WCD_USBSS_FSM_DELAYS8 (WCD_USBSS_SEQUENCER_BASE+0x07) +#define WCD_USBSS_FSM_DEBUG_SIGNALS (WCD_USBSS_SEQUENCER_BASE+0x08) +#define WCD_USBSS_FSM_OVERRIDE (WCD_USBSS_SEQUENCER_BASE+0x09) +#define WCD_USBSS_ENABLE_STATUS (WCD_USBSS_SEQUENCER_BASE+0x0a) +#define WCD_USBSS_FRZ_STATUS (WCD_USBSS_SEQUENCER_BASE+0x0b) + +#define WCD_USBSS_USB_ANA_DIG_TOP_BASE (WCD_USBSS_BASE+0x6c) +#define WCD_USBSS_DPR_DNL_SWITCH_ENABLE_STATUS (WCD_USBSS_USB_ANA_DIG_TOP_BASE+0x00) +#define WCD_USBSS_SBU_GSBU_SWITCH_ENABLE_STATUS (WCD_USBSS_USB_ANA_DIG_TOP_BASE+0x01) +#define WCD_USBSS_DPAUX_SWITCH_ENABLE_STATUS (WCD_USBSS_USB_ANA_DIG_TOP_BASE+0x02) +#define WCD_USBSS_DPR_DNL_EXTFET_GATE_MUX_STATUS (WCD_USBSS_USB_ANA_DIG_TOP_BASE+0x03) +#define WCD_USBSS_SBU_EXTFET_GATE_MUX_OVP_STATUS (WCD_USBSS_USB_ANA_DIG_TOP_BASE+0x04) +#define WCD_USBSS_CP_LIN_CNTL_STATUS (WCD_USBSS_USB_ANA_DIG_TOP_BASE+0x05) + +#define WCD_USBSS_E_BASE (WCD_USBSS_BASE+0x81) +#define WCD_USBSS_DISP_AUXP_THRESH (WCD_USBSS_E_BASE+0x00) +#define WCD_USBSS_DISP_AUXP_CTL (WCD_USBSS_E_BASE+0x01) +#define WCD_USBSS_DISP_AUXM_THRESH (WCD_USBSS_E_BASE+0x02) +#define WCD_USBSS_DISP_AUXM_CTL (WCD_USBSS_E_BASE+0x03) + +#define WCD_USBSS_USB_LDO_BASE (WCD_USBSS_BASE+0x87) +#define WCD_USBSS_CTRL_0 (WCD_USBSS_USB_LDO_BASE+0x00) +#define WCD_USBSS_CTRL_1 (WCD_USBSS_USB_LDO_BASE+0x01) + +#define WCD_USBSS_LINEARIZER_BYPASS_CAL_BASE (WCD_USBSS_BASE+0x91) +#define WCD_USBSS_DC_TRIMCODE_1 (WCD_USBSS_LINEARIZER_BYPASS_CAL_BASE+0x00) +#define WCD_USBSS_DC_TRIMCODE_2 (WCD_USBSS_LINEARIZER_BYPASS_CAL_BASE+0x01) +#define WCD_USBSS_DC_TRIMCODE_3 (WCD_USBSS_LINEARIZER_BYPASS_CAL_BASE+0x02) +#define WCD_USBSS_AC_TRIMCODE_1 (WCD_USBSS_LINEARIZER_BYPASS_CAL_BASE+0x03) +#define WCD_USBSS_AC_TRIMCODE_2 (WCD_USBSS_LINEARIZER_BYPASS_CAL_BASE+0x04) + +#define WCD_USBSS_CP_LDO_BASE (WCD_USBSS_BASE+0xa1) +#define WCD_USBSS_CPLDO_CTL1 (WCD_USBSS_CP_LDO_BASE+0x00) +#define WCD_USBSS_CPLDO_CTL2 (WCD_USBSS_CP_LDO_BASE+0x01) + +#define WCD_USBSS_LINEARIZER_CAL_BASE (WCD_USBSS_BASE+0x101) +#define WCD_USBSS_LUT_REG0 (WCD_USBSS_LINEARIZER_CAL_BASE+0x01) +#define WCD_USBSS_LUT_REG1 (WCD_USBSS_LINEARIZER_CAL_BASE+0x02) +#define WCD_USBSS_LUT_REG2 (WCD_USBSS_LINEARIZER_CAL_BASE+0x03) +#define WCD_USBSS_LUT_REG3 (WCD_USBSS_LINEARIZER_CAL_BASE+0x04) +#define WCD_USBSS_LUT_REG4 (WCD_USBSS_LINEARIZER_CAL_BASE+0x05) +#define WCD_USBSS_LUT_REG5 (WCD_USBSS_LINEARIZER_CAL_BASE+0x06) +#define WCD_USBSS_LUT_REG6 (WCD_USBSS_LINEARIZER_CAL_BASE+0x07) +#define WCD_USBSS_LUT_REG7 (WCD_USBSS_LINEARIZER_CAL_BASE+0x08) +#define WCD_USBSS_LUT_REG8 (WCD_USBSS_LINEARIZER_CAL_BASE+0x09) +#define WCD_USBSS_LUT_REG9 (WCD_USBSS_LINEARIZER_CAL_BASE+0x0a) +#define WCD_USBSS_LUT_REG10 (WCD_USBSS_LINEARIZER_CAL_BASE+0x0b) +#define WCD_USBSS_LUT_REG11 (WCD_USBSS_LINEARIZER_CAL_BASE+0x0c) +#define WCD_USBSS_LUT_REG12 (WCD_USBSS_LINEARIZER_CAL_BASE+0x0d) +#define WCD_USBSS_LUT_REG13 (WCD_USBSS_LINEARIZER_CAL_BASE+0x0e) +#define WCD_USBSS_LUT_REG14 (WCD_USBSS_LINEARIZER_CAL_BASE+0x0f) +#define WCD_USBSS_LUT_REG15 (WCD_USBSS_LINEARIZER_CAL_BASE+0x10) +#define WCD_USBSS_LUT_REG16 (WCD_USBSS_LINEARIZER_CAL_BASE+0x11) +#define WCD_USBSS_LUT_REG17 (WCD_USBSS_LINEARIZER_CAL_BASE+0x12) +#define WCD_USBSS_LUT_REG18 (WCD_USBSS_LINEARIZER_CAL_BASE+0x13) +#define WCD_USBSS_LUT_REG19 (WCD_USBSS_LINEARIZER_CAL_BASE+0x14) +#define WCD_USBSS_LUT_REG20 (WCD_USBSS_LINEARIZER_CAL_BASE+0x15) +#define WCD_USBSS_LUT_REG21 (WCD_USBSS_LINEARIZER_CAL_BASE+0x16) +#define WCD_USBSS_LUT_REG22 (WCD_USBSS_LINEARIZER_CAL_BASE+0x17) +#define WCD_USBSS_LUT_REG23 (WCD_USBSS_LINEARIZER_CAL_BASE+0x18) +#define WCD_USBSS_LUT_REG24 (WCD_USBSS_LINEARIZER_CAL_BASE+0x19) +#define WCD_USBSS_LUT_REG25 (WCD_USBSS_LINEARIZER_CAL_BASE+0x1a) +#define WCD_USBSS_LUT_REG26 (WCD_USBSS_LINEARIZER_CAL_BASE+0x1b) +#define WCD_USBSS_LUT_REG27 (WCD_USBSS_LINEARIZER_CAL_BASE+0x1c) +#define WCD_USBSS_LUT_REG28 (WCD_USBSS_LINEARIZER_CAL_BASE+0x1d) +#define WCD_USBSS_LUT_REG29 (WCD_USBSS_LINEARIZER_CAL_BASE+0x1e) +#define WCD_USBSS_LUT_REG30 (WCD_USBSS_LINEARIZER_CAL_BASE+0x1f) +#define WCD_USBSS_LUT_REG31 (WCD_USBSS_LINEARIZER_CAL_BASE+0x20) +#define WCD_USBSS_LUT_REG32 (WCD_USBSS_LINEARIZER_CAL_BASE+0x21) +#define WCD_USBSS_LUT_REG33 (WCD_USBSS_LINEARIZER_CAL_BASE+0x22) +#define WCD_USBSS_LUT_REG34 (WCD_USBSS_LINEARIZER_CAL_BASE+0x23) +#define WCD_USBSS_LUT_REG35 (WCD_USBSS_LINEARIZER_CAL_BASE+0x24) +#define WCD_USBSS_LUT_REG36 (WCD_USBSS_LINEARIZER_CAL_BASE+0x25) +#define WCD_USBSS_LUT_REG37 (WCD_USBSS_LINEARIZER_CAL_BASE+0x26) +#define WCD_USBSS_LUT_REG38 (WCD_USBSS_LINEARIZER_CAL_BASE+0x27) +#define WCD_USBSS_LUT_REG39 (WCD_USBSS_LINEARIZER_CAL_BASE+0x28) +#define WCD_USBSS_LUT_REG40 (WCD_USBSS_LINEARIZER_CAL_BASE+0x29) +#define WCD_USBSS_LUT_REG41 (WCD_USBSS_LINEARIZER_CAL_BASE+0x2a) +#define WCD_USBSS_LUT_REG42 (WCD_USBSS_LINEARIZER_CAL_BASE+0x2b) +#define WCD_USBSS_LUT_REG43 (WCD_USBSS_LINEARIZER_CAL_BASE+0x2c) +#define WCD_USBSS_LUT_REG44 (WCD_USBSS_LINEARIZER_CAL_BASE+0x2d) +#define WCD_USBSS_LUT_REG45 (WCD_USBSS_LINEARIZER_CAL_BASE+0x2e) +#define WCD_USBSS_LUT_REG46 (WCD_USBSS_LINEARIZER_CAL_BASE+0x2f) +#define WCD_USBSS_LUT_REG47 (WCD_USBSS_LINEARIZER_CAL_BASE+0x30) +#define WCD_USBSS_LUT_REG48 (WCD_USBSS_LINEARIZER_CAL_BASE+0x31) +#define WCD_USBSS_LUT_REG49 (WCD_USBSS_LINEARIZER_CAL_BASE+0x32) +#define WCD_USBSS_LUT_REG50 (WCD_USBSS_LINEARIZER_CAL_BASE+0x33) +#define WCD_USBSS_LUT_REG51 (WCD_USBSS_LINEARIZER_CAL_BASE+0x34) +#define WCD_USBSS_LUT_REG52 (WCD_USBSS_LINEARIZER_CAL_BASE+0x35) +#define WCD_USBSS_LUT_REG53 (WCD_USBSS_LINEARIZER_CAL_BASE+0x36) +#define WCD_USBSS_LUT_REG54 (WCD_USBSS_LINEARIZER_CAL_BASE+0x37) +#define WCD_USBSS_LUT_REG55 (WCD_USBSS_LINEARIZER_CAL_BASE+0x38) +#define WCD_USBSS_LUT_REG56 (WCD_USBSS_LINEARIZER_CAL_BASE+0x39) +#define WCD_USBSS_LUT_REG57 (WCD_USBSS_LINEARIZER_CAL_BASE+0x3a) +#define WCD_USBSS_LUT_REG58 (WCD_USBSS_LINEARIZER_CAL_BASE+0x3b) +#define WCD_USBSS_LUT_REG59 (WCD_USBSS_LINEARIZER_CAL_BASE+0x3c) +#define WCD_USBSS_LUT_REG60 (WCD_USBSS_LINEARIZER_CAL_BASE+0x3d) +#define WCD_USBSS_LUT_REG61 (WCD_USBSS_LINEARIZER_CAL_BASE+0x3e) +#define WCD_USBSS_LUT_REG62 (WCD_USBSS_LINEARIZER_CAL_BASE+0x3f) +#define WCD_USBSS_LUT_REG63 (WCD_USBSS_LINEARIZER_CAL_BASE+0x40) +#define WCD_USBSS_LUT_REG64 (WCD_USBSS_LINEARIZER_CAL_BASE+0x41) +#define WCD_USBSS_LUT_REG65 (WCD_USBSS_LINEARIZER_CAL_BASE+0x42) +#define WCD_USBSS_LUT_REG66 (WCD_USBSS_LINEARIZER_CAL_BASE+0x43) +#define WCD_USBSS_LUT_REG67 (WCD_USBSS_LINEARIZER_CAL_BASE+0x44) +#define WCD_USBSS_LUT_REG68 (WCD_USBSS_LINEARIZER_CAL_BASE+0x45) +#define WCD_USBSS_LUT_REG69 (WCD_USBSS_LINEARIZER_CAL_BASE+0x46) +#define WCD_USBSS_LUT_REG70 (WCD_USBSS_LINEARIZER_CAL_BASE+0x47) +#define WCD_USBSS_LUT_REG71 (WCD_USBSS_LINEARIZER_CAL_BASE+0x48) +#define WCD_USBSS_LUT_REG72 (WCD_USBSS_LINEARIZER_CAL_BASE+0x49) +#define WCD_USBSS_LUT_REG73 (WCD_USBSS_LINEARIZER_CAL_BASE+0x4a) +#define WCD_USBSS_LUT_REG74 (WCD_USBSS_LINEARIZER_CAL_BASE+0x4b) +#define WCD_USBSS_LUT_REG75 (WCD_USBSS_LINEARIZER_CAL_BASE+0x4c) +#define WCD_USBSS_LUT_REG76 (WCD_USBSS_LINEARIZER_CAL_BASE+0x4d) +#define WCD_USBSS_LUT_REG77 (WCD_USBSS_LINEARIZER_CAL_BASE+0x4e) +#define WCD_USBSS_LUT_REG78 (WCD_USBSS_LINEARIZER_CAL_BASE+0x4f) +#define WCD_USBSS_LUT_REG79 (WCD_USBSS_LINEARIZER_CAL_BASE+0x50) +#define WCD_USBSS_LUT_REG80 (WCD_USBSS_LINEARIZER_CAL_BASE+0x51) +#define WCD_USBSS_LUT_REG81 (WCD_USBSS_LINEARIZER_CAL_BASE+0x52) +#define WCD_USBSS_LUT_REG82 (WCD_USBSS_LINEARIZER_CAL_BASE+0x53) +#define WCD_USBSS_LUT_REG83 (WCD_USBSS_LINEARIZER_CAL_BASE+0x54) +#define WCD_USBSS_LUT_REG84 (WCD_USBSS_LINEARIZER_CAL_BASE+0x55) +#define WCD_USBSS_LUT_REG85 (WCD_USBSS_LINEARIZER_CAL_BASE+0x56) +#define WCD_USBSS_LUT_REG86 (WCD_USBSS_LINEARIZER_CAL_BASE+0x57) +#define WCD_USBSS_LUT_REG87 (WCD_USBSS_LINEARIZER_CAL_BASE+0x58) +#define WCD_USBSS_LUT_REG88 (WCD_USBSS_LINEARIZER_CAL_BASE+0x59) +#define WCD_USBSS_LUT_REG89 (WCD_USBSS_LINEARIZER_CAL_BASE+0x5a) +#define WCD_USBSS_LUT_REG90 (WCD_USBSS_LINEARIZER_CAL_BASE+0x5b) +#define WCD_USBSS_LUT_REG91 (WCD_USBSS_LINEARIZER_CAL_BASE+0x5c) +#define WCD_USBSS_LUT_REG92 (WCD_USBSS_LINEARIZER_CAL_BASE+0x5d) +#define WCD_USBSS_LUT_REG93 (WCD_USBSS_LINEARIZER_CAL_BASE+0x5e) +#define WCD_USBSS_LUT_REG94 (WCD_USBSS_LINEARIZER_CAL_BASE+0x5f) +#define WCD_USBSS_LUT_REG95 (WCD_USBSS_LINEARIZER_CAL_BASE+0x60) +#define WCD_USBSS_LUT_REG96 (WCD_USBSS_LINEARIZER_CAL_BASE+0x61) +#define WCD_USBSS_LUT_REG97 (WCD_USBSS_LINEARIZER_CAL_BASE+0x62) +#define WCD_USBSS_LUT_REG98 (WCD_USBSS_LINEARIZER_CAL_BASE+0x63) +#define WCD_USBSS_LUT_REG99 (WCD_USBSS_LINEARIZER_CAL_BASE+0x64) +#define WCD_USBSS_LUT_REG100 (WCD_USBSS_LINEARIZER_CAL_BASE+0x65) +#define WCD_USBSS_LUT_REG101 (WCD_USBSS_LINEARIZER_CAL_BASE+0x66) +#define WCD_USBSS_LUT_REG102 (WCD_USBSS_LINEARIZER_CAL_BASE+0x67) +#define WCD_USBSS_LUT_REG103 (WCD_USBSS_LINEARIZER_CAL_BASE+0x68) +#define WCD_USBSS_LUT_REG104 (WCD_USBSS_LINEARIZER_CAL_BASE+0x69) +#define WCD_USBSS_LUT_REG105 (WCD_USBSS_LINEARIZER_CAL_BASE+0x6a) +#define WCD_USBSS_LUT_REG106 (WCD_USBSS_LINEARIZER_CAL_BASE+0x6b) +#define WCD_USBSS_LUT_REG107 (WCD_USBSS_LINEARIZER_CAL_BASE+0x6c) +#define WCD_USBSS_LUT_REG108 (WCD_USBSS_LINEARIZER_CAL_BASE+0x6d) +#define WCD_USBSS_LUT_REG109 (WCD_USBSS_LINEARIZER_CAL_BASE+0x6e) +#define WCD_USBSS_LUT_REG110 (WCD_USBSS_LINEARIZER_CAL_BASE+0x6f) +#define WCD_USBSS_LUT_REG111 (WCD_USBSS_LINEARIZER_CAL_BASE+0x70) +#define WCD_USBSS_LUT_REG112 (WCD_USBSS_LINEARIZER_CAL_BASE+0x71) +#define WCD_USBSS_LUT_REG113 (WCD_USBSS_LINEARIZER_CAL_BASE+0x72) +#define WCD_USBSS_LUT_REG114 (WCD_USBSS_LINEARIZER_CAL_BASE+0x73) +#define WCD_USBSS_LUT_REG115 (WCD_USBSS_LINEARIZER_CAL_BASE+0x74) +#define WCD_USBSS_LUT_REG116 (WCD_USBSS_LINEARIZER_CAL_BASE+0x75) +#define WCD_USBSS_LUT_REG117 (WCD_USBSS_LINEARIZER_CAL_BASE+0x76) +#define WCD_USBSS_LUT_REG118 (WCD_USBSS_LINEARIZER_CAL_BASE+0x77) +#define WCD_USBSS_LUT_REG119 (WCD_USBSS_LINEARIZER_CAL_BASE+0x78) +#define WCD_USBSS_LUT_REG120 (WCD_USBSS_LINEARIZER_CAL_BASE+0x79) +#define WCD_USBSS_LUT_REG121 (WCD_USBSS_LINEARIZER_CAL_BASE+0x7a) +#define WCD_USBSS_LUT_REG122 (WCD_USBSS_LINEARIZER_CAL_BASE+0x7b) +#define WCD_USBSS_LUT_REG123 (WCD_USBSS_LINEARIZER_CAL_BASE+0x7c) +#define WCD_USBSS_LUT_REG124 (WCD_USBSS_LINEARIZER_CAL_BASE+0x7d) +#define WCD_USBSS_LUT_REG125 (WCD_USBSS_LINEARIZER_CAL_BASE+0x7e) +#define WCD_USBSS_LUT_REG126 (WCD_USBSS_LINEARIZER_CAL_BASE+0x7f) +#define WCD_USBSS_LUT_REG127 (WCD_USBSS_LINEARIZER_CAL_BASE+0x80) +#define WCD_USBSS_LUT_REG128 (WCD_USBSS_LINEARIZER_CAL_BASE+0x81) +#define WCD_USBSS_LUT_REG129 (WCD_USBSS_LINEARIZER_CAL_BASE+0x82) +#define WCD_USBSS_LUT_REG130 (WCD_USBSS_LINEARIZER_CAL_BASE+0x83) +#define WCD_USBSS_LUT_REG131 (WCD_USBSS_LINEARIZER_CAL_BASE+0x84) +#define WCD_USBSS_LUT_REG132 (WCD_USBSS_LINEARIZER_CAL_BASE+0x85) +#define WCD_USBSS_LUT_REG133 (WCD_USBSS_LINEARIZER_CAL_BASE+0x86) +#define WCD_USBSS_LUT_REG134 (WCD_USBSS_LINEARIZER_CAL_BASE+0x87) +#define WCD_USBSS_LUT_REG135 (WCD_USBSS_LINEARIZER_CAL_BASE+0x88) +#define WCD_USBSS_LUT_REG136 (WCD_USBSS_LINEARIZER_CAL_BASE+0x89) +#define WCD_USBSS_LUT_REG137 (WCD_USBSS_LINEARIZER_CAL_BASE+0x8a) +#define WCD_USBSS_LUT_REG138 (WCD_USBSS_LINEARIZER_CAL_BASE+0x8b) +#define WCD_USBSS_LUT_REG139 (WCD_USBSS_LINEARIZER_CAL_BASE+0x8c) +#define WCD_USBSS_LUT_REG140 (WCD_USBSS_LINEARIZER_CAL_BASE+0x8d) +#define WCD_USBSS_LUT_REG141 (WCD_USBSS_LINEARIZER_CAL_BASE+0x8e) +#define WCD_USBSS_LUT_REG142 (WCD_USBSS_LINEARIZER_CAL_BASE+0x8f) +#define WCD_USBSS_LUT_REG143 (WCD_USBSS_LINEARIZER_CAL_BASE+0x90) +#define WCD_USBSS_LUT_REG144 (WCD_USBSS_LINEARIZER_CAL_BASE+0x91) +#define WCD_USBSS_LUT_REG145 (WCD_USBSS_LINEARIZER_CAL_BASE+0x92) +#define WCD_USBSS_LUT_REG146 (WCD_USBSS_LINEARIZER_CAL_BASE+0x93) +#define WCD_USBSS_LUT_REG147 (WCD_USBSS_LINEARIZER_CAL_BASE+0x94) +#define WCD_USBSS_LUT_REG148 (WCD_USBSS_LINEARIZER_CAL_BASE+0x95) +#define WCD_USBSS_LUT_REG149 (WCD_USBSS_LINEARIZER_CAL_BASE+0x96) +#define WCD_USBSS_LUT_REG150 (WCD_USBSS_LINEARIZER_CAL_BASE+0x97) +#define WCD_USBSS_LUT_REG151 (WCD_USBSS_LINEARIZER_CAL_BASE+0x98) +#define WCD_USBSS_LUT_REG152 (WCD_USBSS_LINEARIZER_CAL_BASE+0x99) +#define WCD_USBSS_LUT_REG153 (WCD_USBSS_LINEARIZER_CAL_BASE+0x9a) +#define WCD_USBSS_LUT_REG154 (WCD_USBSS_LINEARIZER_CAL_BASE+0x9b) +#define WCD_USBSS_LUT_REG155 (WCD_USBSS_LINEARIZER_CAL_BASE+0x9c) +#define WCD_USBSS_LUT_REG156 (WCD_USBSS_LINEARIZER_CAL_BASE+0x9d) +#define WCD_USBSS_LUT_REG157 (WCD_USBSS_LINEARIZER_CAL_BASE+0x9e) +#define WCD_USBSS_LUT_REG158 (WCD_USBSS_LINEARIZER_CAL_BASE+0x9f) +#define WCD_USBSS_LUT_REG159 (WCD_USBSS_LINEARIZER_CAL_BASE+0xa0) +#define WCD_USBSS_LUT_REG160 (WCD_USBSS_LINEARIZER_CAL_BASE+0xa1) +#define WCD_USBSS_LUT_REG161 (WCD_USBSS_LINEARIZER_CAL_BASE+0xa2) +#define WCD_USBSS_LUT_REG162 (WCD_USBSS_LINEARIZER_CAL_BASE+0xa3) +#define WCD_USBSS_LUT_REG163 (WCD_USBSS_LINEARIZER_CAL_BASE+0xa4) +#define WCD_USBSS_LUT_REG164 (WCD_USBSS_LINEARIZER_CAL_BASE+0xa5) +#define WCD_USBSS_LUT_REG165 (WCD_USBSS_LINEARIZER_CAL_BASE+0xa6) +#define WCD_USBSS_LUT_REG166 (WCD_USBSS_LINEARIZER_CAL_BASE+0xa7) +#define WCD_USBSS_LUT_REG167 (WCD_USBSS_LINEARIZER_CAL_BASE+0xa8) +#define WCD_USBSS_LUT_REG168 (WCD_USBSS_LINEARIZER_CAL_BASE+0xa9) +#define WCD_USBSS_LUT_REG169 (WCD_USBSS_LINEARIZER_CAL_BASE+0xaa) +#define WCD_USBSS_LUT_REG170 (WCD_USBSS_LINEARIZER_CAL_BASE+0xab) +#define WCD_USBSS_LUT_REG171 (WCD_USBSS_LINEARIZER_CAL_BASE+0xac) +#define WCD_USBSS_LUT_REG172 (WCD_USBSS_LINEARIZER_CAL_BASE+0xad) +#define WCD_USBSS_LUT_REG173 (WCD_USBSS_LINEARIZER_CAL_BASE+0xae) +#define WCD_USBSS_LUT_REG174 (WCD_USBSS_LINEARIZER_CAL_BASE+0xaf) +#define WCD_USBSS_LUT_REG175 (WCD_USBSS_LINEARIZER_CAL_BASE+0xb0) +#define WCD_USBSS_LUT_REG176 (WCD_USBSS_LINEARIZER_CAL_BASE+0xb1) +#define WCD_USBSS_LUT_REG177 (WCD_USBSS_LINEARIZER_CAL_BASE+0xb2) +#define WCD_USBSS_LUT_REG178 (WCD_USBSS_LINEARIZER_CAL_BASE+0xb3) +#define WCD_USBSS_LUT_REG179 (WCD_USBSS_LINEARIZER_CAL_BASE+0xb4) +#define WCD_USBSS_LUT_REG180 (WCD_USBSS_LINEARIZER_CAL_BASE+0xb5) +#define WCD_USBSS_LUT_REG181 (WCD_USBSS_LINEARIZER_CAL_BASE+0xb6) +#define WCD_USBSS_LUT_REG182 (WCD_USBSS_LINEARIZER_CAL_BASE+0xb7) +#define WCD_USBSS_LUT_REG183 (WCD_USBSS_LINEARIZER_CAL_BASE+0xb8) +#define WCD_USBSS_LUT_REG184 (WCD_USBSS_LINEARIZER_CAL_BASE+0xb9) +#define WCD_USBSS_LUT_REG185 (WCD_USBSS_LINEARIZER_CAL_BASE+0xba) +#define WCD_USBSS_LUT_REG186 (WCD_USBSS_LINEARIZER_CAL_BASE+0xbb) +#define WCD_USBSS_LUT_REG187 (WCD_USBSS_LINEARIZER_CAL_BASE+0xbc) +#define WCD_USBSS_LUT_REG188 (WCD_USBSS_LINEARIZER_CAL_BASE+0xbd) +#define WCD_USBSS_LUT_REG189 (WCD_USBSS_LINEARIZER_CAL_BASE+0xbe) +#define WCD_USBSS_LUT_REG190 (WCD_USBSS_LINEARIZER_CAL_BASE+0xbf) +#define WCD_USBSS_LUT_REG191 (WCD_USBSS_LINEARIZER_CAL_BASE+0xc0) +#define WCD_USBSS_LUT_REG192 (WCD_USBSS_LINEARIZER_CAL_BASE+0xc1) +#define WCD_USBSS_LUT_REG193 (WCD_USBSS_LINEARIZER_CAL_BASE+0xc2) +#define WCD_USBSS_LUT_REG194 (WCD_USBSS_LINEARIZER_CAL_BASE+0xc3) +#define WCD_USBSS_LUT_REG195 (WCD_USBSS_LINEARIZER_CAL_BASE+0xc4) +#define WCD_USBSS_LUT_REG196 (WCD_USBSS_LINEARIZER_CAL_BASE+0xc5) +#define WCD_USBSS_LUT_REG197 (WCD_USBSS_LINEARIZER_CAL_BASE+0xc6) +#define WCD_USBSS_LUT_REG198 (WCD_USBSS_LINEARIZER_CAL_BASE+0xc7) +#define WCD_USBSS_LUT_REG199 (WCD_USBSS_LINEARIZER_CAL_BASE+0xc8) +#define WCD_USBSS_LUT_REG200 (WCD_USBSS_LINEARIZER_CAL_BASE+0xc9) +#define WCD_USBSS_LUT_REG201 (WCD_USBSS_LINEARIZER_CAL_BASE+0xca) +#define WCD_USBSS_LUT_REG202 (WCD_USBSS_LINEARIZER_CAL_BASE+0xcb) +#define WCD_USBSS_LUT_REG203 (WCD_USBSS_LINEARIZER_CAL_BASE+0xcc) +#define WCD_USBSS_LUT_REG204 (WCD_USBSS_LINEARIZER_CAL_BASE+0xcd) +#define WCD_USBSS_LUT_REG205 (WCD_USBSS_LINEARIZER_CAL_BASE+0xce) +#define WCD_USBSS_LUT_REG206 (WCD_USBSS_LINEARIZER_CAL_BASE+0xcf) +#define WCD_USBSS_LUT_REG207 (WCD_USBSS_LINEARIZER_CAL_BASE+0xd0) +#define WCD_USBSS_LUT_REG208 (WCD_USBSS_LINEARIZER_CAL_BASE+0xd1) +#define WCD_USBSS_LUT_REG209 (WCD_USBSS_LINEARIZER_CAL_BASE+0xd2) +#define WCD_USBSS_LUT_REG210 (WCD_USBSS_LINEARIZER_CAL_BASE+0xd3) +#define WCD_USBSS_DATA_SEL (WCD_USBSS_LINEARIZER_CAL_BASE+0xf6) +#define WCD_USBSS_OFF3 (WCD_USBSS_LINEARIZER_CAL_BASE+0xf7) +#define WCD_USBSS_OFF2_LSB (WCD_USBSS_LINEARIZER_CAL_BASE+0xf8) +#define WCD_USBSS_OFF2_MSB (WCD_USBSS_LINEARIZER_CAL_BASE+0xf9) +#define WCD_USBSS_OFF1_LSB (WCD_USBSS_LINEARIZER_CAL_BASE+0xfa) +#define WCD_USBSS_OFF1_MSB (WCD_USBSS_LINEARIZER_CAL_BASE+0xfb) +#define WCD_USBSS_AUD_L (WCD_USBSS_LINEARIZER_CAL_BASE+0xfc) +#define WCD_USBSS_AUD_R (WCD_USBSS_LINEARIZER_CAL_BASE+0xfd) +#define WCD_USBSS_GND_L (WCD_USBSS_LINEARIZER_CAL_BASE+0xfe) +#define WCD_USBSS_GND_R (WCD_USBSS_LINEARIZER_CAL_BASE+0xff) + +#define WCD_USBSS_USB_DIG_BASE (WCD_USBSS_BASE+0x401) +#define WCD_USBSS_USB_DIG_PAGE (WCD_USBSS_USB_DIG_BASE+0x00) +#define WCD_USBSS_OVP_STATUS_SELF_CLEARING (WCD_USBSS_USB_DIG_BASE+0x01) +#define WCD_USBSS_OVP_STATUS (WCD_USBSS_USB_DIG_BASE+0x02) +#define WCD_USBSS_SWITCH_SETTINGS_ENABLE (WCD_USBSS_USB_DIG_BASE+0x03) +#define WCD_USBSS_SWITCH_SELECT0 (WCD_USBSS_USB_DIG_BASE+0x04) +#define WCD_USBSS_SWITCH_SELECT1 (WCD_USBSS_USB_DIG_BASE+0x05) +#define WCD_USBSS_SWITCH_STATUS0 (WCD_USBSS_USB_DIG_BASE+0x06) +#define WCD_USBSS_SWITCH_STATUS1 (WCD_USBSS_USB_DIG_BASE+0x07) +#define WCD_USBSS_AUD_LEFT_SW_SLOW (WCD_USBSS_USB_DIG_BASE+0x08) +#define WCD_USBSS_AUD_RIGHT_SW_SLOW (WCD_USBSS_USB_DIG_BASE+0x09) +#define WCD_USBSS_AUD_MIC_SW_SLOW (WCD_USBSS_USB_DIG_BASE+0x0a) +#define WCD_USBSS_AUD_SENSE_SW_SLOW (WCD_USBSS_USB_DIG_BASE+0x0b) +#define WCD_USBSS_AUD_GND_SW_SLOW (WCD_USBSS_USB_DIG_BASE+0x0c) +#define WCD_USBSS_DELAY_R_SW (WCD_USBSS_USB_DIG_BASE+0x0d) +#define WCD_USBSS_DELAY_MIC_SW (WCD_USBSS_USB_DIG_BASE+0x0e) +#define WCD_USBSS_DELAY_SENSE_SW (WCD_USBSS_USB_DIG_BASE+0x0f) +#define WCD_USBSS_DELAY_GND_SW (WCD_USBSS_USB_DIG_BASE+0x10) +#define WCD_USBSS_DELAY_L_SW (WCD_USBSS_USB_DIG_BASE+0x11) +#define WCD_USBSS_EXT_FET_ENABLE_DELAY (WCD_USBSS_USB_DIG_BASE+0x12) +#define WCD_USBSS_FUNCTION_ENABLE (WCD_USBSS_USB_DIG_BASE+0x13) +#define WCD_USBSS_USB_RST_CTL (WCD_USBSS_USB_DIG_BASE+0x14) +#define WCD_USBSS_EQUALIZER1 (WCD_USBSS_USB_DIG_BASE+0x15) +#define WCD_USBSS_SPARE_0 (WCD_USBSS_USB_DIG_BASE+0x16) +#define WCD_USBSS_DIG_FUNCTIONS_STATUS (WCD_USBSS_USB_DIG_BASE+0x17) +#define WCD_USBSS_CLK_SOURCE (WCD_USBSS_USB_DIG_BASE+0x18) +#define WCD_USBSS_USB_SS_CNTL (WCD_USBSS_USB_DIG_BASE+0x19) +#define WCD_USBSS_SPARE_1 (WCD_USBSS_USB_DIG_BASE+0x1a) +#define WCD_USBSS_ANA_FUNCTIONS_STATUS (WCD_USBSS_USB_DIG_BASE+0x1b) +#define WCD_USBSS_FSM_STATUS (WCD_USBSS_USB_DIG_BASE+0x1c) +#define WCD_USBSS_SPARE_14 (WCD_USBSS_USB_DIG_BASE+0x30) +#define WCD_USBSS_SAFE_STATE_PD_DPAUX (WCD_USBSS_USB_DIG_BASE+0x32) +#define WCD_USBSS_AUDIO_FSM_START (WCD_USBSS_USB_DIG_BASE+0x33) +#define WCD_USBSS_FSM_RESET (WCD_USBSS_USB_DIG_BASE+0x34) +#define WCD_USBSS_CHIP_ID0 (WCD_USBSS_USB_DIG_BASE+0x38) +#define WCD_USBSS_CHIP_ID1 (WCD_USBSS_USB_DIG_BASE+0x39) +#define WCD_USBSS_CHIP_ID2 (WCD_USBSS_USB_DIG_BASE+0x3a) +#define WCD_USBSS_CHIP_ID3 (WCD_USBSS_USB_DIG_BASE+0x3b) +#define WCD_USBSS_LINEARIZER_CFG (WCD_USBSS_USB_DIG_BASE+0x60) +#define WCD_USBSS_RATIO_SPKR_REXT_L_LSB (WCD_USBSS_USB_DIG_BASE+0x61) +#define WCD_USBSS_RATIO_SPKR_REXT_L_MSB (WCD_USBSS_USB_DIG_BASE+0x62) +#define WCD_USBSS_RATIO_SPKR_REXT_R_LSB (WCD_USBSS_USB_DIG_BASE+0x63) +#define WCD_USBSS_RATIO_SPKR_REXT_R_MSB (WCD_USBSS_USB_DIG_BASE+0x64) +#define WCD_USBSS_SW_TAP_AUD_L_LSB (WCD_USBSS_USB_DIG_BASE+0x65) +#define WCD_USBSS_SW_TAP_AUD_L_MSB (WCD_USBSS_USB_DIG_BASE+0x66) +#define WCD_USBSS_SW_TAP_AUD_R_LSB (WCD_USBSS_USB_DIG_BASE+0x67) +#define WCD_USBSS_SW_TAP_AUD_R_MSB (WCD_USBSS_USB_DIG_BASE+0x68) +#define WCD_USBSS_SW_TAP_GND_L_LSB (WCD_USBSS_USB_DIG_BASE+0x69) +#define WCD_USBSS_SW_TAP_GND_L_MSB (WCD_USBSS_USB_DIG_BASE+0x6a) +#define WCD_USBSS_SW_TAP_GND_R_LSB (WCD_USBSS_USB_DIG_BASE+0x6b) +#define WCD_USBSS_SW_TAP_GND_R_MSB (WCD_USBSS_USB_DIG_BASE+0x6c) +#define WCD_USBSS_HW_TAP_AUD_L_LSB (WCD_USBSS_USB_DIG_BASE+0x6d) +#define WCD_USBSS_HW_TAP_AUD_L_MSB (WCD_USBSS_USB_DIG_BASE+0x6e) +#define WCD_USBSS_HW_TAP_AUD_R_LSB (WCD_USBSS_USB_DIG_BASE+0x6f) +#define WCD_USBSS_HW_TAP_AUD_R_MSB (WCD_USBSS_USB_DIG_BASE+0x70) +#define WCD_USBSS_HW_TAP_GND_L_LSB (WCD_USBSS_USB_DIG_BASE+0x71) +#define WCD_USBSS_HW_TAP_GND_L_MSB (WCD_USBSS_USB_DIG_BASE+0x72) +#define WCD_USBSS_HW_TAP_GND_R_LSB (WCD_USBSS_USB_DIG_BASE+0x73) +#define WCD_USBSS_HW_TAP_GND_R_MSB (WCD_USBSS_USB_DIG_BASE+0x74) +#define WCD_USBSS_AUD_COEF_L_K0_0 (WCD_USBSS_USB_DIG_BASE+0x75) +#define WCD_USBSS_AUD_COEF_L_K0_1 (WCD_USBSS_USB_DIG_BASE+0x76) +#define WCD_USBSS_AUD_COEF_L_K0_2 (WCD_USBSS_USB_DIG_BASE+0x77) +#define WCD_USBSS_AUD_COEF_L_K1_0 (WCD_USBSS_USB_DIG_BASE+0x78) +#define WCD_USBSS_AUD_COEF_L_K1_1 (WCD_USBSS_USB_DIG_BASE+0x79) +#define WCD_USBSS_AUD_COEF_L_K2_0 (WCD_USBSS_USB_DIG_BASE+0x7a) +#define WCD_USBSS_AUD_COEF_L_K2_1 (WCD_USBSS_USB_DIG_BASE+0x7b) +#define WCD_USBSS_AUD_COEF_L_K3_0 (WCD_USBSS_USB_DIG_BASE+0x7c) +#define WCD_USBSS_AUD_COEF_L_K3_1 (WCD_USBSS_USB_DIG_BASE+0x7d) +#define WCD_USBSS_AUD_COEF_L_K4_0 (WCD_USBSS_USB_DIG_BASE+0x7e) +#define WCD_USBSS_AUD_COEF_L_K4_1 (WCD_USBSS_USB_DIG_BASE+0x7f) +#define WCD_USBSS_AUD_COEF_L_K5_0 (WCD_USBSS_USB_DIG_BASE+0x80) +#define WCD_USBSS_AUD_COEF_L_K5_1 (WCD_USBSS_USB_DIG_BASE+0x81) +#define WCD_USBSS_AUD_COEF_R_K0_0 (WCD_USBSS_USB_DIG_BASE+0x82) +#define WCD_USBSS_AUD_COEF_R_K0_1 (WCD_USBSS_USB_DIG_BASE+0x83) +#define WCD_USBSS_AUD_COEF_R_K0_2 (WCD_USBSS_USB_DIG_BASE+0x84) +#define WCD_USBSS_AUD_COEF_R_K1_0 (WCD_USBSS_USB_DIG_BASE+0x85) +#define WCD_USBSS_AUD_COEF_R_K1_1 (WCD_USBSS_USB_DIG_BASE+0x86) +#define WCD_USBSS_AUD_COEF_R_K2_0 (WCD_USBSS_USB_DIG_BASE+0x87) +#define WCD_USBSS_AUD_COEF_R_K2_1 (WCD_USBSS_USB_DIG_BASE+0x88) +#define WCD_USBSS_AUD_COEF_R_K3_0 (WCD_USBSS_USB_DIG_BASE+0x89) +#define WCD_USBSS_AUD_COEF_R_K3_1 (WCD_USBSS_USB_DIG_BASE+0x8a) +#define WCD_USBSS_AUD_COEF_R_K4_0 (WCD_USBSS_USB_DIG_BASE+0x8b) +#define WCD_USBSS_AUD_COEF_R_K4_1 (WCD_USBSS_USB_DIG_BASE+0x8c) +#define WCD_USBSS_AUD_COEF_R_K5_0 (WCD_USBSS_USB_DIG_BASE+0x8d) +#define WCD_USBSS_AUD_COEF_R_K5_1 (WCD_USBSS_USB_DIG_BASE+0x8e) +#define WCD_USBSS_GND_COEF_L_K0_0 (WCD_USBSS_USB_DIG_BASE+0x8f) +#define WCD_USBSS_GND_COEF_L_K0_1 (WCD_USBSS_USB_DIG_BASE+0x90) +#define WCD_USBSS_GND_COEF_L_K0_2 (WCD_USBSS_USB_DIG_BASE+0x91) +#define WCD_USBSS_GND_COEF_L_K1_0 (WCD_USBSS_USB_DIG_BASE+0x92) +#define WCD_USBSS_GND_COEF_L_K1_1 (WCD_USBSS_USB_DIG_BASE+0x93) +#define WCD_USBSS_GND_COEF_L_K2_0 (WCD_USBSS_USB_DIG_BASE+0x94) +#define WCD_USBSS_GND_COEF_L_K2_1 (WCD_USBSS_USB_DIG_BASE+0x95) +#define WCD_USBSS_GND_COEF_L_K3_0 (WCD_USBSS_USB_DIG_BASE+0x96) +#define WCD_USBSS_GND_COEF_L_K3_1 (WCD_USBSS_USB_DIG_BASE+0x97) +#define WCD_USBSS_GND_COEF_L_K4_0 (WCD_USBSS_USB_DIG_BASE+0x98) +#define WCD_USBSS_GND_COEF_L_K4_1 (WCD_USBSS_USB_DIG_BASE+0x99) +#define WCD_USBSS_GND_COEF_L_K5_0 (WCD_USBSS_USB_DIG_BASE+0x9a) +#define WCD_USBSS_GND_COEF_L_K5_1 (WCD_USBSS_USB_DIG_BASE+0x9b) +#define WCD_USBSS_GND_COEF_R_K0_0 (WCD_USBSS_USB_DIG_BASE+0x9c) +#define WCD_USBSS_GND_COEF_R_K0_1 (WCD_USBSS_USB_DIG_BASE+0x9d) +#define WCD_USBSS_GND_COEF_R_K0_2 (WCD_USBSS_USB_DIG_BASE+0x9e) +#define WCD_USBSS_GND_COEF_R_K1_0 (WCD_USBSS_USB_DIG_BASE+0x9f) +#define WCD_USBSS_GND_COEF_R_K1_1 (WCD_USBSS_USB_DIG_BASE+0xa0) +#define WCD_USBSS_GND_COEF_R_K2_0 (WCD_USBSS_USB_DIG_BASE+0xa1) +#define WCD_USBSS_GND_COEF_R_K2_1 (WCD_USBSS_USB_DIG_BASE+0xa2) +#define WCD_USBSS_GND_COEF_R_K3_0 (WCD_USBSS_USB_DIG_BASE+0xa3) +#define WCD_USBSS_GND_COEF_R_K3_1 (WCD_USBSS_USB_DIG_BASE+0xa4) +#define WCD_USBSS_GND_COEF_R_K4_0 (WCD_USBSS_USB_DIG_BASE+0xa5) +#define WCD_USBSS_GND_COEF_R_K4_1 (WCD_USBSS_USB_DIG_BASE+0xa6) +#define WCD_USBSS_GND_COEF_R_K5_0 (WCD_USBSS_USB_DIG_BASE+0xa7) +#define WCD_USBSS_GND_COEF_R_K5_1 (WCD_USBSS_USB_DIG_BASE+0xa8) +#define WCD_USBSS_AUD_L_SLOPE_SCALE_LSB (WCD_USBSS_USB_DIG_BASE+0xa9) +#define WCD_USBSS_AUD_L_SLOPE_SCALE_MSB (WCD_USBSS_USB_DIG_BASE+0xaa) +#define WCD_USBSS_AUD_R_SLOPE_SCALE_LSB (WCD_USBSS_USB_DIG_BASE+0xab) +#define WCD_USBSS_AUD_R_SLOPE_SCALE_MSB (WCD_USBSS_USB_DIG_BASE+0xac) +#define WCD_USBSS_GND_L_SLOPE_SCALE_LSB (WCD_USBSS_USB_DIG_BASE+0xad) +#define WCD_USBSS_GND_L_SLOPE_SCALE_MSB (WCD_USBSS_USB_DIG_BASE+0xae) +#define WCD_USBSS_GND_R_SLOPE_SCALE_LSB (WCD_USBSS_USB_DIG_BASE+0xaf) +#define WCD_USBSS_GND_R_SLOPE_SCALE_MSB (WCD_USBSS_USB_DIG_BASE+0xb0) +#define WCD_USBSS_AUD_L_FIRST_TAP (WCD_USBSS_USB_DIG_BASE+0xb1) +#define WCD_USBSS_AUD_R_FIRST_TAP (WCD_USBSS_USB_DIG_BASE+0xb2) +#define WCD_USBSS_GND_L_FIRST_TAP (WCD_USBSS_USB_DIG_BASE+0xb3) +#define WCD_USBSS_GND_R_FIRST_TAP (WCD_USBSS_USB_DIG_BASE+0xb4) +#define WCD_USBSS_FEATURE_SELECTION (WCD_USBSS_USB_DIG_BASE+0xcb) +#define WCD_USBSS_EFUSE_REG_0 (WCD_USBSS_USB_DIG_BASE+0xcc) +#define WCD_USBSS_EFUSE_REG_1 (WCD_USBSS_USB_DIG_BASE+0xcd) +#define WCD_USBSS_EFUSE_REG_2 (WCD_USBSS_USB_DIG_BASE+0xce) +#define WCD_USBSS_EFUSE_REG_3 (WCD_USBSS_USB_DIG_BASE+0xcf) +#define WCD_USBSS_EFUSE_REG_4 (WCD_USBSS_USB_DIG_BASE+0xd0) +#define WCD_USBSS_EFUSE_REG_5 (WCD_USBSS_USB_DIG_BASE+0xd1) +#define WCD_USBSS_EFUSE_REG_6 (WCD_USBSS_USB_DIG_BASE+0xd2) +#define WCD_USBSS_EFUSE_REG_7 (WCD_USBSS_USB_DIG_BASE+0xd3) +#define WCD_USBSS_EFUSE_REG_8 (WCD_USBSS_USB_DIG_BASE+0xd4) +#define WCD_USBSS_EFUSE_REG_9 (WCD_USBSS_USB_DIG_BASE+0xd5) +#define WCD_USBSS_EFUSE_REG_10 (WCD_USBSS_USB_DIG_BASE+0xd6) +#define WCD_USBSS_EFUSE_REG_11 (WCD_USBSS_USB_DIG_BASE+0xd7) +#define WCD_USBSS_EFUSE_REG_12 (WCD_USBSS_USB_DIG_BASE+0xd8) +#define WCD_USBSS_EFUSE_REG_13 (WCD_USBSS_USB_DIG_BASE+0xd9) +#define WCD_USBSS_EFUSE_REG_14 (WCD_USBSS_USB_DIG_BASE+0xda) +#define WCD_USBSS_EFUSE_REG_15 (WCD_USBSS_USB_DIG_BASE+0xdb) +#define WCD_USBSS_EFUSE_PRG_CTL (WCD_USBSS_USB_DIG_BASE+0xe0) + +#define WCD_USBSS_NUM_REGISTERS (WCD_USBSS_EFUSE_PRG_CTL+1) +#define WCD_USBSS_MAX_REGISTER (WCD_USBSS_NUM_REGISTERS-1) + +#endif /* WCD_USBSS_REGISTERS_H */ diff --git a/drivers/soc/qcom/wcd-usbss-regmap.c b/drivers/soc/qcom/wcd-usbss-regmap.c new file mode 100644 index 000000000000..82dc0221b9cf --- /dev/null +++ b/drivers/soc/qcom/wcd-usbss-regmap.c @@ -0,0 +1,503 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include "wcd-usbss-registers.h" + +extern const u8 wcd_usbss_reg_access[WCD_USBSS_NUM_REGISTERS]; + +static struct reg_default wcd_usbss_defaults[] = { + {WCD_USBSS_PAGE0_PAGE, 0x00}, + {WCD_USBSS_PMP_EN, 0x00}, + {WCD_USBSS_PMP_OUT1, 0x08}, + {WCD_USBSS_PMP_OUT2, 0x07}, + {WCD_USBSS_PMP_CLK, 0x10}, + {WCD_USBSS_PMP_MISC1, 0x00}, + {WCD_USBSS_PMP_MISC2, 0x00}, + {WCD_USBSS_RCO_EN, 0x00}, + {WCD_USBSS_RCO_RST, 0x01}, + {WCD_USBSS_RCO_CLK, 0x00}, + {WCD_USBSS_RCO_IBIAS, 0x00}, + {WCD_USBSS_RCO_MISC1, 0x00}, + {WCD_USBSS_RCO_MISC2, 0x01}, + {WCD_USBSS_DP_EN, 0x04}, + {WCD_USBSS_DP_BIAS, 0x0f}, + {WCD_USBSS_DP_DN_MISC1, 0x00}, + {WCD_USBSS_DN_EN, 0x04}, + {WCD_USBSS_DN_BIAS, 0x0f}, + {WCD_USBSS_DP_DN_MISC2, 0x34}, + {WCD_USBSS_MG1_EN, 0x0a}, + {WCD_USBSS_MG1_BIAS, 0x0f}, + {WCD_USBSS_MG1_CTSNS_CTL, 0x21}, + {WCD_USBSS_MG1_MISC, 0x00}, + {WCD_USBSS_MG2_EN, 0x0a}, + {WCD_USBSS_MG2_BIAS, 0x0f}, + {WCD_USBSS_MG2_CTSNS_CTL, 0x21}, + {WCD_USBSS_MG2_MISC, 0x00}, + {WCD_USBSS_BIAS_TOP, 0x00}, + {WCD_USBSS_VREF_CTRL, 0x40}, + {WCD_USBSS_TOP_MISC1, 0x20}, + {WCD_USBSS_TOP_MISC2, 0x0f}, + {WCD_USBSS_STATUS_1, 0x00}, + {WCD_USBSS_STATUS_2, 0x00}, + {WCD_USBSS_STATUS_3, 0x00}, + {WCD_USBSS_EXT_LIN_EN, 0x00}, + {WCD_USBSS_INT_LIN_EN, 0x00}, + {WCD_USBSS_COMBINER_IREF_PROG_1, 0x88}, + {WCD_USBSS_COMBINER_IREF_PROG_2, 0x88}, + {WCD_USBSS_EXTSW_AMP_BIAS, 0x00}, + {WCD_USBSS_INTSW_ILIFT, 0x88}, + {WCD_USBSS_EXT_SW_CTRL_1, 0x00}, + {WCD_USBSS_EXT_SW_CTRL_2, 0x0c}, + {WCD_USBSS_INT_SW_CTRL_1, 0x00}, + {WCD_USBSS_INT_SW_CTRL_2, 0x1b}, + {WCD_USBSS_INT_SW_CTRL_3, 0x90}, + {WCD_USBSS_ATEST_CTRL, 0x00}, + {WCD_USBSS_EXT_LIN_AUD_CEQ_PRG, 0xcc}, + {WCD_USBSS_EXT_LIN_GND_CEQ_PRG, 0xcc}, + {WCD_USBSS_LIN_STATUS_1, 0x00}, + {WCD_USBSS_LIN_STATUS_2, 0x00}, + {WCD_USBSS_LIN_STATUS_3, 0x00}, + {WCD_USBSS_LIN_STATUS_4, 0x00}, + {WCD_USBSS_SW_LIN_CTRL, 0x00}, + {WCD_USBSS_SW_LIN_CTRL_1, 0x00}, + {WCD_USBSS_LDO_3P6, 0x00}, + {WCD_USBSS_SWITCH_BANK_ATEST, 0x00}, + {WCD_USBSS_EQ_EN, 0x28}, + {WCD_USBSS_EQ_MISC, 0x19}, + {WCD_USBSS_STATUS_MISC, 0x00}, + {WCD_USBSS_FSM_DELAYS1, 0x00}, + {WCD_USBSS_FSM_DELAYS2, 0x00}, + {WCD_USBSS_FSM_DELAYS3, 0x00}, + {WCD_USBSS_FSM_DELAYS4, 0x00}, + {WCD_USBSS_FSM_DELAYS5, 0x00}, + {WCD_USBSS_FSM_DELAYS6, 0x00}, + {WCD_USBSS_FSM_DELAYS7, 0x00}, + {WCD_USBSS_FSM_DELAYS8, 0x00}, + {WCD_USBSS_FSM_DEBUG_SIGNALS, 0x00}, + {WCD_USBSS_FSM_OVERRIDE, 0x40}, + {WCD_USBSS_ENABLE_STATUS, 0xe0}, + {WCD_USBSS_FRZ_STATUS, 0x80}, + {WCD_USBSS_DPR_DNL_SWITCH_ENABLE_STATUS, 0x90}, + {WCD_USBSS_SBU_GSBU_SWITCH_ENABLE_STATUS, 0x00}, + {WCD_USBSS_DPAUX_SWITCH_ENABLE_STATUS, 0x00}, + {WCD_USBSS_DPR_DNL_EXTFET_GATE_MUX_STATUS, 0x44}, + {WCD_USBSS_SBU_EXTFET_GATE_MUX_OVP_STATUS, 0x00}, + {WCD_USBSS_CP_LIN_CNTL_STATUS, 0xc0}, + {WCD_USBSS_DISP_AUXP_THRESH, 0x60}, + {WCD_USBSS_DISP_AUXP_CTL, 0xc3}, + {WCD_USBSS_DISP_AUXM_THRESH, 0xa0}, + {WCD_USBSS_DISP_AUXM_CTL, 0xc3}, + {WCD_USBSS_CTRL_0, 0x90}, + {WCD_USBSS_CTRL_1, 0x00}, + {WCD_USBSS_DC_TRIMCODE_1, 0x00}, + {WCD_USBSS_DC_TRIMCODE_2, 0x00}, + {WCD_USBSS_DC_TRIMCODE_3, 0x00}, + {WCD_USBSS_AC_TRIMCODE_1, 0x00}, + {WCD_USBSS_AC_TRIMCODE_2, 0x00}, + {WCD_USBSS_CPLDO_CTL1, 0x08}, + {WCD_USBSS_CPLDO_CTL2, 0x00}, + {WCD_USBSS_LUT_REG0, 0x00}, + {WCD_USBSS_LUT_REG1, 0x00}, + {WCD_USBSS_LUT_REG2, 0x00}, + {WCD_USBSS_LUT_REG3, 0x00}, + {WCD_USBSS_LUT_REG4, 0x00}, + {WCD_USBSS_LUT_REG5, 0x00}, + {WCD_USBSS_LUT_REG6, 0x00}, + {WCD_USBSS_LUT_REG7, 0x00}, + {WCD_USBSS_LUT_REG8, 0x00}, + {WCD_USBSS_LUT_REG9, 0x00}, + {WCD_USBSS_LUT_REG10, 0x00}, + {WCD_USBSS_LUT_REG11, 0x00}, + {WCD_USBSS_LUT_REG12, 0x00}, + {WCD_USBSS_LUT_REG13, 0x00}, + {WCD_USBSS_LUT_REG14, 0x00}, + {WCD_USBSS_LUT_REG15, 0x00}, + {WCD_USBSS_LUT_REG16, 0x00}, + {WCD_USBSS_LUT_REG17, 0x00}, + {WCD_USBSS_LUT_REG18, 0x00}, + {WCD_USBSS_LUT_REG19, 0x00}, + {WCD_USBSS_LUT_REG20, 0x00}, + {WCD_USBSS_LUT_REG21, 0x00}, + {WCD_USBSS_LUT_REG22, 0x00}, + {WCD_USBSS_LUT_REG23, 0x00}, + {WCD_USBSS_LUT_REG24, 0x00}, + {WCD_USBSS_LUT_REG25, 0x00}, + {WCD_USBSS_LUT_REG26, 0x00}, + {WCD_USBSS_LUT_REG27, 0x00}, + {WCD_USBSS_LUT_REG28, 0x00}, + {WCD_USBSS_LUT_REG29, 0x00}, + {WCD_USBSS_LUT_REG30, 0x00}, + {WCD_USBSS_LUT_REG31, 0x00}, + {WCD_USBSS_LUT_REG32, 0x00}, + {WCD_USBSS_LUT_REG33, 0x00}, + {WCD_USBSS_LUT_REG34, 0x00}, + {WCD_USBSS_LUT_REG35, 0x00}, + {WCD_USBSS_LUT_REG36, 0x00}, + {WCD_USBSS_LUT_REG37, 0x00}, + {WCD_USBSS_LUT_REG38, 0x00}, + {WCD_USBSS_LUT_REG39, 0x00}, + {WCD_USBSS_LUT_REG40, 0x00}, + {WCD_USBSS_LUT_REG41, 0x00}, + {WCD_USBSS_LUT_REG42, 0x00}, + {WCD_USBSS_LUT_REG43, 0x00}, + {WCD_USBSS_LUT_REG44, 0x00}, + {WCD_USBSS_LUT_REG45, 0x00}, + {WCD_USBSS_LUT_REG46, 0x00}, + {WCD_USBSS_LUT_REG47, 0x00}, + {WCD_USBSS_LUT_REG48, 0x00}, + {WCD_USBSS_LUT_REG49, 0x00}, + {WCD_USBSS_LUT_REG50, 0x00}, + {WCD_USBSS_LUT_REG51, 0x00}, + {WCD_USBSS_LUT_REG52, 0x00}, + {WCD_USBSS_LUT_REG53, 0x00}, + {WCD_USBSS_LUT_REG54, 0x00}, + {WCD_USBSS_LUT_REG55, 0x00}, + {WCD_USBSS_LUT_REG56, 0x00}, + {WCD_USBSS_LUT_REG57, 0x00}, + {WCD_USBSS_LUT_REG58, 0x00}, + {WCD_USBSS_LUT_REG59, 0x00}, + {WCD_USBSS_LUT_REG60, 0x00}, + {WCD_USBSS_LUT_REG61, 0x00}, + {WCD_USBSS_LUT_REG62, 0x00}, + {WCD_USBSS_LUT_REG63, 0x00}, + {WCD_USBSS_LUT_REG64, 0x00}, + {WCD_USBSS_LUT_REG65, 0x00}, + {WCD_USBSS_LUT_REG66, 0x00}, + {WCD_USBSS_LUT_REG67, 0x00}, + {WCD_USBSS_LUT_REG68, 0x00}, + {WCD_USBSS_LUT_REG69, 0x00}, + {WCD_USBSS_LUT_REG70, 0x00}, + {WCD_USBSS_LUT_REG71, 0x00}, + {WCD_USBSS_LUT_REG72, 0x00}, + {WCD_USBSS_LUT_REG73, 0x00}, + {WCD_USBSS_LUT_REG74, 0x00}, + {WCD_USBSS_LUT_REG75, 0x00}, + {WCD_USBSS_LUT_REG76, 0x00}, + {WCD_USBSS_LUT_REG77, 0x00}, + {WCD_USBSS_LUT_REG78, 0x00}, + {WCD_USBSS_LUT_REG79, 0x00}, + {WCD_USBSS_LUT_REG80, 0x00}, + {WCD_USBSS_LUT_REG81, 0x00}, + {WCD_USBSS_LUT_REG82, 0x00}, + {WCD_USBSS_LUT_REG83, 0x00}, + {WCD_USBSS_LUT_REG84, 0x00}, + {WCD_USBSS_LUT_REG85, 0x00}, + {WCD_USBSS_LUT_REG86, 0x00}, + {WCD_USBSS_LUT_REG87, 0x00}, + {WCD_USBSS_LUT_REG88, 0x00}, + {WCD_USBSS_LUT_REG89, 0x00}, + {WCD_USBSS_LUT_REG90, 0x00}, + {WCD_USBSS_LUT_REG91, 0x00}, + {WCD_USBSS_LUT_REG92, 0x00}, + {WCD_USBSS_LUT_REG93, 0x00}, + {WCD_USBSS_LUT_REG94, 0x00}, + {WCD_USBSS_LUT_REG95, 0x00}, + {WCD_USBSS_LUT_REG96, 0x00}, + {WCD_USBSS_LUT_REG97, 0x00}, + {WCD_USBSS_LUT_REG98, 0x00}, + {WCD_USBSS_LUT_REG99, 0x00}, + {WCD_USBSS_LUT_REG100, 0x00}, + {WCD_USBSS_LUT_REG101, 0x00}, + {WCD_USBSS_LUT_REG102, 0x00}, + {WCD_USBSS_LUT_REG103, 0x00}, + {WCD_USBSS_LUT_REG104, 0x00}, + {WCD_USBSS_LUT_REG105, 0x00}, + {WCD_USBSS_LUT_REG106, 0x00}, + {WCD_USBSS_LUT_REG107, 0x00}, + {WCD_USBSS_LUT_REG108, 0x00}, + {WCD_USBSS_LUT_REG109, 0x00}, + {WCD_USBSS_LUT_REG110, 0x00}, + {WCD_USBSS_LUT_REG111, 0x00}, + {WCD_USBSS_LUT_REG112, 0x00}, + {WCD_USBSS_LUT_REG113, 0x00}, + {WCD_USBSS_LUT_REG114, 0x00}, + {WCD_USBSS_LUT_REG115, 0x00}, + {WCD_USBSS_LUT_REG116, 0x00}, + {WCD_USBSS_LUT_REG117, 0x00}, + {WCD_USBSS_LUT_REG118, 0x00}, + {WCD_USBSS_LUT_REG119, 0x00}, + {WCD_USBSS_LUT_REG120, 0x00}, + {WCD_USBSS_LUT_REG121, 0x00}, + {WCD_USBSS_LUT_REG122, 0x00}, + {WCD_USBSS_LUT_REG123, 0x00}, + {WCD_USBSS_LUT_REG124, 0x00}, + {WCD_USBSS_LUT_REG125, 0x00}, + {WCD_USBSS_LUT_REG126, 0x00}, + {WCD_USBSS_LUT_REG127, 0x00}, + {WCD_USBSS_LUT_REG128, 0x00}, + {WCD_USBSS_LUT_REG129, 0x00}, + {WCD_USBSS_LUT_REG130, 0x00}, + {WCD_USBSS_LUT_REG131, 0x00}, + {WCD_USBSS_LUT_REG132, 0x00}, + {WCD_USBSS_LUT_REG133, 0x00}, + {WCD_USBSS_LUT_REG134, 0x00}, + {WCD_USBSS_LUT_REG135, 0x00}, + {WCD_USBSS_LUT_REG136, 0x00}, + {WCD_USBSS_LUT_REG137, 0x00}, + {WCD_USBSS_LUT_REG138, 0x00}, + {WCD_USBSS_LUT_REG139, 0x00}, + {WCD_USBSS_LUT_REG140, 0x00}, + {WCD_USBSS_LUT_REG141, 0x00}, + {WCD_USBSS_LUT_REG142, 0x00}, + {WCD_USBSS_LUT_REG143, 0x00}, + {WCD_USBSS_LUT_REG144, 0x00}, + {WCD_USBSS_LUT_REG145, 0x00}, + {WCD_USBSS_LUT_REG146, 0x00}, + {WCD_USBSS_LUT_REG147, 0x00}, + {WCD_USBSS_LUT_REG148, 0x00}, + {WCD_USBSS_LUT_REG149, 0x00}, + {WCD_USBSS_LUT_REG150, 0x00}, + {WCD_USBSS_LUT_REG151, 0x00}, + {WCD_USBSS_LUT_REG152, 0x00}, + {WCD_USBSS_LUT_REG153, 0x00}, + {WCD_USBSS_LUT_REG154, 0x00}, + {WCD_USBSS_LUT_REG155, 0x00}, + {WCD_USBSS_LUT_REG156, 0x00}, + {WCD_USBSS_LUT_REG157, 0x00}, + {WCD_USBSS_LUT_REG158, 0x00}, + {WCD_USBSS_LUT_REG159, 0x00}, + {WCD_USBSS_LUT_REG160, 0x00}, + {WCD_USBSS_LUT_REG161, 0x00}, + {WCD_USBSS_LUT_REG162, 0x00}, + {WCD_USBSS_LUT_REG163, 0x00}, + {WCD_USBSS_LUT_REG164, 0x00}, + {WCD_USBSS_LUT_REG165, 0x00}, + {WCD_USBSS_LUT_REG166, 0x00}, + {WCD_USBSS_LUT_REG167, 0x00}, + {WCD_USBSS_LUT_REG168, 0x00}, + {WCD_USBSS_LUT_REG169, 0x00}, + {WCD_USBSS_LUT_REG170, 0x00}, + {WCD_USBSS_LUT_REG171, 0x00}, + {WCD_USBSS_LUT_REG172, 0x00}, + {WCD_USBSS_LUT_REG173, 0x00}, + {WCD_USBSS_LUT_REG174, 0x00}, + {WCD_USBSS_LUT_REG175, 0x00}, + {WCD_USBSS_LUT_REG176, 0x00}, + {WCD_USBSS_LUT_REG177, 0x00}, + {WCD_USBSS_LUT_REG178, 0x00}, + {WCD_USBSS_LUT_REG179, 0x00}, + {WCD_USBSS_LUT_REG180, 0x00}, + {WCD_USBSS_LUT_REG181, 0x00}, + {WCD_USBSS_LUT_REG182, 0x00}, + {WCD_USBSS_LUT_REG183, 0x00}, + {WCD_USBSS_LUT_REG184, 0x00}, + {WCD_USBSS_LUT_REG185, 0x00}, + {WCD_USBSS_LUT_REG186, 0x00}, + {WCD_USBSS_LUT_REG187, 0x00}, + {WCD_USBSS_LUT_REG188, 0x00}, + {WCD_USBSS_LUT_REG189, 0x00}, + {WCD_USBSS_LUT_REG190, 0x00}, + {WCD_USBSS_LUT_REG191, 0x00}, + {WCD_USBSS_LUT_REG192, 0x00}, + {WCD_USBSS_LUT_REG193, 0x00}, + {WCD_USBSS_LUT_REG194, 0x00}, + {WCD_USBSS_LUT_REG195, 0x00}, + {WCD_USBSS_LUT_REG196, 0x00}, + {WCD_USBSS_LUT_REG197, 0x00}, + {WCD_USBSS_LUT_REG198, 0x00}, + {WCD_USBSS_LUT_REG199, 0x00}, + {WCD_USBSS_LUT_REG200, 0x00}, + {WCD_USBSS_LUT_REG201, 0x00}, + {WCD_USBSS_LUT_REG202, 0x00}, + {WCD_USBSS_LUT_REG203, 0x00}, + {WCD_USBSS_LUT_REG204, 0x00}, + {WCD_USBSS_LUT_REG205, 0x00}, + {WCD_USBSS_LUT_REG206, 0x00}, + {WCD_USBSS_LUT_REG207, 0x00}, + {WCD_USBSS_LUT_REG208, 0x00}, + {WCD_USBSS_LUT_REG209, 0x00}, + {WCD_USBSS_LUT_REG210, 0x00}, + {WCD_USBSS_DATA_SEL, 0x2b}, + {WCD_USBSS_OFF3, 0x00}, + {WCD_USBSS_OFF2_LSB, 0x78}, + {WCD_USBSS_OFF2_MSB, 0x01}, + {WCD_USBSS_OFF1_LSB, 0x7f}, + {WCD_USBSS_OFF1_MSB, 0x01}, + {WCD_USBSS_AUD_L, 0x00}, + {WCD_USBSS_AUD_R, 0x00}, + {WCD_USBSS_GND_L, 0x00}, + {WCD_USBSS_GND_R, 0x00}, + {WCD_USBSS_USB_DIG_PAGE, 0x00}, + {WCD_USBSS_OVP_STATUS_SELF_CLEARING, 0x00}, + {WCD_USBSS_OVP_STATUS, 0x00}, + {WCD_USBSS_SWITCH_SETTINGS_ENABLE, 0x98}, + {WCD_USBSS_SWITCH_SELECT0, 0x14}, + {WCD_USBSS_SWITCH_SELECT1, 0x00}, + {WCD_USBSS_SWITCH_STATUS0, 0x00}, + {WCD_USBSS_SWITCH_STATUS1, 0x00}, + {WCD_USBSS_AUD_LEFT_SW_SLOW, 0x01}, + {WCD_USBSS_AUD_RIGHT_SW_SLOW, 0x01}, + {WCD_USBSS_AUD_MIC_SW_SLOW, 0x01}, + {WCD_USBSS_AUD_SENSE_SW_SLOW, 0x01}, + {WCD_USBSS_AUD_GND_SW_SLOW, 0x01}, + {WCD_USBSS_DELAY_R_SW, 0x00}, + {WCD_USBSS_DELAY_MIC_SW, 0x00}, + {WCD_USBSS_DELAY_SENSE_SW, 0x00}, + {WCD_USBSS_DELAY_GND_SW, 0x00}, + {WCD_USBSS_DELAY_L_SW, 0x00}, + {WCD_USBSS_EXT_FET_ENABLE_DELAY, 0x0f}, + {WCD_USBSS_FUNCTION_ENABLE, 0x01}, + {WCD_USBSS_USB_RST_CTL, 0x03}, + {WCD_USBSS_EQUALIZER1, 0xc0}, + {WCD_USBSS_SPARE_0, 0x00}, + {WCD_USBSS_DIG_FUNCTIONS_STATUS, 0x00}, + {WCD_USBSS_CLK_SOURCE, 0x00}, + {WCD_USBSS_USB_SS_CNTL, 0x0d}, + {WCD_USBSS_SPARE_1, 0x00}, + {WCD_USBSS_ANA_FUNCTIONS_STATUS, 0x00}, + {WCD_USBSS_FSM_STATUS, 0x00}, + {WCD_USBSS_SPARE_14, 0x00}, + {WCD_USBSS_SAFE_STATE_PD_DPAUX, 0x00}, + {WCD_USBSS_AUDIO_FSM_START, 0x00}, + {WCD_USBSS_FSM_RESET, 0x00}, + {WCD_USBSS_CHIP_ID0, 0x00}, + {WCD_USBSS_CHIP_ID1, 0x00}, + {WCD_USBSS_CHIP_ID2, 0x01}, + {WCD_USBSS_CHIP_ID3, 0x03}, + {WCD_USBSS_LINEARIZER_CFG, 0x00}, + {WCD_USBSS_RATIO_SPKR_REXT_L_LSB, 0x8f}, + {WCD_USBSS_RATIO_SPKR_REXT_L_MSB, 0x02}, + {WCD_USBSS_RATIO_SPKR_REXT_R_LSB, 0x8f}, + {WCD_USBSS_RATIO_SPKR_REXT_R_MSB, 0x02}, + {WCD_USBSS_SW_TAP_AUD_L_LSB, 0xd4}, + {WCD_USBSS_SW_TAP_AUD_L_MSB, 0x03}, + {WCD_USBSS_SW_TAP_AUD_R_LSB, 0xd4}, + {WCD_USBSS_SW_TAP_AUD_R_MSB, 0x03}, + {WCD_USBSS_SW_TAP_GND_L_LSB, 0x11}, + {WCD_USBSS_SW_TAP_GND_L_MSB, 0x00}, + {WCD_USBSS_SW_TAP_GND_R_LSB, 0x11}, + {WCD_USBSS_SW_TAP_GND_R_MSB, 0x00}, + {WCD_USBSS_HW_TAP_AUD_L_LSB, 0x00}, + {WCD_USBSS_HW_TAP_AUD_L_MSB, 0x00}, + {WCD_USBSS_HW_TAP_AUD_R_LSB, 0x00}, + {WCD_USBSS_HW_TAP_AUD_R_MSB, 0x00}, + {WCD_USBSS_HW_TAP_GND_L_LSB, 0x00}, + {WCD_USBSS_HW_TAP_GND_L_MSB, 0x00}, + {WCD_USBSS_HW_TAP_GND_R_LSB, 0x00}, + {WCD_USBSS_HW_TAP_GND_R_MSB, 0x00}, + {WCD_USBSS_AUD_COEF_L_K0_0, 0xd3}, + {WCD_USBSS_AUD_COEF_L_K0_1, 0x9e}, + {WCD_USBSS_AUD_COEF_L_K0_2, 0x3f}, + {WCD_USBSS_AUD_COEF_L_K1_0, 0x15}, + {WCD_USBSS_AUD_COEF_L_K1_1, 0xfd}, + {WCD_USBSS_AUD_COEF_L_K2_0, 0x7a}, + {WCD_USBSS_AUD_COEF_L_K2_1, 0x05}, + {WCD_USBSS_AUD_COEF_L_K3_0, 0x6e}, + {WCD_USBSS_AUD_COEF_L_K3_1, 0xf5}, + {WCD_USBSS_AUD_COEF_L_K4_0, 0xd1}, + {WCD_USBSS_AUD_COEF_L_K4_1, 0x0e}, + {WCD_USBSS_AUD_COEF_L_K5_0, 0x24}, + {WCD_USBSS_AUD_COEF_L_K5_1, 0xf6}, + {WCD_USBSS_AUD_COEF_R_K0_0, 0xd3}, + {WCD_USBSS_AUD_COEF_R_K0_1, 0x9e}, + {WCD_USBSS_AUD_COEF_R_K0_2, 0x3f}, + {WCD_USBSS_AUD_COEF_R_K1_0, 0x15}, + {WCD_USBSS_AUD_COEF_R_K1_1, 0xfd}, + {WCD_USBSS_AUD_COEF_R_K2_0, 0x7a}, + {WCD_USBSS_AUD_COEF_R_K2_1, 0x05}, + {WCD_USBSS_AUD_COEF_R_K3_0, 0x6e}, + {WCD_USBSS_AUD_COEF_R_K3_1, 0xf5}, + {WCD_USBSS_AUD_COEF_R_K4_0, 0xd1}, + {WCD_USBSS_AUD_COEF_R_K4_1, 0x0e}, + {WCD_USBSS_AUD_COEF_R_K5_0, 0x24}, + {WCD_USBSS_AUD_COEF_R_K5_1, 0xf6}, + {WCD_USBSS_GND_COEF_L_K0_0, 0xf4}, + {WCD_USBSS_GND_COEF_L_K0_1, 0x30}, + {WCD_USBSS_GND_COEF_L_K0_2, 0x00}, + {WCD_USBSS_GND_COEF_L_K1_0, 0xe9}, + {WCD_USBSS_GND_COEF_L_K1_1, 0x02}, + {WCD_USBSS_GND_COEF_L_K2_0, 0xe7}, + {WCD_USBSS_GND_COEF_L_K2_1, 0xf7}, + {WCD_USBSS_GND_COEF_L_K3_0, 0x7a}, + {WCD_USBSS_GND_COEF_L_K3_1, 0x12}, + {WCD_USBSS_GND_COEF_L_K4_0, 0x72}, + {WCD_USBSS_GND_COEF_L_K4_1, 0xe4}, + {WCD_USBSS_GND_COEF_L_K5_0, 0xa0}, + {WCD_USBSS_GND_COEF_L_K5_1, 0x12}, + {WCD_USBSS_GND_COEF_R_K0_0, 0xf4}, + {WCD_USBSS_GND_COEF_R_K0_1, 0x30}, + {WCD_USBSS_GND_COEF_R_K0_2, 0x00}, + {WCD_USBSS_GND_COEF_R_K1_0, 0xe9}, + {WCD_USBSS_GND_COEF_R_K1_1, 0x02}, + {WCD_USBSS_GND_COEF_R_K2_0, 0xe7}, + {WCD_USBSS_GND_COEF_R_K2_1, 0xf7}, + {WCD_USBSS_GND_COEF_R_K3_0, 0x7a}, + {WCD_USBSS_GND_COEF_R_K3_1, 0x12}, + {WCD_USBSS_GND_COEF_R_K4_0, 0x72}, + {WCD_USBSS_GND_COEF_R_K4_1, 0xe4}, + {WCD_USBSS_GND_COEF_R_K5_0, 0xa0}, + {WCD_USBSS_GND_COEF_R_K5_1, 0x12}, + {WCD_USBSS_AUD_L_SLOPE_SCALE_LSB, 0xe8}, + {WCD_USBSS_AUD_L_SLOPE_SCALE_MSB, 0x03}, + {WCD_USBSS_AUD_R_SLOPE_SCALE_LSB, 0xe8}, + {WCD_USBSS_AUD_R_SLOPE_SCALE_MSB, 0x03}, + {WCD_USBSS_GND_L_SLOPE_SCALE_LSB, 0xe8}, + {WCD_USBSS_GND_L_SLOPE_SCALE_MSB, 0x03}, + {WCD_USBSS_GND_R_SLOPE_SCALE_LSB, 0xe8}, + {WCD_USBSS_GND_R_SLOPE_SCALE_MSB, 0x03}, + {WCD_USBSS_AUD_L_FIRST_TAP, 0x00}, + {WCD_USBSS_AUD_R_FIRST_TAP, 0x00}, + {WCD_USBSS_GND_L_FIRST_TAP, 0x00}, + {WCD_USBSS_GND_R_FIRST_TAP, 0x00}, + {WCD_USBSS_FEATURE_SELECTION, 0x00}, + {WCD_USBSS_EFUSE_REG_0, 0x00}, + {WCD_USBSS_EFUSE_REG_1, 0x00}, + {WCD_USBSS_EFUSE_REG_2, 0x00}, + {WCD_USBSS_EFUSE_REG_3, 0x00}, + {WCD_USBSS_EFUSE_REG_4, 0x00}, + {WCD_USBSS_EFUSE_REG_5, 0x00}, + {WCD_USBSS_EFUSE_REG_6, 0x00}, + {WCD_USBSS_EFUSE_REG_7, 0x00}, + {WCD_USBSS_EFUSE_REG_8, 0x00}, + {WCD_USBSS_EFUSE_REG_9, 0x00}, + {WCD_USBSS_EFUSE_REG_10, 0x00}, + {WCD_USBSS_EFUSE_REG_11, 0x00}, + {WCD_USBSS_EFUSE_REG_12, 0x00}, + {WCD_USBSS_EFUSE_REG_13, 0x00}, + {WCD_USBSS_EFUSE_REG_14, 0x00}, + {WCD_USBSS_EFUSE_REG_15, 0x00}, + {WCD_USBSS_EFUSE_PRG_CTL, 0x00}, +}; + +static bool wcd_usbss_readable_register(struct device *dev, unsigned int reg) +{ + if (reg <= (WCD_USBSS_BASE + 1)) + return false; + + return wcd_usbss_reg_access[WCD_USBSS_REG(reg)] & RD_REG; +} + +static bool wcd_usbss_writeable_register(struct device *dev, unsigned int reg) +{ + if (reg <= (WCD_USBSS_BASE + 1)) + return false; + + return wcd_usbss_reg_access[WCD_USBSS_REG(reg)] & WR_REG; +} + +static bool wcd_usbss_volatile_register(struct device *dev, unsigned int reg) +{ + if (reg <= (WCD_USBSS_BASE + 1)) + return false; + + return ((wcd_usbss_reg_access[WCD_USBSS_REG(reg)] & RD_REG) && + !(wcd_usbss_reg_access[WCD_USBSS_REG(reg)] & WR_REG)); +} + +struct regmap_config wcd_usbss_regmap_config = { + .reg_bits = 16, + .val_bits = 8, + .cache_type = REGCACHE_RBTREE, + .reg_defaults = wcd_usbss_defaults, + .num_reg_defaults = ARRAY_SIZE(wcd_usbss_defaults), + .max_register = WCD_USBSS_MAX_REGISTER, + .volatile_reg = wcd_usbss_volatile_register, + .readable_reg = wcd_usbss_readable_register, + .writeable_reg = wcd_usbss_writeable_register, + .reg_format_endian = REGMAP_ENDIAN_NATIVE, + .val_format_endian = REGMAP_ENDIAN_NATIVE, +}; diff --git a/drivers/soc/qcom/wcd-usbss-tables.c b/drivers/soc/qcom/wcd-usbss-tables.c new file mode 100644 index 000000000000..e210f6e28c46 --- /dev/null +++ b/drivers/soc/qcom/wcd-usbss-tables.c @@ -0,0 +1,463 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include "wcd-usbss-registers.h" + +const u8 wcd_usbss_reg_access[WCD_USBSS_NUM_REGISTERS] = { + [WCD_USBSS_REG(WCD_USBSS_PAGE0_PAGE)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_PMP_EN)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_PMP_OUT1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_PMP_OUT2)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_PMP_CLK)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_PMP_MISC1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_PMP_MISC2)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_RCO_EN)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_RCO_RST)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_RCO_CLK)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_RCO_IBIAS)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_RCO_MISC1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_RCO_MISC2)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_DP_EN)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_DP_BIAS)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_DP_DN_MISC1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_DN_EN)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_DN_BIAS)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_DP_DN_MISC2)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_MG1_EN)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_MG1_BIAS)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_MG1_CTSNS_CTL)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_MG1_MISC)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_MG2_EN)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_MG2_BIAS)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_MG2_CTSNS_CTL)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_MG2_MISC)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_BIAS_TOP)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_VREF_CTRL)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_TOP_MISC1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_TOP_MISC2)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_STATUS_1)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_STATUS_2)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_STATUS_3)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_EXT_LIN_EN)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_INT_LIN_EN)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_COMBINER_IREF_PROG_1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_COMBINER_IREF_PROG_2)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_EXTSW_AMP_BIAS)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_INTSW_ILIFT)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_EXT_SW_CTRL_1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_EXT_SW_CTRL_2)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_INT_SW_CTRL_1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_INT_SW_CTRL_2)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_INT_SW_CTRL_3)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_ATEST_CTRL)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_EXT_LIN_AUD_CEQ_PRG)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_EXT_LIN_GND_CEQ_PRG)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LIN_STATUS_1)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_LIN_STATUS_2)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_LIN_STATUS_3)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_LIN_STATUS_4)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_SW_LIN_CTRL)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_SW_LIN_CTRL_1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LDO_3P6)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_SWITCH_BANK_ATEST)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_EQ_EN)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_EQ_MISC)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_STATUS_MISC)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_FSM_DELAYS1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_FSM_DELAYS2)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_FSM_DELAYS3)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_FSM_DELAYS4)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_FSM_DELAYS5)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_FSM_DELAYS6)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_FSM_DELAYS7)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_FSM_DELAYS8)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_FSM_DEBUG_SIGNALS)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_FSM_OVERRIDE)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_ENABLE_STATUS)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_FRZ_STATUS)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_DPR_DNL_SWITCH_ENABLE_STATUS)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_SBU_GSBU_SWITCH_ENABLE_STATUS)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_DPAUX_SWITCH_ENABLE_STATUS)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_DPR_DNL_EXTFET_GATE_MUX_STATUS)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_SBU_EXTFET_GATE_MUX_OVP_STATUS)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_CP_LIN_CNTL_STATUS)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_DISP_AUXP_THRESH)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_DISP_AUXP_CTL)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_DISP_AUXM_THRESH)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_DISP_AUXM_CTL)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_CTRL_0)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_CTRL_1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_DC_TRIMCODE_1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_DC_TRIMCODE_2)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_DC_TRIMCODE_3)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AC_TRIMCODE_1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AC_TRIMCODE_2)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_CPLDO_CTL1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_CPLDO_CTL2)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG0)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG2)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG3)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG4)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG5)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG6)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG7)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG8)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG9)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG10)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG11)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG12)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG13)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG14)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG15)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG16)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG17)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG18)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG19)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG20)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG21)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG22)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG23)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG24)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG25)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG26)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG27)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG28)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG29)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG30)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG31)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG32)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG33)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG34)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG35)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG36)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG37)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG38)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG39)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG40)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG41)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG42)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG43)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG44)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG45)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG46)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG47)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG48)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG49)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG50)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG51)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG52)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG53)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG54)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG55)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG56)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG57)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG58)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG59)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG60)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG61)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG62)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG63)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG64)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG65)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG66)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG67)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG68)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG69)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG70)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG71)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG72)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG73)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG74)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG75)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG76)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG77)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG78)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG79)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG80)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG81)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG82)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG83)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG84)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG85)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG86)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG87)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG88)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG89)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG90)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG91)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG92)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG93)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG94)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG95)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG96)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG97)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG98)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG99)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG100)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG101)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG102)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG103)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG104)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG105)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG106)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG107)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG108)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG109)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG110)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG111)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG112)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG113)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG114)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG115)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG116)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG117)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG118)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG119)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG120)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG121)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG122)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG123)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG124)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG125)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG126)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG127)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG128)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG129)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG130)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG131)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG132)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG133)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG134)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG135)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG136)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG137)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG138)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG139)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG140)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG141)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG142)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG143)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG144)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG145)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG146)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG147)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG148)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG149)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG150)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG151)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG152)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG153)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG154)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG155)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG156)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG157)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG158)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG159)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG160)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG161)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG162)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG163)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG164)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG165)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG166)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG167)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG168)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG169)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG170)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG171)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG172)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG173)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG174)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG175)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG176)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG177)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG178)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG179)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG180)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG181)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG182)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG183)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG184)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG185)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG186)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG187)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG188)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG189)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG190)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG191)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG192)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG193)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG194)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG195)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG196)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG197)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG198)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG199)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG200)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG201)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG202)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG203)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG204)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG205)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG206)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG207)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG208)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG209)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_LUT_REG210)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_DATA_SEL)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_OFF3)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_OFF2_LSB)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_OFF2_MSB)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_OFF1_LSB)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_OFF1_MSB)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_L)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_R)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_GND_L)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_GND_R)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_USB_DIG_PAGE)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_OVP_STATUS_SELF_CLEARING)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_OVP_STATUS)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_SWITCH_SETTINGS_ENABLE)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_SWITCH_SELECT0)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_SWITCH_SELECT1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_SWITCH_STATUS0)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_SWITCH_STATUS1)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_LEFT_SW_SLOW)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_RIGHT_SW_SLOW)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_MIC_SW_SLOW)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_SENSE_SW_SLOW)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_GND_SW_SLOW)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_DELAY_R_SW)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_DELAY_MIC_SW)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_DELAY_SENSE_SW)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_DELAY_GND_SW)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_DELAY_L_SW)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_EXT_FET_ENABLE_DELAY)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_FUNCTION_ENABLE)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_USB_RST_CTL)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_EQUALIZER1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_SPARE_0)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_DIG_FUNCTIONS_STATUS)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_CLK_SOURCE)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_USB_SS_CNTL)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_SPARE_1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_ANA_FUNCTIONS_STATUS)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_FSM_STATUS)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_SPARE_14)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_SAFE_STATE_PD_DPAUX)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AUDIO_FSM_START)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_FSM_RESET)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_CHIP_ID0)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_CHIP_ID1)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_CHIP_ID2)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_CHIP_ID3)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_LINEARIZER_CFG)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_RATIO_SPKR_REXT_L_LSB)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_RATIO_SPKR_REXT_L_MSB)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_RATIO_SPKR_REXT_R_LSB)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_RATIO_SPKR_REXT_R_MSB)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_SW_TAP_AUD_L_LSB)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_SW_TAP_AUD_L_MSB)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_SW_TAP_AUD_R_LSB)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_SW_TAP_AUD_R_MSB)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_SW_TAP_GND_L_LSB)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_SW_TAP_GND_L_MSB)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_SW_TAP_GND_R_LSB)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_SW_TAP_GND_R_MSB)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_HW_TAP_AUD_L_LSB)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_HW_TAP_AUD_L_MSB)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_HW_TAP_AUD_R_LSB)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_HW_TAP_AUD_R_MSB)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_HW_TAP_GND_L_LSB)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_HW_TAP_GND_L_MSB)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_HW_TAP_GND_R_LSB)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_HW_TAP_GND_R_MSB)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_COEF_L_K0_0)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_COEF_L_K0_1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_COEF_L_K0_2)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_COEF_L_K1_0)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_COEF_L_K1_1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_COEF_L_K2_0)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_COEF_L_K2_1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_COEF_L_K3_0)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_COEF_L_K3_1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_COEF_L_K4_0)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_COEF_L_K4_1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_COEF_L_K5_0)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_COEF_L_K5_1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_COEF_R_K0_0)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_COEF_R_K0_1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_COEF_R_K0_2)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_COEF_R_K1_0)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_COEF_R_K1_1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_COEF_R_K2_0)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_COEF_R_K2_1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_COEF_R_K3_0)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_COEF_R_K3_1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_COEF_R_K4_0)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_COEF_R_K4_1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_COEF_R_K5_0)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_COEF_R_K5_1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_GND_COEF_L_K0_0)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_GND_COEF_L_K0_1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_GND_COEF_L_K0_2)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_GND_COEF_L_K1_0)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_GND_COEF_L_K1_1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_GND_COEF_L_K2_0)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_GND_COEF_L_K2_1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_GND_COEF_L_K3_0)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_GND_COEF_L_K3_1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_GND_COEF_L_K4_0)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_GND_COEF_L_K4_1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_GND_COEF_L_K5_0)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_GND_COEF_L_K5_1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_GND_COEF_R_K0_0)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_GND_COEF_R_K0_1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_GND_COEF_R_K0_2)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_GND_COEF_R_K1_0)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_GND_COEF_R_K1_1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_GND_COEF_R_K2_0)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_GND_COEF_R_K2_1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_GND_COEF_R_K3_0)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_GND_COEF_R_K3_1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_GND_COEF_R_K4_0)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_GND_COEF_R_K4_1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_GND_COEF_R_K5_0)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_GND_COEF_R_K5_1)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_L_SLOPE_SCALE_LSB)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_L_SLOPE_SCALE_MSB)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_R_SLOPE_SCALE_LSB)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_R_SLOPE_SCALE_MSB)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_GND_L_SLOPE_SCALE_LSB)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_GND_L_SLOPE_SCALE_MSB)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_GND_R_SLOPE_SCALE_LSB)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_GND_R_SLOPE_SCALE_MSB)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_L_FIRST_TAP)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_AUD_R_FIRST_TAP)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_GND_L_FIRST_TAP)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_GND_R_FIRST_TAP)] = RD_WR_REG, + [WCD_USBSS_REG(WCD_USBSS_FEATURE_SELECTION)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_EFUSE_REG_0)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_EFUSE_REG_1)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_EFUSE_REG_2)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_EFUSE_REG_3)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_EFUSE_REG_4)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_EFUSE_REG_5)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_EFUSE_REG_6)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_EFUSE_REG_7)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_EFUSE_REG_8)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_EFUSE_REG_9)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_EFUSE_REG_10)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_EFUSE_REG_11)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_EFUSE_REG_12)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_EFUSE_REG_13)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_EFUSE_REG_14)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_EFUSE_REG_15)] = RD_REG, + [WCD_USBSS_REG(WCD_USBSS_EFUSE_PRG_CTL)] = RD_WR_REG, +}; + diff --git a/drivers/soc/qcom/wcd-usbss-utils.c b/drivers/soc/qcom/wcd-usbss-utils.c new file mode 100644 index 000000000000..a0ab344b5edd --- /dev/null +++ b/drivers/soc/qcom/wcd-usbss-utils.c @@ -0,0 +1,272 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include "wcd-usbss-priv.h" + +#define REG_BYTES 2 +#define VAL_BYTES 1 +#define PAGE_REG_ADDR 0x00 + +static int wcd_usbss_i2c_write_device(struct wcd_usbss_ctxt *ctxt, u16 reg, u8 *value, + u32 bytes) +{ + struct i2c_msg *msg, xfer_msg[2]; + int ret = 0; + u8 reg_addr = 0; + u8 *data = NULL; + struct i2c_client *client = NULL; + + if (ctxt == NULL || ctxt->client == NULL) + return -ENODEV; + + client = ctxt->client; + data = kzalloc(bytes + 1, GFP_KERNEL); + if (!data) + return -ENOMEM; + + reg_addr = (u8)reg; + msg = &xfer_msg[0]; + msg->addr = client->addr; + msg->len = bytes + 1; + msg->flags = 0; + data[0] = reg; + data[1] = *value; + msg->buf = data; + ret = i2c_transfer(client->adapter, xfer_msg, 1); + /* Try again if the write fails */ + if (ret != 1) { + ret = i2c_transfer(client->adapter, xfer_msg, 1); + if (ret != 1) { + pr_err("failed to write the device\n"); + goto fail; + } + } + pr_debug("write success register = %x val = %x\n", reg, data[1]); +fail: + kfree(data); + return ret; +} + + +static int wcd_usbss_i2c_read_device(struct wcd_usbss_ctxt *ctxt, unsigned short reg, + int bytes, unsigned char *dest) +{ + struct i2c_msg *msg, xfer_msg[2]; + int ret = 0; + u8 reg_addr = 0; + u8 i = 0; + struct i2c_client *client = NULL; + + if (ctxt == NULL || ctxt->client == NULL) + return -ENODEV; + + client = ctxt->client; + for (i = 0; i < bytes; i++) { + reg_addr = (u8)reg++; + msg = &xfer_msg[0]; + msg->addr = client->addr; + msg->len = 1; + msg->flags = 0; + msg->buf = ®_addr; + + msg = &xfer_msg[1]; + msg->addr = client->addr; + msg->len = 1; + msg->flags = I2C_M_RD; + msg->buf = dest++; + ret = i2c_transfer(client->adapter, xfer_msg, 2); + + /* Try again if read fails first time */ + if (ret != 2) { + ret = i2c_transfer(client->adapter, xfer_msg, 2); + if (ret != 2) { + pr_err("failed to read wcd usbss register\n"); + return ret; + } + } + } + return 0; +} + +/* + * wcd_usbss_page_write: + * Retrieve page number from register and + * write that page number to the page address. + * + * @ctxt: pointer to wcd_usbss_ctxt + * @reg: Register address from which page number is retrieved + * + * Returns 0 for success and negative error code for failure. + */ +static int wcd_usbss_page_write(struct wcd_usbss_ctxt *ctxt, unsigned short *reg) +{ + int ret = 0; + unsigned short c_reg = 0, reg_addr = 0; + u8 pg_num = 0, prev_pg_num = 0; + + c_reg = *reg; + pg_num = c_reg >> 8; + reg_addr = c_reg & 0xff; + if (ctxt->prev_pg_valid) { + prev_pg_num = ctxt->prev_pg; + if (prev_pg_num != pg_num) { + ret = wcd_usbss_i2c_write_device( + ctxt, PAGE_REG_ADDR, (void *) &pg_num, 1); + if (ret < 0) { + dev_err(ctxt->dev, "page write error, pg_num: 0x%x\n", pg_num); + } else { + ctxt->prev_pg = pg_num; + dev_dbg(ctxt->dev, "Page 0x%x Write to 0x00\n", pg_num); + } + } + } else { + ret = wcd_usbss_i2c_write_device( + ctxt, PAGE_REG_ADDR, (void *) &pg_num, 1); + if (ret < 0) { + pr_err("page write error, pg_num: 0x%x\n", pg_num); + } else { + ctxt->prev_pg = pg_num; + ctxt->prev_pg_valid = true; + dev_dbg(ctxt->dev, "Page 0x%x Write to 0x00\n", pg_num); + } + } + *reg = reg_addr; + return ret; +} + +static int regmap_bus_read(void *context, const void *reg, size_t reg_size, + void *val, size_t val_size) +{ + struct device *dev = context; + struct wcd_usbss_ctxt *ctxt = dev_get_drvdata(dev); + unsigned short c_reg = 0, rreg = 0; + int ret = 0, i; + + if (!ctxt) { + dev_err(dev, "%s: ctxt is NULL\n", __func__); + return -EINVAL; + } + if (!reg || !val) { + dev_err(dev, "%s: reg or val is NULL\n", __func__); + return -EINVAL; + } + + if (reg_size != REG_BYTES) { + dev_err(dev, "%s: register size %zd bytes, not supported\n", + __func__, reg_size); + return -EINVAL; + } + + mutex_lock(&ctxt->io_lock); + c_reg = *(u16 *)reg; + rreg = c_reg; + + ret = wcd_usbss_page_write(ctxt, &c_reg); + if (ret) + goto err; + ret = wcd_usbss_i2c_read_device(ctxt, c_reg, val_size, val); + if (ret < 0) + dev_err(dev, "%s: Codec read failed (%d), reg: 0x%x, size:%zd\n", + __func__, ret, rreg, val_size); + else { + for (i = 0; i < val_size; i++) + dev_dbg(dev, "%s: Read 0x%02x from 0x%x\n", + __func__, ((u8 *)val)[i], rreg + i); + } +err: + mutex_unlock(&ctxt->io_lock); + + return ret; +} + +static int regmap_bus_gather_write(void *context, + const void *reg, size_t reg_size, + const void *val, size_t val_size) +{ + struct device *dev = context; + struct wcd_usbss_ctxt *ctxt = dev_get_drvdata(dev); + unsigned short c_reg, rreg; + int ret, i; + + if (!ctxt) { + dev_err(dev, "%s: ctxt is NULL\n", __func__); + return -EINVAL; + } + if (!reg || !val) { + dev_err(dev, "%s: reg or val is NULL\n", __func__); + return -EINVAL; + } + if (reg_size != REG_BYTES) { + dev_err(dev, "%s: register size %zd bytes, not supported\n", + __func__, reg_size); + return -EINVAL; + } + mutex_lock(&ctxt->io_lock); + c_reg = *(u16 *)reg; + rreg = c_reg; + + ret = wcd_usbss_page_write(ctxt, &c_reg); + if (ret) + goto err; + + for (i = 0; i < val_size; i++) + dev_dbg(dev, "Write %02x to 0x%x\n", ((u8 *)val)[i], + rreg + i); + + ret = wcd_usbss_i2c_write_device(ctxt, c_reg, (void *) val, val_size); + if (ret < 0) + dev_err(dev, "%s: Codec write failed (%d), reg:0x%x, size:%zd\n", + __func__, ret, rreg, val_size); + +err: + mutex_unlock(&ctxt->io_lock); + return ret; +} + +static int regmap_bus_write(void *context, const void *data, size_t count) +{ + struct device *dev = context; + struct wcd_usbss_ctxt *ctxt = dev_get_drvdata(dev); + + if (!ctxt) + return -EINVAL; + + WARN_ON(count < REG_BYTES); + WARN_ON(count > (REG_BYTES + VAL_BYTES)); + + if (count <= (REG_BYTES + VAL_BYTES)) + return regmap_bus_gather_write(context, data, REG_BYTES, + data + REG_BYTES, + count - REG_BYTES); + + return -EINVAL; +} + +static struct regmap_bus regmap_bus_config = { + .write = regmap_bus_write, + .gather_write = regmap_bus_gather_write, + .read = regmap_bus_read, + .reg_format_endian_default = REGMAP_ENDIAN_NATIVE, + .val_format_endian_default = REGMAP_ENDIAN_NATIVE, +}; + +/* + * wcd_usbss_regmap_init: + * Initialize wcd_usbss register map + * + * @dev: pointer to wcd usbss i2c device + * @config: pointer to register map config + * + * Returns pointer to regmap structure for success + * or NULL in case of failure. + */ +struct regmap *wcd_usbss_regmap_init(struct device *dev, + const struct regmap_config *config) +{ + return devm_regmap_init(dev, ®map_bus_config, dev, config); +} +EXPORT_SYMBOL(wcd_usbss_regmap_init); diff --git a/drivers/soc/qcom/wcd939x-i2c.c b/drivers/soc/qcom/wcd939x-i2c.c new file mode 100644 index 000000000000..1cdd6e76f89b --- /dev/null +++ b/drivers/soc/qcom/wcd939x-i2c.c @@ -0,0 +1,588 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include "wcd-usbss-priv.h" +#include "wcd-usbss-registers.h" +#include "wcd-usbss-reg-masks.h" +#include "wcd-usbss-reg-shifts.h" + +#define WCD_USBSS_I2C_NAME "wcd-usbss-i2c-driver" + +enum { + WCD_USBSS_AUDIO_MANUAL, + WCD_USBSS_AUDIO_FSM, +}; + +struct wcd_usbss_reg_mask_val { + u16 reg; + u8 mask; + u8 val; +}; + +/* regulator power supply names */ +static const char * const supply_names[] = { + "vdd-usb-cp", +}; + +static int audio_fsm_mode = WCD_USBSS_AUDIO_FSM; + +/* Linearlizer coefficients for 32ohm load */ +static const struct wcd_usbss_reg_mask_val coeff_init[] = { + {WCD_USBSS_AUD_COEF_L_K5_0, 0xFF, 0x39}, + {WCD_USBSS_AUD_COEF_R_K5_0, 0xFF, 0x39}, + {WCD_USBSS_GND_COEF_L_K2_0, 0xFF, 0xE8}, + {WCD_USBSS_GND_COEF_L_K4_0, 0xFF, 0x73}, + {WCD_USBSS_GND_COEF_R_K2_0, 0xFF, 0xE8}, + {WCD_USBSS_GND_COEF_R_K4_0, 0xFF, 0x73}, + {WCD_USBSS_RATIO_SPKR_REXT_L_LSB, 0xFF, 0x00}, + {WCD_USBSS_RATIO_SPKR_REXT_L_MSB, 0x7F, 0x04}, + {WCD_USBSS_RATIO_SPKR_REXT_R_LSB, 0xFF, 0x00}, + {WCD_USBSS_RATIO_SPKR_REXT_R_MSB, 0x7F, 0x04}, +}; + +static struct wcd_usbss_ctxt *wcd_usbss_ctxt_; + +static int wcd_usbss_usbc_event_changed(struct notifier_block *nb, + unsigned long evt, void *ptr) +{ + struct wcd_usbss_ctxt *priv = + container_of(nb, struct wcd_usbss_ctxt, ucsi_nb); + struct device *dev; + enum typec_accessory acc = ((struct ucsi_glink_constat_info *)ptr)->acc; + + if (!priv) + return -EINVAL; + + dev = priv->dev; + if (!dev) + return -EINVAL; + + dev_dbg(dev, "%s: USB change event received, supply mode %d, usbc mode %ld, expected %d\n", + __func__, acc, priv->usbc_mode.counter, + TYPEC_ACCESSORY_AUDIO); + + switch (acc) { + case TYPEC_ACCESSORY_AUDIO: + case TYPEC_ACCESSORY_NONE: + if (atomic_read(&(priv->usbc_mode)) == acc) + break; /* filter notifications received before */ + atomic_set(&(priv->usbc_mode), acc); + + dev_dbg(dev, "%s: queueing usbc_analog_work\n", + __func__); + pm_stay_awake(priv->dev); + queue_work(system_freezable_wq, &priv->usbc_analog_work); + break; + default: + break; + } + + return 0; +} + +static int wcd_usbss_usbc_analog_setup_switches(struct wcd_usbss_ctxt *priv) +{ + int rc = 0; + int mode; + struct device *dev; + + if (!priv) + return -EINVAL; + + dev = priv->dev; + if (!dev) + return -EINVAL; + + mutex_lock(&priv->notification_lock); + /* get latest mode again within locked context */ + mode = atomic_read(&(priv->usbc_mode)); + + dev_dbg(dev, "%s: setting GPIOs active = %d\n", + __func__, mode != TYPEC_ACCESSORY_NONE); + + switch (mode) { + /* add all modes WCD USBSS should notify for in here */ + case TYPEC_ACCESSORY_AUDIO: + /* notify call chain on event */ + blocking_notifier_call_chain(&priv->wcd_usbss_notifier, + mode, NULL); + break; + case TYPEC_ACCESSORY_NONE: + /* notify call chain on event */ + blocking_notifier_call_chain(&priv->wcd_usbss_notifier, + TYPEC_ACCESSORY_NONE, NULL); + + break; + default: + /* ignore other usb connection modes */ + break; + } + + mutex_unlock(&priv->notification_lock); + return rc; +} + +static int wcd_usbss_validate_display_port_settings(struct wcd_usbss_ctxt *priv, + enum wcd_usbss_cable_types ctype) +{ + unsigned int sts; + int rc; + + rc = regmap_read(priv->regmap, WCD_USBSS_SWITCH_STATUS1, &sts); + if (rc) + return rc; + + pr_info("Switch Status (MG1/2): %08x\n", sts); + + if (ctype == WCD_USBSS_DP_AUX_CC1 && sts == 0x48) + return 0; + + if (ctype == WCD_USBSS_DP_AUX_CC2 && sts == 0x84) + return 0; + + pr_err("Failed to update switch for display port\n"); + rc = -EINVAL; + + return rc; +} + +static int wcd_usbss_switch_update_defaults(struct wcd_usbss_ctxt *priv) +{ + /* Disable all switches */ + regmap_update_bits(priv->regmap, WCD_USBSS_SWITCH_SETTINGS_ENABLE, 0x7F, 0x00); + /* Select MG1 for AGND_SWITCHES */ + regmap_update_bits(priv->regmap, WCD_USBSS_SWITCH_SELECT1, 0x01, 0x00); + /* Select GSBU1 and MG1 for MIC_SWITCHES */ + regmap_update_bits(priv->regmap, WCD_USBSS_SWITCH_SELECT0, 0x03, 0x00); + regmap_update_bits_base(priv->regmap, WCD_USBSS_AUDIO_FSM_START, 0x01, + 0x01, NULL, false, true); + /* Select DN for DNL_SWITHCES and DP for DPR_SWITCHES */ + regmap_update_bits(priv->regmap, WCD_USBSS_SWITCH_SELECT0, 0x3C, 0x14); + /* Enable DNL_SWITCHES and DPR_SWITCHES */ + regmap_write_bits(priv->regmap, WCD_USBSS_SWITCH_SETTINGS_ENABLE, 0x18, 0x18); + return 0; +} + +static void wcd_usbss_update_reg_init(struct regmap *regmap) +{ + /* update Register Power On Reset values (if any) */ + regmap_update_bits(regmap, WCD_USBSS_USB_SS_CNTL, 0x07, 0x02); /*Mode2*/ + if (audio_fsm_mode == WCD_USBSS_AUDIO_FSM) + regmap_update_bits(regmap, WCD_USBSS_FUNCTION_ENABLE, 0x03, + 0x02); /* AUDIO_FSM mode */ + else + regmap_update_bits(regmap, WCD_USBSS_FUNCTION_ENABLE, 0x03, + 0x01); /* AUDIO_MANUAL mode */ +} + +static int wcd_usbss_display_port_switch_update(struct wcd_usbss_ctxt *priv, + enum wcd_usbss_cable_types ctype) +{ + pr_info("Configuring display port for ctype %d\n", ctype); + + /* Disable all switches */ + regmap_update_bits(priv->regmap, WCD_USBSS_SWITCH_SETTINGS_ENABLE, 0x7F, 0x00); + + /* Select MG1 for AUXP and MG2 for AUXM */ + if (ctype == WCD_USBSS_DP_AUX_CC1) + regmap_update_bits(priv->regmap, WCD_USBSS_SWITCH_SELECT0, 0xC0, 0x40); + /* Select MG2 for AUXP and MG1 for AUXM */ + else + regmap_update_bits(priv->regmap, WCD_USBSS_SWITCH_SELECT0, 0xC0, 0x80); + + /* Enable DP_AUXP_TO_MGX and DP_AUXM_TO_MGX switches */ + regmap_update_bits(priv->regmap, WCD_USBSS_SWITCH_SETTINGS_ENABLE, 0x60, 0x60); + return wcd_usbss_validate_display_port_settings(priv, ctype); +} + +/* to use with DPDM switch selection */ +#define DPDM_SEL_MASK (WCD_USBSS_SWITCH_SELECT0_DPR_SWITCHES_MASK |\ + WCD_USBSS_SWITCH_SELECT0_DNL_SWITCHES_MASK) +#define DPDM_SEL_ENABLE ((0x1 << WCD_USBSS_SWITCH_SELECT0_DPR_SWITCHES_SHIFT) |\ + (0x1 << WCD_USBSS_SWITCH_SELECT0_DNL_SWITCHES_SHIFT)) +#define DPDM_SEL_DISABLE 0x0 + +/* to use with DPDM switch enable/disable*/ +#define DPDM_SW_EN_MASK (WCD_USBSS_SWITCH_SETTINGS_ENABLE_DPR_SWITCHES_MASK |\ + WCD_USBSS_SWITCH_SETTINGS_ENABLE_DNL_SWITCHES_MASK) +#define DPDM_SW_ENABLE ((0x1 << WCD_USBSS_SWITCH_SETTINGS_ENABLE_DNL_SWITCHES_SHIFT) |\ + (0x1 << WCD_USBSS_SWITCH_SETTINGS_ENABLE_DPR_SWITCHES_SHIFT)) +#define DPDM_SW_DISABLE 0x0 + +/* + * wcd_usbss_dpdm_switch_update - configure WCD USBSS DPDM switch position + * + * @enable: value as 0 (to disable) or 1 (to enable) + * + * Returns zero for success, a negative number on error. + */ +int wcd_usbss_dpdm_switch_update(bool enable) +{ + int ret = 0; + + /* check if driver is probed and private context is initialized */ + if (wcd_usbss_ctxt_ == NULL) + return -ENODEV; + + if (!wcd_usbss_ctxt_->regmap) + return -EINVAL; + + ret = regmap_update_bits(wcd_usbss_ctxt_->regmap, WCD_USBSS_SWITCH_SELECT0, + DPDM_SEL_MASK, (enable ? DPDM_SEL_ENABLE : DPDM_SEL_DISABLE)); + + if (ret) + pr_err("%s(): Failed to write dpdm_sel_value ret:%d\n", __func__, ret); + + ret = regmap_update_bits(wcd_usbss_ctxt_->regmap, WCD_USBSS_SWITCH_SETTINGS_ENABLE, + DPDM_SW_EN_MASK, (enable ? DPDM_SW_ENABLE : DPDM_SW_DISABLE)); + if (ret) + pr_err("%s(): Failed to write dpdm_en_value ret:%d\n", __func__, ret); + + return ret; +} +EXPORT_SYMBOL(wcd_usbss_dpdm_switch_update); + +/* + * wcd_usbss_switch_update - configure WCD USBSS switch position based on + * cable type and status + * + * @ctype - cable type + * @connect_status - cable connected/disconnected status + * + * Returns int on whether the switch happened or not. -ENODEV is returned + * in case if the driver is not probed + */ +int wcd_usbss_switch_update(enum wcd_usbss_cable_types ctype, + enum wcd_usbss_cable_status connect_status) +{ + int i = 0; + + /* check if driver is probed and private context is init'ed */ + if (wcd_usbss_ctxt_ == NULL) + return -ENODEV; + + if (!wcd_usbss_ctxt_->regmap) + return -EINVAL; + + if (connect_status == WCD_USBSS_CABLE_DISCONNECT) { + wcd_usbss_switch_update_defaults(wcd_usbss_ctxt_); + } else if (connect_status == WCD_USBSS_CABLE_CONNECT) { + switch (ctype) { + case WCD_USBSS_USB: + break; + case WCD_USBSS_AATC: + /* Disable all switches */ + regmap_update_bits(wcd_usbss_ctxt_->regmap, + WCD_USBSS_SWITCH_SETTINGS_ENABLE, 0x7F, 0x00); + if (audio_fsm_mode == WCD_USBSS_AUDIO_FSM) { + regmap_update_bits_base(wcd_usbss_ctxt_->regmap, + WCD_USBSS_AUDIO_FSM_START, 0x01, 0x01, NULL, false, true); + } + /* Select L, R, GSBU2, MG1 */ + regmap_update_bits(wcd_usbss_ctxt_->regmap, + WCD_USBSS_SWITCH_SELECT0, 0x3F, 0x02); + /* Enable SENSE, MIC switches */ + regmap_update_bits(wcd_usbss_ctxt_->regmap, + WCD_USBSS_SWITCH_SETTINGS_ENABLE, 0x06, 0x06); + /* Select MG2 for AGND_SWITCHES */ + regmap_update_bits(wcd_usbss_ctxt_->regmap, + WCD_USBSS_SWITCH_SELECT1, 0x01, 0x01); + /* Enable AGND switches */ + regmap_update_bits(wcd_usbss_ctxt_->regmap, + WCD_USBSS_SWITCH_SETTINGS_ENABLE, 0x01, 0x01); + /* Enable DPR, DNL */ + regmap_update_bits(wcd_usbss_ctxt_->regmap, + WCD_USBSS_SWITCH_SETTINGS_ENABLE, 0x18, 0x18); + /* Set DELAY_L_SW to CYL_1K */ + regmap_update_bits(wcd_usbss_ctxt_->regmap, + WCD_USBSS_DELAY_L_SW, 0xFF, 0x02); + /* Set DELAY_R_SW to CYL_1K */ + regmap_update_bits(wcd_usbss_ctxt_->regmap, + WCD_USBSS_DELAY_R_SW, 0xFF, 0x02); + /* Set DELAY_MIC_SW to CYL_1K */ + regmap_update_bits(wcd_usbss_ctxt_->regmap, + WCD_USBSS_DELAY_MIC_SW, 0xFF, 0x01); + if (audio_fsm_mode == WCD_USBSS_AUDIO_FSM) { + regmap_update_bits_base(wcd_usbss_ctxt_->regmap, + WCD_USBSS_AUDIO_FSM_START, 0x01, 0x01, NULL, false, true); + } + for (i = 0; i < ARRAY_SIZE(coeff_init); ++i) + regmap_update_bits(wcd_usbss_ctxt_->regmap, coeff_init[i].reg, + coeff_init[i].mask, coeff_init[i].val); + break; + case WCD_USBSS_GND_MIC_SWAP_AATC: + dev_info(wcd_usbss_ctxt_->dev, + "%s: GND MIC Swap register updates..\n", __func__); + /* Disable all switches */ + regmap_update_bits(wcd_usbss_ctxt_->regmap, + WCD_USBSS_SWITCH_SETTINGS_ENABLE, 0x7F, 0x00); + /* Select L, R, GSBU2, MG1 */ + regmap_update_bits(wcd_usbss_ctxt_->regmap, + WCD_USBSS_SWITCH_SELECT0, 0x3F, 0x01); + /* Enable SENSE, MIC switches */ + regmap_update_bits(wcd_usbss_ctxt_->regmap, + WCD_USBSS_SWITCH_SETTINGS_ENABLE, 0x06, 0x06); + /* Select MG1 for AGND_SWITCHES */ + regmap_update_bits(wcd_usbss_ctxt_->regmap, + WCD_USBSS_SWITCH_SELECT1, 0x01, 0x00); + /* Enable AGND switches */ + regmap_update_bits(wcd_usbss_ctxt_->regmap, + WCD_USBSS_SWITCH_SETTINGS_ENABLE, 0x01, 0x01); + /* Enable DPR, DNL */ + regmap_update_bits(wcd_usbss_ctxt_->regmap, + WCD_USBSS_SWITCH_SETTINGS_ENABLE, 0x18, 0x18); + regmap_update_bits_base(wcd_usbss_ctxt_->regmap, + WCD_USBSS_AUDIO_FSM_START, 0x01, 0x01, NULL, false, true); + break; + case WCD_USBSS_DP_AUX_CC1: + fallthrough; + case WCD_USBSS_DP_AUX_CC2: + return wcd_usbss_display_port_switch_update(wcd_usbss_ctxt_, ctype); + } + } + + return 0; +} +EXPORT_SYMBOL(wcd_usbss_switch_update); + +/* + * wcd_usbss_reg_notifier - register notifier block with wcd usbss driver + * + * @nb - notifier block of wcd_usbss + * @node - phandle node to wcd_usbss device + * + * Returns 0 on success, or error code + */ +int wcd_usbss_reg_notifier(struct notifier_block *nb, + struct device_node *node) +{ + int rc = 0; + struct i2c_client *client = of_find_i2c_device_by_node(node); + struct wcd_usbss_ctxt *priv; + + if (!client) + return -EINVAL; + + priv = (struct wcd_usbss_ctxt *)i2c_get_clientdata(client); + if (!priv) + return -EINVAL; + + rc = blocking_notifier_chain_register + (&priv->wcd_usbss_notifier, nb); + + dev_dbg(priv->dev, "%s: registered notifier for %s\n", + __func__, node->name); + if (rc) + return rc; + + /* + * as part of the init sequence check if there is a connected + * USB C analog adapter + */ + if (atomic_read(&(priv->usbc_mode)) == TYPEC_ACCESSORY_AUDIO) { + dev_dbg(priv->dev, "%s: analog adapter already inserted\n", + __func__); + rc = wcd_usbss_usbc_analog_setup_switches(priv); + } + + return rc; +} +EXPORT_SYMBOL(wcd_usbss_reg_notifier); + +/* + * wcd_usbss_unreg_notifier - unregister notifier block with wcd usbss driver + * + * @nb - notifier block of wcd_usbss + * @node - phandle node to wcd_usbss device + * + * Returns 0 on pass, or error code + */ +int wcd_usbss_unreg_notifier(struct notifier_block *nb, + struct device_node *node) +{ + struct i2c_client *client = of_find_i2c_device_by_node(node); + struct wcd_usbss_ctxt *priv; + + if (!client) + return -EINVAL; + + priv = (struct wcd_usbss_ctxt *)i2c_get_clientdata(client); + if (!priv) + return -EINVAL; + + return blocking_notifier_chain_unregister + (&priv->wcd_usbss_notifier, nb); +} +EXPORT_SYMBOL(wcd_usbss_unreg_notifier); + +static void wcd_usbss_usbc_analog_work_fn(struct work_struct *work) +{ + struct wcd_usbss_ctxt *priv = + container_of(work, struct wcd_usbss_ctxt, usbc_analog_work); + + if (!priv) { + pr_err("%s: wcd usbss container invalid\n", __func__); + return; + } + wcd_usbss_usbc_analog_setup_switches(priv); + pm_relax(priv->dev); +} + +static int wcd_usbss_init_optional_reset_pins(struct wcd_usbss_ctxt *priv) +{ + priv->rst_pins = devm_pinctrl_get(priv->dev); + if (IS_ERR_OR_NULL(priv->rst_pins)) { + dev_dbg(priv->dev, "Cannot get wcd usbss reset pinctrl:%ld\n", + PTR_ERR(priv->rst_pins)); + return PTR_ERR(priv->rst_pins); + } + + priv->rst_pins_active = pinctrl_lookup_state( + priv->rst_pins, "active"); + if (IS_ERR_OR_NULL(priv->rst_pins_active)) { + dev_dbg(priv->dev, "Cannot get active pinctrl state:%ld\n", + PTR_ERR(priv->rst_pins_active)); + return PTR_ERR(priv->rst_pins_active); + } + + if (priv->rst_pins_active) + return pinctrl_select_state(priv->rst_pins, + priv->rst_pins_active); + + return 0; +} + +static int wcd_usbss_probe(struct i2c_client *i2c) +{ + struct wcd_usbss_ctxt *priv; + int rc = 0, i; + + priv = devm_kzalloc(&i2c->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = &i2c->dev; + priv->client = i2c; + mutex_init(&priv->io_lock); + i2c_set_clientdata(i2c, priv); + + if (ARRAY_SIZE(supply_names) >= WCD_USBSS_SUPPLY_MAX) { + dev_err(priv->dev, "Unsupported number of supplies: %d\n", + ARRAY_SIZE(supply_names)); + return -EINVAL; + } + for (i = 0; i < ARRAY_SIZE(supply_names); ++i) + priv->supplies[i].supply = supply_names[i]; + + rc = devm_regulator_bulk_get(priv->dev, ARRAY_SIZE(supply_names), + priv->supplies); + if (rc < 0) { + dev_err(priv->dev, "Failed to get supplies: %d\n", rc); + return rc; + } + + rc = regulator_bulk_enable(ARRAY_SIZE(supply_names), priv->supplies); + if (rc) { + dev_err(priv->dev, "Failed to enable supplies: %d\n", rc); + return rc; + } + + rc = wcd_usbss_init_optional_reset_pins(priv); + if (rc) { + dev_dbg(priv->dev, "%s: Optional reset pin reset failed\n", + __func__); + rc = 0; + } + priv->regmap = wcd_usbss_regmap_init(priv->dev, &wcd_usbss_regmap_config); + if (IS_ERR_OR_NULL(priv->regmap)) { + rc = PTR_ERR(priv->regmap); + if (!priv->regmap) + rc = -EINVAL; + + dev_err(priv->dev, "Failed to initialize regmap: %d\n", rc); + goto err_data; + } + + devm_regmap_qti_debugfs_register(priv->dev, priv->regmap); + + priv->ucsi_nb.notifier_call = wcd_usbss_usbc_event_changed; + priv->ucsi_nb.priority = 0; + rc = register_ucsi_glink_notifier(&priv->ucsi_nb); + if (rc) { + dev_err(priv->dev, "%s: ucsi glink notifier registration failed: %d\n", + __func__, rc); + goto err_data; + } + + mutex_init(&priv->notification_lock); + i2c_set_clientdata(i2c, priv); + wcd_usbss_ctxt_ = priv; + + wcd_usbss_update_reg_init(priv->regmap); + INIT_WORK(&priv->usbc_analog_work, + wcd_usbss_usbc_analog_work_fn); + + BLOCKING_INIT_NOTIFIER_HEAD(&priv->wcd_usbss_notifier); + + dev_info(priv->dev, "Probe completed!\n"); + + return 0; + +err_data: + return rc; +} + +static int wcd_usbss_remove(struct i2c_client *i2c) +{ + struct wcd_usbss_ctxt *priv = + (struct wcd_usbss_ctxt *)i2c_get_clientdata(i2c); + + if (!priv) + return -EINVAL; + + unregister_ucsi_glink_notifier(&priv->ucsi_nb); + cancel_work_sync(&priv->usbc_analog_work); + pm_relax(priv->dev); + mutex_destroy(&priv->notification_lock); + mutex_destroy(&priv->io_lock); + dev_set_drvdata(&i2c->dev, NULL); + wcd_usbss_ctxt_ = NULL; + + return 0; +} + +static const struct of_device_id wcd_usbss_i2c_dt_match[] = { + { + .compatible = "qcom,wcd939x-i2c", + }, + {} +}; +MODULE_DEVICE_TABLE(of, wcd_usbss_i2c_dt_match); + +static const struct i2c_device_id wcd_usbss_id_i2c[] = { + { "wcd939x", 0 }, + {} +}; +MODULE_DEVICE_TABLE(i2c, wcd_usbss_id_i2c); + +static struct i2c_driver wcd_usbss_i2c_driver = { + .driver = { + .name = WCD_USBSS_I2C_NAME, + .of_match_table = wcd_usbss_i2c_dt_match, + .probe_type = PROBE_PREFER_ASYNCHRONOUS, + }, + .id_table = wcd_usbss_id_i2c, + .probe_new = wcd_usbss_probe, + .remove = wcd_usbss_remove, +}; +module_i2c_driver(wcd_usbss_i2c_driver); + +MODULE_DESCRIPTION("WCD USBSS I2C driver"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/soc/qcom/wcd939x-i2c.h b/include/linux/soc/qcom/wcd939x-i2c.h new file mode 100644 index 000000000000..7d9fb4edb711 --- /dev/null +++ b/include/linux/soc/qcom/wcd939x-i2c.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ +#ifndef WCD939X_I2C_H +#define WCD939X_I2C_H + +#include +#include +#include + +enum wcd_usbss_cable_types { + WCD_USBSS_USB, + WCD_USBSS_DP_AUX_CC1, + WCD_USBSS_DP_AUX_CC2, + WCD_USBSS_AATC, + WCD_USBSS_GND_MIC_SWAP_AATC, +}; + +enum wcd_usbss_cable_status { + WCD_USBSS_CABLE_CONNECT, + WCD_USBSS_CABLE_DISCONNECT, +}; + +#if IS_ENABLED(CONFIG_QCOM_WCD_USBSS_I2C) +int wcd_usbss_switch_update(enum wcd_usbss_cable_types ctype, + enum wcd_usbss_cable_status status); +int wcd_usbss_reg_notifier(struct notifier_block *nb, + struct device_node *node); +int wcd_usbss_unreg_notifier(struct notifier_block *nb, + struct device_node *node); +int wcd_usbss_dpdm_switch_update(bool enable); +#else +static inline int wcd_usbss_switch_update(enum wcd_usbss_cable_types ctype, + enum wcd_usbss_cable_status status) +{ + return 0; +} + +static inline int wcd_usbss_reg_notifier(struct notifier_block *nb, + struct device_node *node) +{ + return 0; +} + +static inline int wcd_usbss_unreg_notifier(struct notifier_block *nb, + struct device_node *node) +{ + return 0; +} + +static inline int wcd_usbss_dpdm_switch_update(bool enable) +{ + return 0; +} +#endif /* CONFIG_QCOM_WCD_USBSS_I2C */ + +#endif /* WCD939X_I2C_H */ +