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iio: adc: nxp-sar-adc: Fix the delay calculation in nxp_sar_adc_wait_for()
The original code was using ndelay() twice. In one case the delay is calculated as 1/3 of ADC clock and in the other as 80 ADC clocks. But according to the comments in all cases it should be a multiplier of the ADC clock, and not a fraction of it. Inadvertently nxp_sar_adc_wait_for() takes the wrong case and spread it over the code make it wrong in all places. Fix this by modifying a helper to correctly use the multiplier. Fixes:7e5c0f97c6("iio: adc: nxp-sar-adc: Avoid division by zero") Fixes:4434072a89("iio: adc: Add the NXP SAR ADC support for the s32g2/3 platforms") Reported-by: Sashiko <sashiko-bot@kernel.org> Closes: https://sashiko.dev/#/patchset/20260416090122.758990-1-andriy.shevchenko%40linux.intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Stepan Ionichev <sozdayvek@gmail.com> Acked-by: Daniel Lezcano <daniel.lezcano@oss.qualcomm.com> Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
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@ -198,13 +198,13 @@ static void nxp_sar_adc_irq_cfg(struct nxp_sar_adc *info, bool enable)
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writel(0, NXP_SAR_ADC_IMR(info->regs));
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}
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static void nxp_sar_adc_wait_for(struct nxp_sar_adc *info, unsigned int cycles)
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static void nxp_sar_adc_wait_for(struct nxp_sar_adc *info, u64 cycles)
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{
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u64 rate;
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rate = clk_get_rate(info->clk);
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if (rate)
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ndelay(div64_u64(NSEC_PER_SEC, rate * cycles));
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ndelay(div64_u64(NSEC_PER_SEC * cycles, rate));
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}
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static bool nxp_sar_adc_set_enabled(struct nxp_sar_adc *info, bool enable)
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