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net: stmmac: rk: replace empty set_to_rmii() with supports_rmii
Rather than providing a now-empty set_to_rmii() method to indicate that RMII is supported, switch to setting ops->supports_rmii instead. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Heiko Stuebner <heiko@sntech.de> #px30,rk3328,rk3568,rk3588 Link: https://patch.msgid.link/E1vnYxq-00000007hor-3yXt@rmk-PC.armlinux.org.uk Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Russell King (Oracle)
Jakub Kicinski
parent
d323769d64
commit
a9d4aff670
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@ -268,12 +268,7 @@ static void rk_gmac_integrated_fephy_powerdown(struct rk_priv_data *priv,
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#define PX30_GRF_GMAC_CON1 0x0904
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static void px30_set_to_rmii(struct rk_priv_data *bsp_priv)
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{
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}
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static const struct rk_gmac_ops px30_ops = {
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.set_to_rmii = px30_set_to_rmii,
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.set_speed = rk_set_clk_mac_speed,
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.gmac_grf_reg = PX30_GRF_GMAC_CON1,
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@ -281,6 +276,8 @@ static const struct rk_gmac_ops px30_ops = {
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.clock_grf_reg = PX30_GRF_GMAC_CON1,
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.clock.mac_speed_mask = BIT_U16(2),
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.supports_rmii = true,
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};
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#define RK3128_GRF_MAC_CON0 0x0168
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@ -307,13 +304,8 @@ static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv,
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RK3128_GMAC_CLK_TX_DL_CFG(tx_delay));
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}
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static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)
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{
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}
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static const struct rk_gmac_ops rk3128_ops = {
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.set_to_rgmii = rk3128_set_to_rgmii,
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.set_to_rmii = rk3128_set_to_rmii,
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.gmac_grf_reg = RK3128_GRF_MAC_CON1,
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.gmac_phy_intf_sel_mask = GENMASK_U16(8, 6),
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@ -323,6 +315,8 @@ static const struct rk_gmac_ops rk3128_ops = {
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.clock.gmii_clk_sel_mask = GENMASK_U16(13, 12),
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.clock.rmii_clk_sel_mask = BIT_U16(11),
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.clock.mac_speed_mask = BIT_U16(10),
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.supports_rmii = true,
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};
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#define RK3228_GRF_MAC_CON0 0x0900
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@ -410,13 +404,8 @@ static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv,
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RK3288_GMAC_CLK_TX_DL_CFG(tx_delay));
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}
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static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
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{
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}
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static const struct rk_gmac_ops rk3288_ops = {
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.set_to_rgmii = rk3288_set_to_rgmii,
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.set_to_rmii = rk3288_set_to_rmii,
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.gmac_grf_reg = RK3288_GRF_SOC_CON1,
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.gmac_phy_intf_sel_mask = GENMASK_U16(8, 6),
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@ -426,6 +415,8 @@ static const struct rk_gmac_ops rk3288_ops = {
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.clock.gmii_clk_sel_mask = GENMASK_U16(13, 12),
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.clock.rmii_clk_sel_mask = BIT_U16(11),
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.clock.mac_speed_mask = BIT_U16(10),
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.supports_rmii = true,
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};
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#define RK3308_GRF_MAC_CON0 0x04a0
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@ -434,18 +425,14 @@ static const struct rk_gmac_ops rk3288_ops = {
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#define RK3308_GMAC_FLOW_CTRL GRF_BIT(3)
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#define RK3308_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
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static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv)
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{
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}
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static const struct rk_gmac_ops rk3308_ops = {
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.set_to_rmii = rk3308_set_to_rmii,
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.gmac_grf_reg = RK3308_GRF_MAC_CON0,
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.gmac_phy_intf_sel_mask = GENMASK_U16(4, 2),
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.clock_grf_reg = RK3308_GRF_MAC_CON0,
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.clock.mac_speed_mask = BIT_U16(0),
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.supports_rmii = true,
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};
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#define RK3328_GRF_MAC_CON0 0x0900
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@ -497,10 +484,6 @@ static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv,
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RK3328_GMAC_CLK_TX_DL_CFG(tx_delay));
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}
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static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
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{
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}
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static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv)
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{
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regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
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@ -512,7 +495,6 @@ static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv)
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static const struct rk_gmac_ops rk3328_ops = {
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.init = rk3328_init,
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.set_to_rgmii = rk3328_set_to_rgmii,
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.set_to_rmii = rk3328_set_to_rmii,
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.integrated_phy_powerup = rk3328_integrated_phy_powerup,
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.integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown,
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@ -522,6 +504,8 @@ static const struct rk_gmac_ops rk3328_ops = {
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.clock.rmii_clk_sel_mask = BIT_U16(7),
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.clock.mac_speed_mask = BIT_U16(2),
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.supports_rmii = true,
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.regs_valid = true,
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.regs = {
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0xff540000, /* gmac2io */
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@ -554,13 +538,8 @@ static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv,
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RK3366_GMAC_CLK_TX_DL_CFG(tx_delay));
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}
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static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
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{
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}
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static const struct rk_gmac_ops rk3366_ops = {
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.set_to_rgmii = rk3366_set_to_rgmii,
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.set_to_rmii = rk3366_set_to_rmii,
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.gmac_grf_reg = RK3366_GRF_SOC_CON6,
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.gmac_phy_intf_sel_mask = GENMASK_U16(11, 9),
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@ -570,6 +549,8 @@ static const struct rk_gmac_ops rk3366_ops = {
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.clock.gmii_clk_sel_mask = GENMASK_U16(5, 4),
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.clock.rmii_clk_sel_mask = BIT_U16(3),
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.clock.mac_speed_mask = BIT_U16(7),
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.supports_rmii = true,
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};
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#define RK3368_GRF_SOC_CON15 0x043c
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@ -596,13 +577,8 @@ static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv,
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RK3368_GMAC_CLK_TX_DL_CFG(tx_delay));
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}
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static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
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{
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}
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static const struct rk_gmac_ops rk3368_ops = {
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.set_to_rgmii = rk3368_set_to_rgmii,
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.set_to_rmii = rk3368_set_to_rmii,
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.gmac_grf_reg = RK3368_GRF_SOC_CON15,
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.gmac_phy_intf_sel_mask = GENMASK_U16(11, 9),
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@ -612,6 +588,8 @@ static const struct rk_gmac_ops rk3368_ops = {
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.clock.gmii_clk_sel_mask = GENMASK_U16(5, 4),
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.clock.rmii_clk_sel_mask = BIT_U16(3),
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.clock.mac_speed_mask = BIT_U16(7),
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.supports_rmii = true,
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};
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#define RK3399_GRF_SOC_CON5 0xc214
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@ -638,13 +616,8 @@ static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv,
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RK3399_GMAC_CLK_TX_DL_CFG(tx_delay));
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}
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static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
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{
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}
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static const struct rk_gmac_ops rk3399_ops = {
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.set_to_rgmii = rk3399_set_to_rgmii,
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.set_to_rmii = rk3399_set_to_rmii,
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.gmac_grf_reg = RK3399_GRF_SOC_CON5,
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.gmac_phy_intf_sel_mask = GENMASK_U16(11, 9),
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@ -654,6 +627,8 @@ static const struct rk_gmac_ops rk3399_ops = {
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.clock.gmii_clk_sel_mask = GENMASK_U16(5, 4),
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.clock.rmii_clk_sel_mask = BIT_U16(3),
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.clock.mac_speed_mask = BIT_U16(7),
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.supports_rmii = true,
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};
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#define RK3506_GRF_SOC_CON8 0x0020
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@ -884,18 +859,15 @@ static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv,
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RK3568_GMAC_TXCLK_DLY_ENABLE);
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}
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static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv)
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{
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}
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static const struct rk_gmac_ops rk3568_ops = {
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.init = rk3568_init,
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.set_to_rgmii = rk3568_set_to_rgmii,
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.set_to_rmii = rk3568_set_to_rmii,
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.set_speed = rk_set_clk_mac_speed,
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.gmac_phy_intf_sel_mask = GENMASK_U16(6, 4),
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.supports_rmii = true,
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.regs_valid = true,
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.regs = {
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0xfe2a0000, /* gmac0 */
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@ -969,10 +941,6 @@ static void rk3576_set_to_rgmii(struct rk_priv_data *bsp_priv,
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RK3576_GMAC_CLK_RX_DL_CFG(rx_delay));
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}
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static void rk3576_set_to_rmii(struct rk_priv_data *bsp_priv)
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{
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}
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static void rk3576_set_clock_selection(struct rk_priv_data *bsp_priv, bool input,
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bool enable)
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{
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@ -992,7 +960,6 @@ static void rk3576_set_clock_selection(struct rk_priv_data *bsp_priv, bool input
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static const struct rk_gmac_ops rk3576_ops = {
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.init = rk3576_init,
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.set_to_rgmii = rk3576_set_to_rgmii,
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.set_to_rmii = rk3576_set_to_rmii,
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.set_clock_selection = rk3576_set_clock_selection,
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.gmac_rmii_mode_mask = BIT_U16(3),
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@ -1000,6 +967,8 @@ static const struct rk_gmac_ops rk3576_ops = {
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.clock.gmii_clk_sel_mask = GENMASK_U16(6, 5),
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.clock.rmii_clk_sel_mask = BIT_U16(5),
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.supports_rmii = true,
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.php_grf_required = true,
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.regs_valid = true,
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.regs = {
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@ -1120,19 +1089,15 @@ static const struct rk_gmac_ops rk3588_ops = {
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#define RV1108_GMAC_FLOW_CTRL GRF_BIT(3)
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#define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
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static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv)
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{
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}
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static const struct rk_gmac_ops rv1108_ops = {
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.set_to_rmii = rv1108_set_to_rmii,
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.gmac_grf_reg = RV1108_GRF_GMAC_CON0,
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.gmac_phy_intf_sel_mask = GENMASK_U16(6, 4),
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.clock_grf_reg = RV1108_GRF_GMAC_CON0,
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.clock.rmii_clk_sel_mask = BIT_U16(7),
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.clock.mac_speed_mask = BIT_U16(2),
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.supports_rmii = true,
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};
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#define RV1126_GRF_GMAC_CON0 0X0070
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@ -1176,17 +1141,14 @@ static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv,
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RV1126_GMAC_M1_CLK_TX_DL_CFG(tx_delay));
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}
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static void rv1126_set_to_rmii(struct rk_priv_data *bsp_priv)
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{
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}
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static const struct rk_gmac_ops rv1126_ops = {
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.set_to_rgmii = rv1126_set_to_rgmii,
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.set_to_rmii = rv1126_set_to_rmii,
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.set_speed = rk_set_clk_mac_speed,
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.gmac_grf_reg = RV1126_GRF_GMAC_CON0,
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.gmac_phy_intf_sel_mask = GENMASK_U16(6, 4),
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.supports_rmii = true,
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};
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static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat)
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