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drm/i915: pass dev_priv explicitly to DSPSIZE

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Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DSPSIZE register macro.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/d24ee614cac29ccc3917f9cba1ce03ce54fb7d8b.1716469091.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Jani Nikula 2024-05-23 15:59:35 +03:00
parent 3ebfafa75c
commit a99b1e7f63
3 changed files with 5 additions and 5 deletions
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2
drivers/gpu/drm/i915/display/i9xx_plane.c
View File

@ -439,7 +439,7 @@ static void i9xx_plane_update_noarm(struct intel_plane *plane,
*/
intel_de_write_fw(dev_priv, DSPPOS(dev_priv, i9xx_plane),
DISP_POS_Y(crtc_y) | DISP_POS_X(crtc_x));
intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),
intel_de_write_fw(dev_priv, DSPSIZE(dev_priv, i9xx_plane),
DISP_HEIGHT(crtc_h - 1) | DISP_WIDTH(crtc_w - 1));
}
}

2
drivers/gpu/drm/i915/display/i9xx_plane_regs.h
View File

@ -60,7 +60,7 @@
#define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x))
#define _DSPASIZE 0x70190 /* pre-g4x */
#define DSPSIZE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE)
#define DSPSIZE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE)
#define DISP_HEIGHT_MASK REG_GENMASK(31, 16)
#define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h))
#define DISP_WIDTH_MASK REG_GENMASK(15, 0)

6
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
View File

@ -169,7 +169,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(DSPADDR(dev_priv, PIPE_A));
MMIO_D(DSPSTRIDE(dev_priv, PIPE_A));
MMIO_D(DSPPOS(dev_priv, PIPE_A));
MMIO_D(DSPSIZE(PIPE_A));
MMIO_D(DSPSIZE(dev_priv, PIPE_A));
MMIO_D(DSPSURF(PIPE_A));
MMIO_D(DSPOFFSET(PIPE_A));
MMIO_D(DSPSURFLIVE(PIPE_A));
@ -178,7 +178,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(DSPADDR(dev_priv, PIPE_B));
MMIO_D(DSPSTRIDE(dev_priv, PIPE_B));
MMIO_D(DSPPOS(dev_priv, PIPE_B));
MMIO_D(DSPSIZE(PIPE_B));
MMIO_D(DSPSIZE(dev_priv, PIPE_B));
MMIO_D(DSPSURF(PIPE_B));
MMIO_D(DSPOFFSET(PIPE_B));
MMIO_D(DSPSURFLIVE(PIPE_B));
@ -187,7 +187,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(DSPADDR(dev_priv, PIPE_C));
MMIO_D(DSPSTRIDE(dev_priv, PIPE_C));
MMIO_D(DSPPOS(dev_priv, PIPE_C));
MMIO_D(DSPSIZE(PIPE_C));
MMIO_D(DSPSIZE(dev_priv, PIPE_C));
MMIO_D(DSPSURF(PIPE_C));
MMIO_D(DSPOFFSET(PIPE_C));
MMIO_D(DSPSURFLIVE(PIPE_C));