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drm/amd/display: add DalForceMaxDisplayClock debug option to DML2

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[Why & How]
need to apply the debug option check for max displayclk.

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Justin Chen <Justin.Chen5@amd.com>
Signed-off-by: Matthew Stewart <matthew.stewart2@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Justin Chen 2026-05-12 17:05:06 -04:00 committed by Alex Deucher
parent 137b565595
commit a985e937c2
1 changed files with 5 additions and 0 deletions
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5
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c
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@ -155,6 +155,11 @@ static void dml21_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_sta
context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[0];
}
if (dc->config.forced_clocks || dc->debug.max_disp_clk) {
context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz;
context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
}
/* get global mall allocation */
if (dc->res_pool->funcs->calculate_mall_ways_from_bytes) {
context->bw_ctx.bw.dcn.clk.num_ways = dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, context->bw_ctx.bw.dcn.mall_subvp_size_bytes);