From 30e7573babdcd46542364a2505d34112e62d5a22 Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Mon, 3 Mar 2025 16:25:10 +0100 Subject: [PATCH 1/7] dt-bindings: reset: Add T-HEAD TH1520 SoC Reset Controller Add a YAML schema for the T-HEAD TH1520 SoC reset controller. This controller manages resets for subsystems such as the GPU within the TH1520 SoC. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Michal Wilczynski Link: https://lore.kernel.org/r/20250303152511.494405-2-m.wilczynski@samsung.com Signed-off-by: Philipp Zabel --- .../bindings/reset/thead,th1520-reset.yaml | 44 +++++++++++++++++++ MAINTAINERS | 2 + .../dt-bindings/reset/thead,th1520-reset.h | 16 +++++++ 3 files changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml create mode 100644 include/dt-bindings/reset/thead,th1520-reset.h diff --git a/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml b/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml new file mode 100644 index 000000000000..f2e91d0add7a --- /dev/null +++ b/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/thead,th1520-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-HEAD TH1520 SoC Reset Controller + +description: + The T-HEAD TH1520 reset controller is a hardware block that asserts/deasserts + resets for SoC subsystems. + +maintainers: + - Michal Wilczynski + +properties: + compatible: + enum: + - thead,th1520-reset + + reg: + maxItems: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - "#reset-cells" + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + rst: reset-controller@ffef528000 { + compatible = "thead,th1520-reset"; + reg = <0xff 0xef528000 0x0 0x1000>; + #reset-cells = <1>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 96b827049501..88f9e8b7fa74 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20825,6 +20825,7 @@ F: Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml F: Documentation/devicetree/bindings/mailbox/thead,th1520-mbox.yaml F: Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml F: Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml +F: Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml F: arch/riscv/boot/dts/thead/ F: drivers/clk/thead/clk-th1520-ap.c F: drivers/firmware/thead,th1520-aon.c @@ -20834,6 +20835,7 @@ F: drivers/pinctrl/pinctrl-th1520.c F: drivers/pmdomain/thead/ F: include/dt-bindings/clock/thead,th1520-clk-ap.h F: include/dt-bindings/power/thead,th1520-power.h +F: include/dt-bindings/reset/thead,th1520-reset.h F: include/linux/firmware/thead/thead,th1520-aon.h RNBD BLOCK DRIVERS diff --git a/include/dt-bindings/reset/thead,th1520-reset.h b/include/dt-bindings/reset/thead,th1520-reset.h new file mode 100644 index 000000000000..00459f160489 --- /dev/null +++ b/include/dt-bindings/reset/thead,th1520-reset.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024 Samsung Electronics Co., Ltd. + * Author: Michal Wilczynski + */ + +#ifndef _DT_BINDINGS_TH1520_RESET_H +#define _DT_BINDINGS_TH1520_RESET_H + +#define TH1520_RESET_ID_GPU 0 +#define TH1520_RESET_ID_GPU_CLKGEN 1 +#define TH1520_RESET_ID_NPU 2 +#define TH1520_RESET_ID_WDT0 3 +#define TH1520_RESET_ID_WDT1 4 + +#endif /* _DT_BINDINGS_TH1520_RESET_H */ From 4a65326311aba694faafcef9e3c0ef7ae1b722e6 Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Mon, 3 Mar 2025 16:25:11 +0100 Subject: [PATCH 2/7] reset: thead: Add TH1520 reset controller driver Add reset controller driver for the T-HEAD TH1520 SoC that manages hardware reset lines for various subsystems. The driver currently implements support for GPU reset control, with infrastructure in place to extend support for NPU and Watchdog Timer resets in future updates. Reviewed-by: Philipp Zabel Signed-off-by: Michal Wilczynski Link: https://lore.kernel.org/r/20250303152511.494405-3-m.wilczynski@samsung.com Signed-off-by: Philipp Zabel --- MAINTAINERS | 1 + drivers/reset/Kconfig | 10 +++ drivers/reset/Makefile | 1 + drivers/reset/reset-th1520.c | 135 +++++++++++++++++++++++++++++++++++ 4 files changed, 147 insertions(+) create mode 100644 drivers/reset/reset-th1520.c diff --git a/MAINTAINERS b/MAINTAINERS index 88f9e8b7fa74..10ec129c066d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20833,6 +20833,7 @@ F: drivers/mailbox/mailbox-th1520.c F: drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c F: drivers/pinctrl/pinctrl-th1520.c F: drivers/pmdomain/thead/ +F: drivers/reset/reset-th1520.c F: include/dt-bindings/clock/thead,th1520-clk-ap.h F: include/dt-bindings/power/thead,th1520-power.h F: include/dt-bindings/reset/thead,th1520-reset.h diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 99f6f9784e68..11ce86c8156b 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -279,6 +279,16 @@ config RESET_SUNXI help This enables the reset driver for Allwinner SoCs. +config RESET_TH1520 + tristate "T-HEAD 1520 reset controller" + depends on ARCH_THEAD || COMPILE_TEST + select REGMAP_MMIO + help + This driver provides support for the T-HEAD TH1520 SoC reset controller, + which manages hardware reset lines for SoC components such as the GPU. + Enable this option if you need to control hardware resets on TH1520-based + systems. + config RESET_TI_SCI tristate "TI System Control Interface (TI-SCI) reset driver" depends on TI_SCI_PROTOCOL || (COMPILE_TEST && TI_SCI_PROTOCOL=n) diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 31f9904d13f9..6322a191e2a8 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o +obj-$(CONFIG_RESET_TH1520) += reset-th1520.o obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o obj-$(CONFIG_RESET_TI_TPS380X) += reset-tps380x.o diff --git a/drivers/reset/reset-th1520.c b/drivers/reset/reset-th1520.c new file mode 100644 index 000000000000..7874f0693e1b --- /dev/null +++ b/drivers/reset/reset-th1520.c @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024 Samsung Electronics Co., Ltd. + * Author: Michal Wilczynski + */ + +#include +#include +#include +#include + +#include + + /* register offset in VOSYS_REGMAP */ +#define TH1520_GPU_RST_CFG 0x0 +#define TH1520_GPU_RST_CFG_MASK GENMASK(1, 0) + +/* register values */ +#define TH1520_GPU_SW_GPU_RST BIT(0) +#define TH1520_GPU_SW_CLKGEN_RST BIT(1) + +struct th1520_reset_priv { + struct reset_controller_dev rcdev; + struct regmap *map; +}; + +struct th1520_reset_map { + u32 bit; + u32 reg; +}; + +static const struct th1520_reset_map th1520_resets[] = { + [TH1520_RESET_ID_GPU] = { + .bit = TH1520_GPU_SW_GPU_RST, + .reg = TH1520_GPU_RST_CFG, + }, + [TH1520_RESET_ID_GPU_CLKGEN] = { + .bit = TH1520_GPU_SW_CLKGEN_RST, + .reg = TH1520_GPU_RST_CFG, + } +}; + +static inline struct th1520_reset_priv * +to_th1520_reset(struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct th1520_reset_priv, rcdev); +} + +static int th1520_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct th1520_reset_priv *priv = to_th1520_reset(rcdev); + const struct th1520_reset_map *reset; + + reset = &th1520_resets[id]; + + return regmap_update_bits(priv->map, reset->reg, reset->bit, 0); +} + +static int th1520_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct th1520_reset_priv *priv = to_th1520_reset(rcdev); + const struct th1520_reset_map *reset; + + reset = &th1520_resets[id]; + + return regmap_update_bits(priv->map, reset->reg, reset->bit, + reset->bit); +} + +static const struct reset_control_ops th1520_reset_ops = { + .assert = th1520_reset_assert, + .deassert = th1520_reset_deassert, +}; + +static const struct regmap_config th1520_reset_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .fast_io = true, +}; + +static int th1520_reset_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct th1520_reset_priv *priv; + void __iomem *base; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + priv->map = devm_regmap_init_mmio(dev, base, + &th1520_reset_regmap_config); + if (IS_ERR(priv->map)) + return PTR_ERR(priv->map); + + /* Initialize GPU resets to asserted state */ + ret = regmap_update_bits(priv->map, TH1520_GPU_RST_CFG, + TH1520_GPU_RST_CFG_MASK, 0); + if (ret) + return ret; + + priv->rcdev.owner = THIS_MODULE; + priv->rcdev.nr_resets = ARRAY_SIZE(th1520_resets); + priv->rcdev.ops = &th1520_reset_ops; + priv->rcdev.of_node = dev->of_node; + + return devm_reset_controller_register(dev, &priv->rcdev); +} + +static const struct of_device_id th1520_reset_match[] = { + { .compatible = "thead,th1520-reset" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, th1520_reset_match); + +static struct platform_driver th1520_reset_driver = { + .driver = { + .name = "th1520-reset", + .of_match_table = th1520_reset_match, + }, + .probe = th1520_reset_probe, +}; +module_platform_driver(th1520_reset_driver); + +MODULE_AUTHOR("Michal Wilczynski "); +MODULE_DESCRIPTION("T-HEAD TH1520 SoC reset controller"); +MODULE_LICENSE("GPL"); From 6b3754009f871083b114daacbad5b87a494da4b8 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Fri, 11 Apr 2025 14:41:10 +0200 Subject: [PATCH 3/7] reset: Add devm_reset_control_array_get_exclusive_released() Add the released variant of devm_reset_control_array_get_exclusive(). Needed by spi-smt32-ospi driver as same reset line is ulso used by stm32-omm driver. Signed-off-by: Patrice Chotard Reviewed-by: Philipp Zabel Link: https://lore.kernel.org/r/20250411-b4-upstream_ospi_reset_update-v2-1-4de7f5dd2a91@foss.st.com Signed-off-by: Philipp Zabel --- include/linux/reset.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/linux/reset.h b/include/linux/reset.h index 2986ced69a02..840d75d172f6 100644 --- a/include/linux/reset.h +++ b/include/linux/reset.h @@ -1004,6 +1004,12 @@ devm_reset_control_array_get_exclusive(struct device *dev) return devm_reset_control_array_get(dev, RESET_CONTROL_EXCLUSIVE); } +static inline struct reset_control * +devm_reset_control_array_get_exclusive_released(struct device *dev) +{ + return devm_reset_control_array_get(dev, RESET_CONTROL_EXCLUSIVE_RELEASED); +} + static inline struct reset_control * devm_reset_control_array_get_shared(struct device *dev) { From 261f3ff29a2b15ad70bf2530550421ad9a9a5966 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 15 Apr 2025 20:51:29 +0100 Subject: [PATCH 4/7] dt-bindings: reset: Document RZ/V2H(P) USB2PHY reset Add a device tree binding document for the Renesas RZ/V2H(P) USB2PHY reset controller. This block manages the reset and power-down of the USB 2.0 PHY, which is used in both host and function modes. Signed-off-by: Lad Prabhakar Reviewed-by: Krzysztof Kozlowski Reviewed-by: Fabrizio Castro Link: https://lore.kernel.org/r/20250415195131.281060-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Philipp Zabel --- .../reset/renesas,rzv2h-usb2phy-reset.yaml | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/renesas,rzv2h-usb2phy-reset.yaml diff --git a/Documentation/devicetree/bindings/reset/renesas,rzv2h-usb2phy-reset.yaml b/Documentation/devicetree/bindings/reset/renesas,rzv2h-usb2phy-reset.yaml new file mode 100644 index 000000000000..c79f61c2373b --- /dev/null +++ b/Documentation/devicetree/bindings/reset/renesas,rzv2h-usb2phy-reset.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/renesas,rzv2h-usb2phy-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/V2H(P) USB2PHY Port reset Control + +maintainers: + - Lad Prabhakar + +description: + The RZ/V2H(P) USB2PHY Control mainly controls Port reset and power down of the + USB2.0 PHY. + +properties: + compatible: + const: renesas,r9a09g057-usb2phy-reset # RZ/V2H(P) + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + power-domains: + maxItems: 1 + + '#reset-cells': + const: 0 + +required: + - compatible + - reg + - clocks + - resets + - power-domains + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + + reset-controller@15830000 { + compatible = "renesas,r9a09g057-usb2phy-reset"; + reg = <0x15830000 0x10000>; + clocks = <&cpg CPG_MOD 0xb6>; + resets = <&cpg 0xaf>; + power-domains = <&cpg>; + #reset-cells = <0>; + }; From e3911d7f865bbc704205f45333e491e4034942c7 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 15 Apr 2025 20:51:30 +0100 Subject: [PATCH 5/7] reset: Add USB2PHY port reset driver for Renesas RZ/V2H(P) Implement a USB2PHY port reset driver for the Renesas RZ/V2H(P) SoC. Enable control of USB2.0 PHY reset and power-down operations, including assert and deassert functionalities for the PHY. Leverage device tree (OF) data to support future SoCs with similar USB2PHY hardware but varying register configurations. Define initialization values and control register settings to ensure flexibility for upcoming platforms. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Reviewed-by: Fabrizio Castro Link: https://lore.kernel.org/r/20250415195131.281060-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Philipp Zabel --- drivers/reset/Kconfig | 7 + drivers/reset/Makefile | 1 + drivers/reset/reset-rzv2h-usb2phy.c | 236 ++++++++++++++++++++++++++++ 3 files changed, 244 insertions(+) create mode 100644 drivers/reset/reset-rzv2h-usb2phy.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 11ce86c8156b..d85be5899da6 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -225,6 +225,13 @@ config RESET_RZG2L_USBPHY_CTRL Support for USBPHY Control found on RZ/G2L family. It mainly controls reset and power down of the USB/PHY. +config RESET_RZV2H_USB2PHY + tristate "Renesas RZ/V2H(P) (and similar SoCs) USB2PHY Reset driver" + depends on ARCH_RENESAS || COMPILE_TEST + help + Support for USB2PHY Port reset Control found on the RZ/V2H(P) SoC + (and similar SoCs). + config RESET_SCMI tristate "Reset driver controlled via ARM SCMI interface" depends on ARM_SCMI_PROTOCOL || COMPILE_TEST diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 6322a191e2a8..91e6348e3351 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o +obj-$(CONFIG_RESET_RZV2H_USB2PHY) += reset-rzv2h-usb2phy.o obj-$(CONFIG_RESET_SCMI) += reset-scmi.o obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o diff --git a/drivers/reset/reset-rzv2h-usb2phy.c b/drivers/reset/reset-rzv2h-usb2phy.c new file mode 100644 index 000000000000..ae643575b067 --- /dev/null +++ b/drivers/reset/reset-rzv2h-usb2phy.c @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas RZ/V2H(P) USB2PHY Port reset control driver + * + * Copyright (C) 2025 Renesas Electronics Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct rzv2h_usb2phy_regval { + u16 reg; + u16 val; +}; + +struct rzv2h_usb2phy_reset_of_data { + const struct rzv2h_usb2phy_regval *init_vals; + unsigned int init_val_count; + + u16 reset_reg; + u16 reset_assert_val; + u16 reset_deassert_val; + u16 reset_status_bits; + u16 reset_release_val; + + u16 reset2_reg; + u16 reset2_acquire_val; + u16 reset2_release_val; +}; + +struct rzv2h_usb2phy_reset_priv { + const struct rzv2h_usb2phy_reset_of_data *data; + void __iomem *base; + struct device *dev; + struct reset_controller_dev rcdev; + spinlock_t lock; /* protects register accesses */ +}; + +static inline struct rzv2h_usb2phy_reset_priv +*rzv2h_usbphy_rcdev_to_priv(struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct rzv2h_usb2phy_reset_priv, rcdev); +} + +/* This function must be called only after pm_runtime_resume_and_get() has been called */ +static void rzv2h_usbphy_assert_helper(struct rzv2h_usb2phy_reset_priv *priv) +{ + const struct rzv2h_usb2phy_reset_of_data *data = priv->data; + + scoped_guard(spinlock, &priv->lock) { + writel(data->reset2_acquire_val, priv->base + data->reset2_reg); + writel(data->reset_assert_val, priv->base + data->reset_reg); + } + + usleep_range(11, 20); +} + +static int rzv2h_usbphy_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct rzv2h_usb2phy_reset_priv *priv = rzv2h_usbphy_rcdev_to_priv(rcdev); + struct device *dev = priv->dev; + int ret; + + ret = pm_runtime_resume_and_get(dev); + if (ret) { + dev_err(dev, "pm_runtime_resume_and_get failed\n"); + return ret; + } + + rzv2h_usbphy_assert_helper(priv); + + pm_runtime_put(dev); + + return 0; +} + +static int rzv2h_usbphy_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct rzv2h_usb2phy_reset_priv *priv = rzv2h_usbphy_rcdev_to_priv(rcdev); + const struct rzv2h_usb2phy_reset_of_data *data = priv->data; + struct device *dev = priv->dev; + int ret; + + ret = pm_runtime_resume_and_get(dev); + if (ret) { + dev_err(dev, "pm_runtime_resume_and_get failed\n"); + return ret; + } + + scoped_guard(spinlock, &priv->lock) { + writel(data->reset_deassert_val, priv->base + data->reset_reg); + writel(data->reset2_release_val, priv->base + data->reset2_reg); + writel(data->reset_release_val, priv->base + data->reset_reg); + } + + pm_runtime_put(dev); + + return 0; +} + +static int rzv2h_usbphy_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct rzv2h_usb2phy_reset_priv *priv = rzv2h_usbphy_rcdev_to_priv(rcdev); + struct device *dev = priv->dev; + int ret; + u32 reg; + + ret = pm_runtime_resume_and_get(dev); + if (ret) { + dev_err(dev, "pm_runtime_resume_and_get failed\n"); + return ret; + } + + reg = readl(priv->base + priv->data->reset_reg); + + pm_runtime_put(dev); + + return (reg & priv->data->reset_status_bits) == priv->data->reset_status_bits; +} + +static const struct reset_control_ops rzv2h_usbphy_reset_ops = { + .assert = rzv2h_usbphy_reset_assert, + .deassert = rzv2h_usbphy_reset_deassert, + .status = rzv2h_usbphy_reset_status, +}; + +static int rzv2h_usb2phy_reset_of_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + /* No special handling needed, we have only one reset line per device */ + return 0; +} + +static int rzv2h_usb2phy_reset_probe(struct platform_device *pdev) +{ + const struct rzv2h_usb2phy_reset_of_data *data; + struct rzv2h_usb2phy_reset_priv *priv; + struct device *dev = &pdev->dev; + struct reset_control *rstc; + int error; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + data = of_device_get_match_data(dev); + priv->data = data; + priv->dev = dev; + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + rstc = devm_reset_control_get_shared_deasserted(dev, NULL); + if (IS_ERR(rstc)) + return dev_err_probe(dev, PTR_ERR(rstc), + "failed to get deasserted reset\n"); + + spin_lock_init(&priv->lock); + + error = devm_pm_runtime_enable(dev); + if (error) + return dev_err_probe(dev, error, "Failed to enable pm_runtime\n"); + + error = pm_runtime_resume_and_get(dev); + if (error) + return dev_err_probe(dev, error, "pm_runtime_resume_and_get failed\n"); + + for (unsigned int i = 0; i < data->init_val_count; i++) + writel(data->init_vals[i].val, priv->base + data->init_vals[i].reg); + + /* keep usb2phy in asserted state */ + rzv2h_usbphy_assert_helper(priv); + + pm_runtime_put(dev); + + priv->rcdev.ops = &rzv2h_usbphy_reset_ops; + priv->rcdev.of_reset_n_cells = 0; + priv->rcdev.nr_resets = 1; + priv->rcdev.of_xlate = rzv2h_usb2phy_reset_of_xlate; + priv->rcdev.of_node = dev->of_node; + priv->rcdev.dev = dev; + + return devm_reset_controller_register(dev, &priv->rcdev); +} + +/* + * initialization values required to prepare the PHY to receive + * assert and deassert requests. + */ +static const struct rzv2h_usb2phy_regval rzv2h_init_vals[] = { + { .reg = 0xc10, .val = 0x67c }, + { .reg = 0xc14, .val = 0x1f }, + { .reg = 0x600, .val = 0x909 }, +}; + +static const struct rzv2h_usb2phy_reset_of_data rzv2h_reset_of_data = { + .init_vals = rzv2h_init_vals, + .init_val_count = ARRAY_SIZE(rzv2h_init_vals), + .reset_reg = 0, + .reset_assert_val = 0x206, + .reset_status_bits = BIT(2), + .reset_deassert_val = 0x200, + .reset_release_val = 0x0, + .reset2_reg = 0xb04, + .reset2_acquire_val = 0x303, + .reset2_release_val = 0x3, +}; + +static const struct of_device_id rzv2h_usb2phy_reset_of_match[] = { + { .compatible = "renesas,r9a09g057-usb2phy-reset", .data = &rzv2h_reset_of_data }, + { /* Sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rzv2h_usb2phy_reset_of_match); + +static struct platform_driver rzv2h_usb2phy_reset_driver = { + .driver = { + .name = "rzv2h_usb2phy_reset", + .of_match_table = rzv2h_usb2phy_reset_of_match, + }, + .probe = rzv2h_usb2phy_reset_probe, +}; +module_platform_driver(rzv2h_usb2phy_reset_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Lad Prabhakar "); +MODULE_DESCRIPTION("Renesas RZ/V2H(P) USB2PHY Control"); From 57dfdfbe1a03408a0351afab83bd0f3e4741f727 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 15 Apr 2025 20:51:31 +0100 Subject: [PATCH 6/7] MAINTAINERS: Add entry for Renesas RZ/V2H(P) USB2PHY Port Reset driver Add a new MAINTAINERS entry for the Renesas RZ/V2H(P) USB2PHY Port Reset driver. Signed-off-by: Lad Prabhakar Acked-by: Fabrizio Castro Link: https://lore.kernel.org/r/20250415195131.281060-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Philipp Zabel --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 10ec129c066d..28dbd9dc8673 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20613,6 +20613,14 @@ S: Maintained F: Documentation/devicetree/bindings/usb/renesas,rzn1-usbf.yaml F: drivers/usb/gadget/udc/renesas_usbf.c +RENESAS RZ/V2H(P) USB2PHY PORT RESET DRIVER +M: Fabrizio Castro +M: Lad Prabhakar +L: linux-renesas-soc@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/reset/renesas,rzv2h-usb2phy-reset.yaml +F: drivers/reset/reset-rzv2h-usb2phy.c + RENESAS RZ/V2M I2C DRIVER M: Fabrizio Castro L: linux-i2c@vger.kernel.org From 1c64de886b8893c0158097edd6ba08d527a2c97a Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Mon, 14 Apr 2025 06:34:59 +0800 Subject: [PATCH 7/7] dt-bindings: reset: sophgo: Add SG2044 bindings. The SG2044 shares the same reset controller as SG2042, so it is just enough to use the compatible string of SG2042 as a basis. Add compatible string for the reset controller of SG2044. Signed-off-by: Inochi Amaoto Acked-by: "Rob Herring (Arm)" Reviewed-by: Chen Wang Link: https://lore.kernel.org/r/20250413223507.46480-6-inochiama@gmail.com Signed-off-by: Philipp Zabel --- .../devicetree/bindings/reset/sophgo,sg2042-reset.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml b/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml index 76e1931f0908..1d1b84575960 100644 --- a/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml +++ b/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml @@ -11,7 +11,12 @@ maintainers: properties: compatible: - const: sophgo,sg2042-reset + oneOf: + - items: + - enum: + - sophgo,sg2044-reset + - const: sophgo,sg2042-reset + - const: sophgo,sg2042-reset reg: maxItems: 1