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drm/rockchip: dsi: Add support for PX30/RK1808/RK3128/RK3368
Change-Id: Ia9934a50c63e046e34ea694e10b0e1d17b53a6f0 Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
This commit is contained in:
Wyon Bi
Tao Huang
parent
b2028b88c9
commit
a96ba7fcd5
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@ -4,21 +4,32 @@ Rockchip specific extensions to the Synopsys Designware MIPI DSI
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Required properties:
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- #address-cells: Should be <1>.
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- #size-cells: Should be <0>.
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- compatible: "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi".
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"rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi".
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- compatible: must be one of:
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"rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi".
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"rockchip,rk1808-mipi-dsi", "snps,dw-mipi-dsi".
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"rockchip,rk3128-mipi-dsi", "snps,dw-mipi-dsi".
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"rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi".
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"rockchip,rk3368-mipi-dsi", "snps,dw-mipi-dsi".
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"rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi".
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- reg: Represent the physical address range of the controller.
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- interrupts: Represent the controller's interrupt to the CPU(s).
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- power-domains: a phandle to mipi dsi power domain node.
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- resets: list of phandle + reset specifier pairs, as described in [3].
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- reset-names: string reset name, must be "apb".
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- clocks, clock-names: Phandles to the controller's pll reference
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clock(ref) and APB clock(pclk). For RK3399, a phy config clock
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(phy_cfg) and a grf clock(grf) are required. As described in [1].
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- clocks, clock-names: Phandles to the controller's APB clock(pclk),
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As described in [1].
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- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
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- ports: contain a port node with endpoint definitions as defined in [2].
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For vopb,set the reg = <0> and set the reg = <1> for vopl.
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Optional properties:
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- clocks, clock-names:
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phandle to the SNPS-PHY config clock, name should be "phy_cfg".
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phandle to the SNPS-PHY PLL reference clock, name should be "ref".
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phandle to the Non-SNPS PHY high speed clock, name should be "hs_clk".
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- phys: phandle to Non-SNPS PHY node
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- phy-names: the string "mipi_dphy" when is found in a node, along with "phys"
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attribute, provides phandle to MIPI PHY node
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- rockchip,lane-rate: optional override of the desired bandwidth.
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- rockchip,dual-channel: for dual-channel mode, phandle to the slave channel.
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@ -27,7 +38,7 @@ Optional properties:
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[3] Documentation/devicetree/bindings/reset/reset.txt
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Example:
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mipi_dsi: mipi@ff960000 {
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dsi: dsi@ff960000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
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@ -44,16 +55,18 @@ Example:
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#size-cells = <0>;
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reg = <1>;
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mipi_in: port {
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port {
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_in_vopb: endpoint@0 {
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dsi_in_vopb: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&vopb_out_mipi>;
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remote-endpoint = <&vopb_out_dsi>;
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};
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mipi_in_vopl: endpoint@1 {
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dsi_in_vopl: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&vopl_out_mipi>;
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remote-endpoint = <&vopl_out_dsi>;
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};
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};
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};
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@ -17,6 +17,7 @@
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <linux/mfd/syscon.h>
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#include <linux/phy/phy.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_crtc_helper.h>
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@ -236,11 +237,16 @@ struct dw_mipi_dsi_plat_data {
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};
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struct mipi_dphy {
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/* SNPS PHY */
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struct regmap *regmap;
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struct clk *ref_clk;
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struct clk *cfg_clk;
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u16 input_div;
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u16 feedback_div;
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/* Non-SNPS PHY */
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struct phy *phy;
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struct clk *hs_clk;
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};
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struct dw_mipi_dsi {
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@ -502,7 +508,7 @@ static inline void mipi_dphy_rstz_deassert(struct dw_mipi_dsi *dsi)
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udelay(1);
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}
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static int mipi_dphy_power_on(struct dw_mipi_dsi *dsi)
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static void dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
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{
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struct mipi_dphy *dphy = &dsi->dphy;
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const struct {
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@ -523,28 +529,6 @@ static int mipi_dphy_power_on(struct dw_mipi_dsi *dsi)
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u8 hsfreqrange, counter;
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unsigned int index, txbyteclkhs;
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u16 n, m;
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unsigned int val, mask;
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int ret;
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mipi_dphy_enableclk_deassert(dsi);
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mipi_dphy_shutdownz_assert(dsi);
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mipi_dphy_rstz_assert(dsi);
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testif_testclr_assert(dsi);
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/* Configures DPHY to work as a Master */
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grf_field_write(dsi, MASTERSLAVEZ, 1);
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/* Configures lane as TX */
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grf_field_write(dsi, BASEDIR, 0);
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/* Set all REQUEST inputs to zero */
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grf_field_write(dsi, TURNREQUEST, 0);
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grf_field_write(dsi, TURNDISABLE, 0);
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grf_field_write(dsi, FORCETXSTOPMODE, 0);
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grf_field_write(dsi, FORCERXMODE, 0);
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udelay(1);
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testif_testclr_deassert(dsi);
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for (index = 0; index < ARRAY_SIZE(hsfreqrange_table); index++)
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if (dsi->lane_mbps <= hsfreqrange_table[index].max_lane_mbps)
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@ -568,6 +552,36 @@ static int mipi_dphy_power_on(struct dw_mipi_dsi *dsi)
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regmap_write(dphy->regmap, 0x17, INPUT_DIV(n));
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regmap_write(dphy->regmap, 0x18, FEEDBACK_DIV_LO(m));
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regmap_write(dphy->regmap, 0x18, FEEDBACK_DIV_HI(m >> 5));
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}
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static int mipi_dphy_power_on(struct dw_mipi_dsi *dsi)
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{
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struct mipi_dphy *dphy = &dsi->dphy;
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unsigned int val, mask;
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int ret;
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mipi_dphy_enableclk_deassert(dsi);
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mipi_dphy_shutdownz_assert(dsi);
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mipi_dphy_rstz_assert(dsi);
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testif_testclr_assert(dsi);
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/* Configures DPHY to work as a Master */
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grf_field_write(dsi, MASTERSLAVEZ, 1);
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/* Configures lane as TX */
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grf_field_write(dsi, BASEDIR, 0);
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/* Set all REQUEST inputs to zero */
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grf_field_write(dsi, TURNREQUEST, 0);
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grf_field_write(dsi, TURNDISABLE, 0);
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grf_field_write(dsi, FORCETXSTOPMODE, 0);
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grf_field_write(dsi, FORCERXMODE, 0);
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udelay(1);
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testif_testclr_deassert(dsi);
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if (!dphy->phy)
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dw_mipi_dsi_phy_init(dsi);
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/* Enable Data Lane Module */
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grf_field_write(dsi, ENABLE_N, GENMASK(dsi->lanes - 1, 0));
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@ -580,6 +594,17 @@ static int mipi_dphy_power_on(struct dw_mipi_dsi *dsi)
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mipi_dphy_rstz_deassert(dsi);
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usleep_range(1500, 2000);
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if (dphy->phy) {
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ret = phy_set_mode(dphy->phy, PHY_MODE_VIDEO_MIPI);
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if (ret) {
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DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n",
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ret);
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return ret;
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}
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phy_power_on(dphy->phy);
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}
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ret = regmap_read_poll_timeout(dsi->regmap, DSI_PHY_STATUS,
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val, val & PHY_LOCK, 0, 1000);
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if (ret < 0) {
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@ -605,7 +630,12 @@ static int mipi_dphy_power_on(struct dw_mipi_dsi *dsi)
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static void mipi_dphy_power_off(struct dw_mipi_dsi *dsi)
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{
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struct mipi_dphy *dphy = &dsi->dphy;
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regmap_write(dsi->regmap, DSI_PHY_RSTZ, 0);
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if (dphy->phy)
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phy_power_off(dphy->phy);
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}
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static const struct regmap_config testif_regmap_config = {
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@ -624,31 +654,52 @@ static int mipi_dphy_attach(struct dw_mipi_dsi *dsi)
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struct device *dev = dsi->dev;
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int ret;
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dphy->ref_clk = devm_clk_get(dev, "ref");
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if (IS_ERR(dphy->ref_clk)) {
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ret = PTR_ERR(dphy->ref_clk);
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DRM_DEV_ERROR(dev,
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"Unable to get pll reference clock: %d\n", ret);
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dphy->phy = devm_phy_optional_get(dev, "mipi_dphy");
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if (IS_ERR(dphy->phy)) {
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ret = PTR_ERR(dphy->phy);
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DRM_DEV_ERROR(dev, "failed to get mipi dphy: %d\n", ret);
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return ret;
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}
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dphy->cfg_clk = devm_clk_get(dev, "phy_cfg");
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if (IS_ERR(dphy->cfg_clk)) {
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if (PTR_ERR(dphy->cfg_clk) != -ENOENT) {
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ret = PTR_ERR(dphy->cfg_clk);
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DRM_DEV_ERROR(dev,
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"Unable to get phy cfg clk: %d\n", ret);
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if (dphy->phy) {
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dphy->hs_clk = devm_clk_get(dev, "hs_clk");
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if (IS_ERR(dphy->hs_clk)) {
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ret = PTR_ERR(dphy->hs_clk);
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DRM_DEV_ERROR(dev, "failed to get hs clock: %d\n", ret);
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return ret;
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}
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} else {
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dphy->ref_clk = devm_clk_get(dev, "ref");
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if (IS_ERR(dphy->ref_clk)) {
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ret = PTR_ERR(dphy->ref_clk);
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DRM_DEV_ERROR(dev,
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"Unable to get pll reference clock: %d\n",
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ret);
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return ret;
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}
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/* Clock is optional (for RK3288) */
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dphy->cfg_clk = NULL;
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}
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dphy->regmap = devm_regmap_init(dev, NULL, dsi, &testif_regmap_config);
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if (IS_ERR(dphy->regmap)) {
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ret = PTR_ERR(dphy->regmap);
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DRM_DEV_ERROR(dev, "failed to int phy regmap: %d\n", ret);
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return ret;
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dphy->cfg_clk = devm_clk_get(dev, "phy_cfg");
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if (IS_ERR(dphy->cfg_clk)) {
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if (PTR_ERR(dphy->cfg_clk) != -ENOENT) {
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ret = PTR_ERR(dphy->cfg_clk);
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DRM_DEV_ERROR(dev,
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"Unable to get phy cfg clk: %d\n",
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ret);
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return ret;
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}
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/* Clock is optional (for RK3288) */
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dphy->cfg_clk = NULL;
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}
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dphy->regmap = devm_regmap_init(dev, NULL, dsi,
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&testif_regmap_config);
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if (IS_ERR(dphy->regmap)) {
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ret = PTR_ERR(dphy->regmap);
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DRM_DEV_ERROR(dev, "failed to int phy regmap: %d\n",
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ret);
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return ret;
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}
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}
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return 0;
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@ -1235,12 +1286,23 @@ static void dw_mipi_dsi_enable(struct dw_mipi_dsi *dsi)
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dw_mipi_dsi_enable(dsi->slave);
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}
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static void dw_mipi_dsi_set_hs_clk(struct dw_mipi_dsi *dsi, unsigned long rate)
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{
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rate = clk_round_rate(dsi->dphy.hs_clk, rate);
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clk_set_rate(dsi->dphy.hs_clk, rate);
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dsi->lane_mbps = rate / USEC_PER_SEC;
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}
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static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
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{
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struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
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unsigned long lane_rate = dw_mipi_dsi_get_lane_rate(dsi);
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dw_mipi_dsi_calc_pll_cfg(dsi, lane_rate);
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if (dsi->dphy.phy)
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dw_mipi_dsi_set_hs_clk(dsi, lane_rate);
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else
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dw_mipi_dsi_calc_pll_cfg(dsi, lane_rate);
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DRM_DEV_INFO(dsi->dev, "final DSI-Link bandwidth: %u x %d Mbps\n",
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dsi->lane_mbps, dsi->slave ? dsi->lanes * 2 : dsi->lanes);
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@ -1615,6 +1677,7 @@ static int __maybe_unused dw_mipi_dsi_runtime_suspend(struct device *dev)
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struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
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clk_disable_unprepare(dsi->pclk);
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clk_disable_unprepare(dsi->dphy.hs_clk);
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clk_disable_unprepare(dsi->dphy.ref_clk);
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clk_disable_unprepare(dsi->dphy.cfg_clk);
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@ -1627,6 +1690,7 @@ static int __maybe_unused dw_mipi_dsi_runtime_resume(struct device *dev)
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clk_prepare_enable(dsi->dphy.cfg_clk);
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clk_prepare_enable(dsi->dphy.ref_clk);
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clk_prepare_enable(dsi->dphy.hs_clk);
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clk_prepare_enable(dsi->pclk);
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return 0;
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@ -1637,6 +1701,49 @@ static const struct dev_pm_ops dw_mipi_dsi_pm_ops = {
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dw_mipi_dsi_runtime_resume, NULL)
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};
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static const u32 px30_dsi_grf_reg_fields[MAX_FIELDS] = {
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[DPIUPDATECFG] = GRF_REG_FIELD(0x0434, 7, 7),
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[DPICOLORM] = GRF_REG_FIELD(0x0434, 3, 3),
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[DPISHUTDN] = GRF_REG_FIELD(0x0434, 2, 2),
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[FORCETXSTOPMODE] = GRF_REG_FIELD(0x0438, 7, 10),
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[FORCERXMODE] = GRF_REG_FIELD(0x0438, 6, 6),
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[TURNDISABLE] = GRF_REG_FIELD(0x0438, 5, 5),
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[VOPSEL] = GRF_REG_FIELD(0x0438, 0, 0),
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};
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static const struct dw_mipi_dsi_plat_data px30_mipi_dsi_plat_data = {
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.dsi0_grf_reg_fields = px30_dsi_grf_reg_fields,
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.max_bit_rate_per_lane = 1000000000UL,
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};
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static const u32 rk1808_dsi_grf_reg_fields[MAX_FIELDS] = {
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[MASTERSLAVEZ] = GRF_REG_FIELD(0x0440, 8, 8),
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[DPIUPDATECFG] = GRF_REG_FIELD(0x0440, 7, 7),
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[DPICOLORM] = GRF_REG_FIELD(0x0440, 3, 3),
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[DPISHUTDN] = GRF_REG_FIELD(0x0440, 2, 2),
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[FORCETXSTOPMODE] = GRF_REG_FIELD(0x0444, 7, 10),
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[FORCERXMODE] = GRF_REG_FIELD(0x0444, 6, 6),
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[TURNDISABLE] = GRF_REG_FIELD(0x0444, 5, 5),
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};
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static const struct dw_mipi_dsi_plat_data rk1808_mipi_dsi_plat_data = {
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.dsi0_grf_reg_fields = rk1808_dsi_grf_reg_fields,
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.max_bit_rate_per_lane = 2000000000UL,
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};
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static const u32 rk3128_dsi_grf_reg_fields[MAX_FIELDS] = {
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[FORCETXSTOPMODE] = GRF_REG_FIELD(0x0150, 10, 13),
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[FORCERXMODE] = GRF_REG_FIELD(0x0150, 9, 9),
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[TURNDISABLE] = GRF_REG_FIELD(0x0150, 8, 8),
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[DPICOLORM] = GRF_REG_FIELD(0x0150, 5, 5),
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[DPISHUTDN] = GRF_REG_FIELD(0x0150, 4, 4),
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};
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static const struct dw_mipi_dsi_plat_data rk3128_mipi_dsi_plat_data = {
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.dsi0_grf_reg_fields = rk3128_dsi_grf_reg_fields,
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.max_bit_rate_per_lane = 1000000000UL,
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};
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static const u32 rk3288_dsi0_grf_reg_fields[MAX_FIELDS] = {
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[DPICOLORM] = GRF_REG_FIELD(0x025c, 8, 8),
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[DPISHUTDN] = GRF_REG_FIELD(0x025c, 7, 7),
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@ -1669,6 +1776,20 @@ static const struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_plat_data = {
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.max_bit_rate_per_lane = 1500000000UL,
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};
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static const u32 rk3368_dsi_grf_reg_fields[MAX_FIELDS] = {
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[DPIUPDATECFG] = GRF_REG_FIELD(0x0418, 7, 7),
|
||||
[DPICOLORM] = GRF_REG_FIELD(0x0418, 3, 3),
|
||||
[DPISHUTDN] = GRF_REG_FIELD(0x0418, 2, 2),
|
||||
[FORCETXSTOPMODE] = GRF_REG_FIELD(0x041c, 7, 10),
|
||||
[FORCERXMODE] = GRF_REG_FIELD(0x041c, 6, 6),
|
||||
[TURNDISABLE] = GRF_REG_FIELD(0x041c, 5, 5),
|
||||
};
|
||||
|
||||
static const struct dw_mipi_dsi_plat_data rk3368_mipi_dsi_plat_data = {
|
||||
.dsi0_grf_reg_fields = rk3368_dsi_grf_reg_fields,
|
||||
.max_bit_rate_per_lane = 1000000000UL,
|
||||
};
|
||||
|
||||
static const u32 rk3399_dsi0_grf_reg_fields[MAX_FIELDS] = {
|
||||
[DPIUPDATECFG] = GRF_REG_FIELD(0x6224, 15, 15),
|
||||
[DPISHUTDN] = GRF_REG_FIELD(0x6224, 14, 14),
|
||||
|
|
@ -1703,8 +1824,20 @@ static const struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_plat_data = {
|
|||
|
||||
static const struct of_device_id dw_mipi_dsi_dt_ids[] = {
|
||||
{
|
||||
.compatible = "rockchip,px30-mipi-dsi",
|
||||
.data = &px30_mipi_dsi_plat_data,
|
||||
}, {
|
||||
.compatible = "rockchip,rk1808-mipi-dsi",
|
||||
.data = &rk1808_mipi_dsi_plat_data,
|
||||
}, {
|
||||
.compatible = "rockchip,rk3128-mipi-dsi",
|
||||
.data = &rk3128_mipi_dsi_plat_data,
|
||||
}, {
|
||||
.compatible = "rockchip,rk3288-mipi-dsi",
|
||||
.data = &rk3288_mipi_dsi_plat_data,
|
||||
}, {
|
||||
.compatible = "rockchip,rk3368-mipi-dsi",
|
||||
.data = &rk3368_mipi_dsi_plat_data,
|
||||
}, {
|
||||
.compatible = "rockchip,rk3399-mipi-dsi",
|
||||
.data = &rk3399_mipi_dsi_plat_data,
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user