From 25ee898961a2c661e4cd72bc98f0060f1cd11222 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Sven=20P=C3=BCschel?= Date: Thu, 21 May 2026 00:44:33 +0200 Subject: [PATCH 01/16] arm64: dts: rockchip: add rga3 dt nodes to rk3588 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add devicetree nodes for the RGA3 (Raster Graphics Acceleration 3) peripheral in the RK3588. The existing rga node refers to the RGA2-Enhanced peripheral. The RK3588 contains one RGA2-Enhanced core and two RGA3 cores. Both feature a similar functionality of scaling, cropping and rotating of up to two input images into one output image. Key differences of the RGA3 are: - supports 10bit YUV output formats - supports 8x8 tiles and FBCD as inputs and outputs - supports BT2020 color space conversion - max output resolution of (8192-64)x(8192-64) - MMU can map up to 32G DDR RAM - fully planar formats (3 planes) are not supported - max scale up/down factor of 8 (RGA2 allows up to 16) Signed-off-by: Sven Püschel Link: https://patch.msgid.link/20260521-spu-rga3-v7-28-3f33e8c7145f@pengutronix.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 4535e0b6e979..4aff2701febf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1262,6 +1262,50 @@ vpu121_mmu: iommu@fdb50800 { #iommu-cells = <0>; }; + rga3_core0: rga@fdb60000 { + compatible = "rockchip,rk3588-rga3"; + reg = <0x0 0xfdb60000 0x0 0x200>; + interrupts = ; + clocks = <&cru ACLK_RGA3_0>, <&cru HCLK_RGA3_0>, <&cru CLK_RGA3_0_CORE>; + clock-names = "aclk", "hclk", "sclk"; + resets = <&cru SRST_RGA3_0_CORE>, <&cru SRST_A_RGA3_0>, <&cru SRST_H_RGA3_0>; + reset-names = "core", "axi", "ahb"; + power-domains = <&power RK3588_PD_RGA30>; + iommus = <&rga3_0_mmu>; + }; + + rga3_0_mmu: iommu@fdb60f00 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdb60f00 0x0 0x100>; + interrupts = ; + clocks = <&cru ACLK_RGA3_0>, <&cru HCLK_RGA3_0>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_RGA30>; + }; + + rga3_core1: rga@fdb70000 { + compatible = "rockchip,rk3588-rga3"; + reg = <0x0 0xfdb70000 0x0 0x200>; + interrupts = ; + clocks = <&cru ACLK_RGA3_1>, <&cru HCLK_RGA3_1>, <&cru CLK_RGA3_1_CORE>; + clock-names = "aclk", "hclk", "sclk"; + resets = <&cru SRST_RGA3_1_CORE>, <&cru SRST_A_RGA3_1>, <&cru SRST_H_RGA3_1>; + reset-names = "core", "axi", "ahb"; + power-domains = <&power RK3588_PD_RGA31>; + iommus = <&rga3_1_mmu>; + }; + + rga3_1_mmu: iommu@fdb70f00 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdb70f00 0x0 0x100>; + interrupts = ; + clocks = <&cru ACLK_RGA3_1>, <&cru HCLK_RGA3_1>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_RGA31>; + }; + rga: rga@fdb80000 { compatible = "rockchip,rk3588-rga", "rockchip,rk3288-rga"; reg = <0x0 0xfdb80000 0x0 0x180>; From d8d7e7549312c50fa5dcd69a6dc6f0035e770c09 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Sat, 23 May 2026 15:02:40 +0100 Subject: [PATCH 02/16] arm64: dts: rockchip: Add EL2 virtual timer interrupt The ARMv8.2 based CPUs used in a number of Rockchip SoCs are missing the EL2 virtual timer interrupt. Add it. Signed-off-by: Marc Zyngier Link: https://patch.msgid.link/20260523140242.586031-16-maz@kernel.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi index 64bdd8b7754b..a5832895bd39 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -195,7 +195,8 @@ timer { interrupts = , , , - ; + , + ; arm,no-tick-in-suspend; }; From c7126247fb797127ced68691583932d0a05bbd68 Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Fri, 22 May 2026 23:23:11 +0200 Subject: [PATCH 03/16] arm64: dts: rockchip: add vicap node to rk3588 Add the device tree node for the RK3588 Video Capture (VICAP) unit. Signed-off-by: Michael Riesch [converted reg values in vicap ports to hexadecimal, to have them align with the port@X values, and be less confusing] Link: https://patch.msgid.link/20260522-rk3588-vicap-v5-5-d1d1f5265c56@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 91 +++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 4aff2701febf..a22da6671da3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1474,6 +1474,89 @@ av1d: video-codec@fdc70000 { resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; }; + vicap: video-capture@fdce0000 { + compatible = "rockchip,rk3588-vicap"; + reg = <0x0 0xfdce0000 0x0 0x800>; + interrupts = ; + clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, + <&cru DCLK_VICAP>, <&cru ICLK_CSIHOST0>, + <&cru ICLK_CSIHOST1>; + clock-names = "aclk", "hclk", "dclk", "iclk", "iclk1"; + iommus = <&vicap_mmu>; + power-domains = <&power RK3588_PD_VI>; + resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, + <&cru SRST_D_VICAP>, <&cru SRST_CSIHOST0_VICAP>, + <&cru SRST_CSIHOST1_VICAP>, + <&cru SRST_CSIHOST2_VICAP>, + <&cru SRST_CSIHOST3_VICAP>, + <&cru SRST_CSIHOST4_VICAP>, + <&cru SRST_CSIHOST5_VICAP>; + reset-names = "arst", "hrst", "drst", "irst0", "irst1", + "irst2", "irst3", "irst4", "irst5"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + vicap_dvp: port@0 { + reg = <0x0>; + }; + + vicap_mipi0: port@1 { + reg = <0x1>; + }; + + vicap_mipi1: port@2 { + reg = <0x2>; + }; + + vicap_mipi2: port@3 { + reg = <0x3>; + + vicap_mipi2_input: endpoint { + remote-endpoint = <&csi2_output>; + }; + }; + + vicap_mipi3: port@4 { + reg = <0x4>; + }; + + vicap_mipi4: port@5 { + reg = <0x5>; + + vicap_mipi4_input: endpoint { + remote-endpoint = <&csi4_output>; + }; + }; + + vicap_mipi5: port@6 { + reg = <0x6>; + }; + + vicap_toisp0: port@10 { + reg = <0x10>; + }; + + vicap_toisp1: port@11 { + reg = <0x11>; + }; + }; + }; + + vicap_mmu: iommu@fdce0800 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdce0800 0x0 0x40>, <0x0 0xfdce0900 0x0 0x40>; + interrupts = ; + clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_VI>; + rockchip,disable-mmu-reset; + status = "disabled"; + }; + csi2: csi@fdd30000 { compatible = "rockchip,rk3588-mipi-csi2", "rockchip,rk3568-mipi-csi2"; reg = <0x0 0xfdd30000 0x0 0x10000>; @@ -1496,6 +1579,10 @@ csi2_in: port@0 { csi2_out: port@1 { reg = <1>; + + csi2_output: endpoint { + remote-endpoint = <&vicap_mipi2_input>; + }; }; }; }; @@ -1522,6 +1609,10 @@ csi4_in: port@0 { csi4_out: port@1 { reg = <1>; + + csi4_output: endpoint { + remote-endpoint = <&vicap_mipi4_input>; + }; }; }; }; From bfc2779116ab7636a08c254d76a7a43d06feae1c Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Fri, 22 May 2026 23:23:12 +0200 Subject: [PATCH 04/16] arm64: dts: rockchip: add radxa camera 4k on rock 5b+ cam0 Add device tree overlay for the Radxa Camera 4K (featuring the Sony IMX415 image sensor) to applied on the Radxa ROCK 5B+ CAM0 port. Signed-off-by: Michael Riesch Link: https://patch.msgid.link/20260522-rk3588-vicap-v5-6-d1d1f5265c56@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 5 + .../rk3588-rock-5b-plus-radxa-cam4k-cam0.dtso | 99 +++++++++++++++++++ 2 files changed, 104 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus-radxa-cam4k-cam0.dtso diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index cb55c6b70d0e..d4ff476fb981 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -206,6 +206,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-plus.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-plus-radxa-cam4k-cam0.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5t.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou-video-demo.dtbo @@ -321,6 +322,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtb rk3588-rock-5b-pcie-srns-dtbs := rk3588-rock-5b.dtb \ rk3588-rock-5b-pcie-srns.dtbo +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-plus-radxa-4k-cam.dtb +rk3588-rock-5b-plus-radxa-4k-cam-dtbs := rk3588-rock-5b-plus.dtb \ + rk3588-rock-5b-plus-radxa-cam4k-cam0.dtbo + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou-haikou-video-demo.dtb rk3588-tiger-haikou-haikou-video-demo-dtbs := rk3588-tiger-haikou.dtb \ rk3588-tiger-haikou-video-demo.dtbo diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus-radxa-cam4k-cam0.dtso b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus-radxa-cam4k-cam0.dtso new file mode 100644 index 000000000000..ee9ecf68a886 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus-radxa-cam4k-cam0.dtso @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device tree overlay for the Radxa Camera 4K attached to the CAM0 port of + * the Radxa ROCK 5B+. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +&{/} { + savdd_cam0: regulator-savdd-cam0 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-name = "savdd_cam0"; + vin-supply = <&vcc_3v3_s3>; + }; + + sdvdd_cam0: regulator-sdvdd-cam0 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "sdvdd_cam0"; + vin-supply = <&vcc5v0_sys>; + }; + + siovdd_cam0: regulator-siovdd-cam0 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "siovdd_cam0"; + vin-supply = <&vcc_3v3_s3>; + }; +}; + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + imx415: camera-sensor@1a { + compatible = "sony,imx415"; + reg = <0x1a>; + assigned-clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + assigned-clock-rates = <37125000>; + avdd-supply = <&savdd_cam0>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + dvdd-supply = <&sdvdd_cam0>; + orientation = <2>; /* External */ + ovdd-supply = <&siovdd_cam0>; + pinctrl-names = "default"; + pinctrl-0 = <&cam0_rstn &mipim0_camera3_clk>; + reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>; + + port { + imx415_output: endpoint { + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <445500000>; + remote-endpoint = <&csi2_input>; + }; + }; + }; +}; + +&pinctrl { + cam0 { + cam0_rstn: cam0-rstn-pinctrl { + rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&csi2 { + status = "okay"; +}; + +&csi2_in { + csi2_input: endpoint { + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <445500000>; + remote-endpoint = <&imx415_output>; + }; +}; + +&csi_dphy0 { + status = "okay"; +}; + +&vicap { + status = "okay"; +}; + +&vicap_mmu { + status = "okay"; +}; From a34ae4f44c9ff4f4170dd21cdb22efad63710af4 Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Fri, 22 May 2026 23:23:13 +0200 Subject: [PATCH 05/16] arm64: dts: rockchip: add radxa camera 4k on rock 5b+ cam1 Add device tree overlay for the Radxa Camera 4K (featuring the Sony IMX415 image sensor) to applied on the Radxa ROCK 5B+ CAM1 port. Signed-off-by: Michael Riesch Link: https://patch.msgid.link/20260522-rk3588-vicap-v5-7-d1d1f5265c56@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 4 +- .../rk3588-rock-5b-plus-radxa-cam4k-cam1.dtso | 99 +++++++++++++++++++ 2 files changed, 102 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus-radxa-cam4k-cam1.dtso diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index d4ff476fb981..761d82b4f4f2 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -207,6 +207,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-plus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-plus-radxa-cam4k-cam0.dtbo +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-plus-radxa-cam4k-cam1.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5t.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou-video-demo.dtbo @@ -324,7 +325,8 @@ rk3588-rock-5b-pcie-srns-dtbs := rk3588-rock-5b.dtb \ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-plus-radxa-4k-cam.dtb rk3588-rock-5b-plus-radxa-4k-cam-dtbs := rk3588-rock-5b-plus.dtb \ - rk3588-rock-5b-plus-radxa-cam4k-cam0.dtbo + rk3588-rock-5b-plus-radxa-cam4k-cam0.dtbo \ + rk3588-rock-5b-plus-radxa-cam4k-cam1.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou-haikou-video-demo.dtb rk3588-tiger-haikou-haikou-video-demo-dtbs := rk3588-tiger-haikou.dtb \ diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus-radxa-cam4k-cam1.dtso b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus-radxa-cam4k-cam1.dtso new file mode 100644 index 000000000000..8a4cf3fdbf8e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus-radxa-cam4k-cam1.dtso @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device tree overlay for the Radxa Camera 4K attached to the CAM1 port of + * the Radxa ROCK 5B+. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +&{/} { + savdd_cam1: regulator-savdd-cam1 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-name = "savdd_cam1"; + vin-supply = <&vcc_3v3_s3>; + }; + + sdvdd_cam1: regulator-sdvdd-cam1 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "sdvdd_cam1"; + vin-supply = <&vcc5v0_sys>; + }; + + siovdd_cam1: regulator-siovdd-cam1 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "siovdd_cam1"; + vin-supply = <&vcc_3v3_s3>; + }; +}; + +&i2c4 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + cam1_imx415: camera-sensor@1a { + compatible = "sony,imx415"; + reg = <0x1a>; + assigned-clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; + assigned-clock-rates = <37125000>; + avdd-supply = <&savdd_cam1>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; + dvdd-supply = <&sdvdd_cam1>; + orientation = <2>; /* External */ + ovdd-supply = <&siovdd_cam1>; + pinctrl-names = "default"; + pinctrl-0 = <&cam1_rstn &mipim0_camera4_clk>; + reset-gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>; + + port { + cam1_imx415_output: endpoint { + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <445500000>; + remote-endpoint = <&csi4_input>; + }; + }; + }; +}; + +&pinctrl { + cam1 { + cam1_rstn: cam1-rstn-pinctrl { + rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&csi4 { + status = "okay"; +}; + +&csi4_in { + csi4_input: endpoint { + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <445500000>; + remote-endpoint = <&cam1_imx415_output>; + }; +}; + +&csi_dphy1 { + status = "okay"; +}; + +&vicap { + status = "okay"; +}; + +&vicap_mmu { + status = "okay"; +}; From ab1375e25ea3fef62a4a5a93abf5d03d67aaf99c Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 6 May 2026 00:52:43 +0800 Subject: [PATCH 06/16] arm64: dts: rockchip: Fix EEPROM compatible on rk3399-nanopi-r4s-enterprise The EEPROM used on the R4S (enterprise) is the 24AA025E48T-I/OT from MicroChip. This is a 2-Kbit EEPROM with 16-byte page size. The latter half of the EEPROM is read-only, and the last 48 bits contain a globally unique MAC address. That is to say this is not an ordinary EEPROM. The compatible for this type of EEPROM was introduced later that the board. Switch over to the correct compatible now that it is available. Signed-off-by: Chen-Yu Tsai Link: https://patch.msgid.link/20260505165244.1902-1-wens@kernel.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-enterprise.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-enterprise.dts b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-enterprise.dts index b76f98962076..e366f1a04b32 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-enterprise.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-enterprise.dts @@ -16,7 +16,7 @@ &gmac { &i2c2 { eeprom@51 { - compatible = "microchip,24c02", "atmel,24c02"; + compatible = "microchip,24aa025e48"; reg = <0x51>; pagesize = <16>; size = <256>; From 8333fe46b0010d110b36f1628dd8dfc77d2c389a Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 6 May 2026 01:29:02 +0800 Subject: [PATCH 07/16] arm64: dts: rockchip: Disable removed devices from rk3399-nanopi-r4s While the design of the NanoPi R4S is based on the common NanoPi 4 family, it is trimmed down a lot. Disable all the peripherals on the SoC that are not used, and delete all the external components that are not present. Signed-off-by: Chen-Yu Tsai [feels like the cleaner option, than to move those peripherals into a new rk3399-nanopi-allothers.dtsi, as the r4s variants are not as many ] Link: https://patch.msgid.link/20260505172903.33271-1-wens@kernel.org Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3399-nanopi-r4s.dtsi | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi index 3a9a10f531bd..4274d1b6e80a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi @@ -66,16 +66,41 @@ &emmc_phy { status = "disabled"; }; +/* No USB type-C PD power manager */ +/delete-node/ &fusb0; + +&i2c1 { + status = "disabled"; +}; + &i2c4 { status = "disabled"; }; +&i2c7 { + status = "disabled"; +}; + +&i2s2 { + status = "disabled"; +}; + +&hdmi { + status = "disabled"; +}; + +&hdmi_sound { + status = "disabled"; +}; + &pcie0 { num-lanes = <1>; vpcie3v3-supply = <&vcc3v3_sys>; }; &pinctrl { + /delete-node/ fusb30x; + gpio-leds { /delete-node/ status-led-pin; @@ -101,14 +126,21 @@ reset_button_pin: reset-button-pin { }; }; +&pwm0 { + status = "disabled"; +}; + &sdhci { status = "disabled"; }; &sdio0 { + /delete-property/ mmc-pwrseq; status = "disabled"; }; +/delete-node/ &sdio_pwrseq; + &u2phy0_host { phy-supply = <&vdd_5v>; }; @@ -119,12 +151,48 @@ &u2phy1_host { &uart0 { status = "disabled"; + + /delete-node/ bluetooth; }; +&u2phy1_host { + status = "disabled"; +}; + +&usb_host1_ehci { + status = "disabled"; +}; + +&usb_host1_ohci { + status = "disabled"; +}; &usbdrd_dwc3_0 { dr_mode = "host"; }; +/delete-node/ &vbus_typec; + &vcc3v3_sys { vin-supply = <&vcc5v0_sys>; }; + +&vopb { + status = "disabled"; +}; + +&vopb_mmu { + status = "disabled"; +}; + +&vopl { + status = "disabled"; +}; + +&vopl_mmu { + status = "disabled"; +}; + +/delete-node/ &bt_host_wake_l; +/delete-node/ &bt_reg_on_h; +/delete-node/ &bt_wake_l; +/delete-node/ &wifi_reg_on_h; From 720fe68fd9f138ada2936ffcf3dd0129a889455a Mon Sep 17 00:00:00 2001 From: Gray Huang Date: Thu, 7 May 2026 11:35:40 +0800 Subject: [PATCH 08/16] arm64: dts: rockchip: Enable USB for Khadas Edge 2L The Khadas Edge 2L board provides one USB 3.0 Host port and one USB 2.0 port (connected via an internal hub). Enable the corresponding DWC3 controllers and PHYs. Signed-off-by: Gray Huang Link: https://patch.msgid.link/20260507033541.2576335-2-gray.huang@wesion.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3576-khadas-edge-2l.dts | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts b/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts index e7fe22eb31a3..967a95ce01de 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts @@ -30,6 +30,29 @@ hdmi_con_in: endpoint { }; }; + vcc5v0_device: regulator-vcc5v0-device { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_device"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_host: regulator-vcc5v0-host { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren>; + vin-supply = <&vcc5v0_device>; + }; + vcc_sys: regulator-vcc5v0-sys { compatible = "regulator-fixed"; regulator-name = "vcc_sys"; @@ -78,6 +101,10 @@ &combphy0_ps { status = "okay"; }; +&combphy1_psu { + status = "okay"; +}; + &cpu_l0 { cpu-supply = <&vdd_cpu_lit_s0>; }; @@ -531,6 +558,12 @@ pcie0_rst: pcie0-rst { }; }; + usb { + usb_host_pwren: usb-host-pwren { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + wifi { wifi_reg_on: wifi-reg-on { rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; @@ -552,10 +585,24 @@ &sdhci { status = "okay"; }; +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + &uart0 { status = "okay"; }; +&usb_drd1_dwc3 { + dr_mode = "host"; + status = "okay"; +}; + &vop { status = "okay"; }; From ef81db2fdd5a75e3834a4726dc7837f6d2a7229d Mon Sep 17 00:00:00 2001 From: Gray Huang Date: Thu, 7 May 2026 11:35:41 +0800 Subject: [PATCH 09/16] arm64: dts: rockchip: Add Bluetooth support for Khadas Edge 2L Enable Bluetooth support for the Ampak AP6275P module on the Khadas Edge 2L. This involves enabling the UART5 interface for HCI communication and defining the required regulators and power-sequence pins. Signed-off-by: Gray Huang Link: https://patch.msgid.link/20260507033541.2576335-3-gray.huang@wesion.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3576-khadas-edge-2l.dts | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts b/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts index 967a95ce01de..3121a0ba7c7c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts @@ -552,6 +552,20 @@ wifi: wifi@0,0 { }; &pinctrl { + bluetooth { + bt_reg_on: bt-reg-on { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + bt_wake_host: bt-wake-host { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + host_wake_bt: host-wake-bt { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + pcie0 { pcie0_rst: pcie0-rst { rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; @@ -598,6 +612,27 @@ &uart0 { status = "okay"; }; +&uart5 { + pinctrl-0 = <&uart5m1_xfer &uart5m1_ctsn &uart5m1_rtsn>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&hym8563>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-0 = <&bt_reg_on &bt_wake_host &host_wake_bt>; + pinctrl-names = "default"; + shutdown-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + vbat-supply = <&vcc_3v3_s3>; + vddio-supply = <&vcc_1v8_s3>; + }; +}; + &usb_drd1_dwc3 { dr_mode = "host"; status = "okay"; From dc98bd71f41db3666aa8505cc8c72d02653d2980 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Mon, 1 Jun 2026 18:10:00 +0800 Subject: [PATCH 10/16] arm64: dts: rockchip: enable adc button for Radxa E25 The Radxa E25 board has an ADC button. Enable it. Signed-off-by: Chukun Pan Link: https://patch.msgid.link/20260601101000.2076721-1-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts index 98cfa3abb809..a091c3a44747 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts @@ -1,6 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /dts-v1/; +#include #include "rk3568-radxa-cm3i.dtsi" / { @@ -11,6 +12,19 @@ aliases { mmc1 = &sdmmc0; }; + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + + button-recovery { + label = "Recovery"; + linux,code = ; + press-threshold-microvolt = <0>; + }; + }; + pwm-leds { compatible = "pwm-leds-multicolor"; From 5f3ae9b12a6c523992a7216bbc4420ac33450b79 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 29 May 2026 21:03:51 +0200 Subject: [PATCH 11/16] arm64: dts: rockchip: Add USB nodes for RK3528 Rockchip RK3528 has one USB 3.0 DWC3 controller and oneUSB 2.0 EHCI/OHCI controller and uses an Innosilicon-USB2PHY for USB 2.0. The DWC3 controller additionally uses the Naneng Combo PHY for USB3. Add device tree nodes to describe these USB controllers along with the USB 2.0 PHYs. [moved snps,dis_u2_susphy_quirk here from individual boards, describe both usb2+3 default phy connections, usb2 boards can override] Signed-off-by: Jonas Karlman Signed-off-by: Heiko Stuebner Link: https://patch.msgid.link/20260529190355.4148175-2-heiko@sntech.de --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 80 ++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi index 77d314716b43..03cd00f88dbb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -336,6 +336,33 @@ pcie_intc: legacy-interrupt-controller { }; }; + usb_host0_xhci: usb@fe500000 { + compatible = "rockchip,rk3528-dwc3", "snps,dwc3"; + reg = <0x0 0xfe500000 0x0 0x400000>; + clocks = <&cru CLK_REF_USB3OTG>, + <&cru CLK_SUSPEND_USB3OTG>, + <&cru ACLK_USB3OTG>; + clock-names = "ref_clk", "suspend_clk", "bus_clk"; + interrupts = ; + power-domains = <&power RK3528_PD_VPU>; + resets = <&cru SRST_A_USB3OTG>; + dr_mode = "otg"; + phys = <&usb2phy_otg>, <&combphy PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis_rxdet_inp3_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis_u2_susphy_quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + status = "disabled"; + }; + gic: interrupt-controller@fed01000 { compatible = "arm,gic-400"; reg = <0x0 0xfed01000 0 0x1000>, @@ -349,6 +376,30 @@ gic: interrupt-controller@fed01000 { #interrupt-cells = <3>; }; + usb_host0_ehci: usb@ff100000 { + compatible = "generic-ehci"; + reg = <0x0 0xff100000 0x0 0x40000>; + clocks = <&cru HCLK_USBHOST>, <&cru HCLK_USBHOST_ARB>, + <&usb2phy>; + interrupts = ; + phys = <&usb2phy_host>; + phy-names = "usb"; + power-domains = <&power RK3528_PD_VO>; + status = "disabled"; + }; + + usb_host0_ohci: usb@ff140000 { + compatible = "generic-ohci"; + reg = <0x0 0xff140000 0x0 0x40000>; + clocks = <&cru HCLK_USBHOST>, <&cru HCLK_USBHOST_ARB>, + <&usb2phy>; + interrupts = ; + phys = <&usb2phy_host>; + phy-names = "usb"; + power-domains = <&power RK3528_PD_VO>; + status = "disabled"; + }; + qos_crypto_a: qos@ff200000 { compatible = "rockchip,rk3528-qos", "syscon"; reg = <0x0 0xff200000 0x0 0x20>; @@ -1281,6 +1332,35 @@ combphy: phy@ffdc0000 { rockchip,pipe-phy-grf = <&pipe_phy_grf>; status = "disabled"; }; + + usb2phy: usb2phy@ffdf0000 { + compatible = "rockchip,rk3528-usb2phy"; + reg = <0x0 0xffdf0000 0x0 0x10000>; + clocks = <&cru CLK_REF_USBPHY>, <&cru PCLK_USBPHY>; + clock-names = "phyclk", "pclk"; + #clock-cells = <0>; + clock-output-names = "clk_usbphy_480m"; + power-domains = <&power RK3528_PD_VO>; + rockchip,usbgrf = <&vo_grf>; + status = "disabled"; + + usb2phy_otg: otg-port { + interrupts = , + , + ; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + + usb2phy_host: host-port { + interrupts = ; + interrupt-names = "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + }; }; }; From e897bcf81dd920bf80ace6d98ec6f9645c5b50f2 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 29 May 2026 21:03:52 +0200 Subject: [PATCH 12/16] arm64: dts: rockchip: Enable USB 2.0 ports on Radxa E20C The Radxa E20C has one USB2.0 Type-A HOST port and one USB2.0 Type-C port. The Type-C port is conneced to a FE1.1s_QFN USB hub on the board, with its ports being connected to the XHCI usb controller and an usb-uart bridge. This also means, the XHCI controller can only be used in device-mode. Add support for using the USB 2.0 ports on Radxa E20C. Signed-off-by: Jonas Karlman [set xhci to peripheral and add comment about the outward-facing hub] Signed-off-by: Heiko Stuebner Link: https://patch.msgid.link/20260529190355.4148175-3-heiko@sntech.de --- .../boot/dts/rockchip/rk3528-radxa-e20c.dts | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts index b32452756155..f872b8d20ebc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts @@ -134,6 +134,18 @@ vcc5v0_sys: regulator-5v0-vcc-sys { regulator-max-microvolt = <5000000>; }; + vcc5v0_usb20: regulator-5v0-vcc-usb20 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_en>; + regulator-name = "vcc5v0_usb20"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + vccio_sd: regulator-vccio-sd { compatible = "regulator-gpio"; gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; @@ -273,6 +285,12 @@ sdmmc_vol_ctrl_h: sdmmc-vol-ctrl-h { rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + usb { + usb_host_en: usb-host-en { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &pwm1 { @@ -320,3 +338,45 @@ &uart0 { pinctrl-0 = <&uart0m0_xfer>; status = "okay"; }; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +/* + * The usb controller can only work in peripheral mode, as it is + * connected to one of the ports of an outward-facing usb hub. + * + * type_c-port (hub-input) + * | + * usb-hub + * | | + * uart-usb usb-host0 + * | + * uart0 + */ +&usb_host0_xhci { + dr_mode = "peripheral"; + extcon = <&usb2phy>; + maximum-speed = "high-speed"; + phys = <&usb2phy_otg>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usb2phy { + status = "okay"; +}; + +&usb2phy_host { + phy-supply = <&vcc5v0_usb20>; + status = "okay"; +}; + +&usb2phy_otg { + status = "okay"; +}; From 4e55d52f5f3b333a9ff5103099df97291aaeb083 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 29 May 2026 21:03:53 +0200 Subject: [PATCH 13/16] arm64: dts: rockchip: Enable USB ports on Radxa ROCK 2A/2F The ROCK 2A has three USB 2.0 Type-A HOST ports behind an onboard USB hub, and one USB 3.0 Type-A port. And the ROCK 2F has two USB 2.0 Type-A HOST ports behind an onboard USB hub, and one USB 2.0 Type-C OTG port. Add support for using the USB ports on Radxa ROCK 2A/2F. The onboard USB hub handles OHCI so only the EHCI controller is enabled. Signed-off-by: Jonas Karlman Signed-off-by: Heiko Stuebner Link: https://patch.msgid.link/20260529190355.4148175-4-heiko@sntech.de --- arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi | 17 +++++++++++++++++ arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dts | 11 +++++++++++ arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dts | 12 ++++++++++++ 3 files changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi b/arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi index aedc7ee9ee46..501a91f4c23e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi @@ -166,6 +166,10 @@ rfkill { }; }; +&combphy { + status = "okay"; +}; + &cpu0 { cpu-supply = <&vdd_arm>; }; @@ -291,3 +295,16 @@ &uart0 { pinctrl-0 = <&uart0m0_xfer>; status = "okay"; }; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb2phy { + status = "okay"; +}; + +&usb2phy_host { + phy-supply = <&vcc5v0_usb20>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dts b/arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dts index 0b696d49b71f..5e17ec2758d5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dts @@ -79,3 +79,14 @@ usb_otg_en: usb-otg-en { }; }; }; + +&usb_host0_xhci { + dr_mode = "host"; + extcon = <&usb2phy>; + status = "okay"; +}; + +&usb2phy_otg { + phy-supply = <&vcc5v0_usb30_otg>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dts b/arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dts index 3e2b9b685cb2..f2b021ff5046 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dts +++ b/arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dts @@ -8,3 +8,15 @@ / { model = "Radxa ROCK 2F"; compatible = "radxa,rock-2f", "rockchip,rk3528"; }; + +&usb_host0_xhci { + extcon = <&usb2phy>; + maximum-speed = "high-speed"; + phys = <&usb2phy_otg>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usb2phy_otg { + status = "okay"; +}; From b6b74087f90a201cfdd6da6a43e7b92dba8370e3 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 29 May 2026 21:03:54 +0200 Subject: [PATCH 14/16] arm64: dts: rockchip: Enable USB 2.0 ports on ArmSoM Sige1 The ArmSoM Sige1 has two USB 2.0 Type-A HOST ports behind an onboard USB hub, and one USB 2.0 Type-C OTG port. Add support for using the USB 2.0 ports on ArmSoM Sige1. The onboard USB hub handles OHCI so only the EHCI controller is enabled. Signed-off-by: Jonas Karlman [added phy-supply for otg port] Signed-off-by: Heiko Stuebner Link: https://patch.msgid.link/20260529190355.4148175-5-heiko@sntech.de --- .../boot/dts/rockchip/rk3528-armsom-sige1.dts | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts b/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts index c41af8fc0c8d..ee4183fb980d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts @@ -480,3 +480,28 @@ bluetooth { vddio-supply = <&vcc_1v8>; }; }; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_xhci { + extcon = <&usb2phy>; + maximum-speed = "high-speed"; + phys = <&usb2phy_otg>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usb2phy { + status = "okay"; +}; + +&usb2phy_host { + status = "okay"; +}; + +&usb2phy_otg { + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; From ff660109f4129a13bbdc31bc14ca233ebf0c9450 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 29 May 2026 21:03:55 +0200 Subject: [PATCH 15/16] arm64: dts: rockchip: Enable USB 2.0 ports on NanoPi Zero2 The NanoPi Zero2 has one USB 2.0 Type-A HOST port and one USB 2.0 Type-C OTG port. Add support for using the USB 2.0 ports on NanoPi Zero2. Signed-off-by: Jonas Karlman Signed-off-by: Heiko Stuebner Link: https://patch.msgid.link/20260529190355.4148175-6-heiko@sntech.de --- .../boot/dts/rockchip/rk3528-nanopi-zero2.dts | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dts b/arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dts index 9f683033c5f3..97d85124d21b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dts @@ -338,3 +338,32 @@ &uart0 { pinctrl-0 = <&uart0m0_xfer>; status = "okay"; }; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + extcon = <&usb2phy>; + maximum-speed = "high-speed"; + phys = <&usb2phy_otg>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usb2phy { + status = "okay"; +}; + +&usb2phy_host { + phy-supply = <&usb2_host_5v>; + status = "okay"; +}; + +&usb2phy_otg { + status = "okay"; +}; From 8545eda00fdf3d7e17933ce0f706d005b1bad42d Mon Sep 17 00:00:00 2001 From: Hugo Osvaldo Barrera Date: Tue, 19 May 2026 11:44:39 +0200 Subject: [PATCH 16/16] arm64: dts: rockchip: Fix vcc_sdio regulator max voltage on Pinebook Pro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The vcc_sdio regulator supports 1.8V to 3.4V output range according to its datasheet. The current DT incorrectly limits the max voltage to 3.0V. This limit causes issues issues downstream with u-boot, which refuses to apply the out-of range value, and falls back to the minimum in that range: 1.8V. This is insufficient to power the SD card, so driver initialisation fails and booting from it does not work. Set regulator-max-microvolt to 3400000 µV to match hardware capability. This matches the rk3399-orangepi for the same regulator. Signed-off-by: Hugo Osvaldo Barrera Reviewed-by: Dang Huynh Link: https://patch.msgid.link/20260519094439.7918-1-hugo@whynothugo.nl Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts index b5c05928142c..f21fcdc1b49a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts @@ -526,7 +526,7 @@ vcc_sdio: LDO_REG4 { regulator-always-on; regulator-boot-on; regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; regulator-state-mem { regulator-on-in-suspend;