From a31bbe5ca2f8265f9c7dbc78f1787b88a1ad1775 Mon Sep 17 00:00:00 2001 From: "Jan Petrous (OSS)" Date: Fri, 13 Mar 2026 08:13:32 +0100 Subject: [PATCH 1/3] net: stmmac: platform: read channels irq Read IRQ resources for all rx/tx channels, to allow Multi-IRQ mode for platform glue drivers. Reviewed-by: Matthias Brugger Signed-off-by: Jan Petrous (OSS) Reviewed-by: Russell King (Oracle) Link: https://patch.msgid.link/20260313-dwmac_multi_irq-v12-1-b5c9d0aa13d6@oss.nxp.com Signed-off-by: Jakub Kicinski --- .../ethernet/stmicro/stmmac/stmmac_platform.c | 57 ++++++++++++++++++- 1 file changed, 56 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c index 3b514a702612..59aac0afc609 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c @@ -695,9 +695,47 @@ struct clk *stmmac_pltfr_find_clk(struct plat_stmmacenet_data *plat_dat, } EXPORT_SYMBOL_GPL(stmmac_pltfr_find_clk); +/** + * stmmac_pltfr_get_irq_array - Read per-channel IRQs from platform device + * @pdev: platform device + * @fmt: IRQ name format string (e.g., "tx-queue-%d") + * @irqs: array to store IRQ numbers + * @num: maximum number of IRQs to read + * + * Return: 0 on success, -EPROBE_DEFER if IRQ is deferred, -EINVAL on error. + * Missing IRQs are set to 0 and iteration stops at first missing IRQ. + */ +static int stmmac_pltfr_get_irq_array(struct platform_device *pdev, + const char *fmt, int *irqs, size_t num) +{ + char name[16]; + int i; + + for (i = 0; i < num; i++) { + if (snprintf(name, sizeof(name), fmt, i) >= sizeof(name)) + return -EINVAL; + + irqs[i] = platform_get_irq_byname_optional(pdev, name); + if (irqs[i] == -EPROBE_DEFER) + return -EPROBE_DEFER; + + if (irqs[i] <= 0) { + dev_dbg(&pdev->dev, "IRQ %s not found\n", name); + + /* Stop silently on first unset irq */ + irqs[i] = 0; + break; + } + } + + return 0; +} + int stmmac_get_platform_resources(struct platform_device *pdev, struct stmmac_resources *stmmac_res) { + int ret; + memset(stmmac_res, 0, sizeof(*stmmac_res)); /* Get IRQ information early to have an ability to ask for deferred @@ -733,7 +771,24 @@ int stmmac_get_platform_resources(struct platform_device *pdev, stmmac_res->addr = devm_platform_ioremap_resource(pdev, 0); - return PTR_ERR_OR_ZERO(stmmac_res->addr); + if (IS_ERR(stmmac_res->addr)) + return PTR_ERR(stmmac_res->addr); + + /* TX channels irq */ + ret = stmmac_pltfr_get_irq_array(pdev, "tx-queue-%d", + stmmac_res->tx_irq, + MTL_MAX_TX_QUEUES); + if (ret) + return ret; + + /* RX channels irq */ + ret = stmmac_pltfr_get_irq_array(pdev, "rx-queue-%d", + stmmac_res->rx_irq, + MTL_MAX_RX_QUEUES); + if (ret) + return ret; + + return 0; } EXPORT_SYMBOL_GPL(stmmac_get_platform_resources); From cc7a3435dfadb7469082c6b09018fb2b9cbdeda1 Mon Sep 17 00:00:00 2001 From: "Jan Petrous (OSS)" Date: Fri, 13 Mar 2026 08:13:34 +0100 Subject: [PATCH 2/3] dt-bindings: net: nxp,s32-dwmac: Declare per-queue interrupts The DWMAC IP on NXP S32G/R SoCs has connected queue-based IRQ lines, set them to allow using Multi-IRQ mode. Reviewed-by: Matthias Brugger Acked-by: Conor Dooley Signed-off-by: Jan Petrous (OSS) Link: https://patch.msgid.link/20260313-dwmac_multi_irq-v12-3-b5c9d0aa13d6@oss.nxp.com Signed-off-by: Jakub Kicinski --- .../bindings/net/nxp,s32-dwmac.yaml | 47 +++++++++++++++++-- 1 file changed, 42 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml index 1b2934f3c87c..753a04941659 100644 --- a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -# Copyright 2021-2024 NXP +# Copyright 2021-2026 NXP %YAML 1.2 --- $id: http://devicetree.org/schemas/net/nxp,s32-dwmac.yaml# @@ -16,6 +16,8 @@ description: the SoC S32R45 has two instances. The devices can use RGMII/RMII/MII interface over Pinctrl device or the output can be routed to the embedded SerDes for SGMII connectivity. + The DWMAC instances have connected all RX/TX queues interrupts, + enabling load balancing of data traffic across all CPU cores. properties: compatible: @@ -45,10 +47,25 @@ properties: FlexTimer Modules connect to GMAC_0. interrupts: - maxItems: 1 + minItems: 1 + maxItems: 11 interrupt-names: - const: macirq + oneOf: + - items: + - const: macirq + - items: + - const: macirq + - const: tx-queue-0 + - const: rx-queue-0 + - const: tx-queue-1 + - const: rx-queue-1 + - const: tx-queue-2 + - const: rx-queue-2 + - const: tx-queue-3 + - const: rx-queue-3 + - const: tx-queue-4 + - const: rx-queue-4 clocks: items: @@ -88,8 +105,28 @@ examples: <0x0 0x4007c004 0x0 0x4>; /* GMAC_0_CTRL_STS */ nxp,phy-sel = <&gpr 0x4>; interrupt-parent = <&gic>; - interrupts = ; - interrupt-names = "macirq"; + interrupts = , + /* CHN 0: tx, rx */ + , + , + /* CHN 1: tx, rx */ + , + , + /* CHN 2: tx, rx */ + , + , + /* CHN 3: tx, rx */ + , + , + /* CHN 4: tx, rx */ + , + ; + interrupt-names = "macirq", + "tx-queue-0", "rx-queue-0", + "tx-queue-1", "rx-queue-1", + "tx-queue-2", "rx-queue-2", + "tx-queue-3", "rx-queue-3", + "tx-queue-4", "rx-queue-4"; snps,mtl-rx-config = <&mtl_rx_setup>; snps,mtl-tx-config = <&mtl_tx_setup>; clocks = <&clks 24>, <&clks 17>, <&clks 16>, <&clks 15>; From 66ccb4f1d20551969e4aff9128f239c195b3e543 Mon Sep 17 00:00:00 2001 From: "Jan Petrous (OSS)" Date: Fri, 13 Mar 2026 08:13:35 +0100 Subject: [PATCH 3/3] stmmac: s32: enable support for Multi-IRQ mode Based on previous changes in platform driver, the vendor glue driver can enable Multi-IRQ mode, if needed. To get enabled Multi-IRQ mode for dwmac-s32, the driver checks: 1) property of 'snps,mtl-xx-config' subnode defines 'snps,xx-queues-to-use' bigger then one, ie: ethernet@4033c000 { compatible = "nxp,s32g2-dwmac"; ... snps,mtl-rx-config = <&mtl_rx_setup>; ... mtl_rx_setup: rx-queues-config { snps,rx-queues-to-use = <2>; }; 2) queue based IRQs are set, ie: ethernet@4033c000 { compatible = "nxp,s32g2-dwmac"; ... interrupts = , /* CHN 0: tx, rx */ , , /* CHN 1: tx, rx */ , ; interrupt-names = "macirq", "tx-queue-0", "rx-queue-0", "tx-queue-1", "rx-queue-1"; If those prerequisites are met, the driver switches to Multi-IRQ mode, using per-queue IRQs for rx/tx data pathr: [ 1.387045] s32-dwmac 4033c000.ethernet: Multi-IRQ mode (per queue IRQs) selected Now the driver owns all queues IRQs: root@s32g399aevb3:~# grep eth /proc/interrupts 29: 0 0 0 0 0 0 0 0 GICv3 89 Level eth0:mac 30: 0 0 0 0 0 0 0 0 GICv3 91 Level eth0:rx-0 31: 0 0 0 0 0 0 0 0 GICv3 93 Level eth0:rx-1 32: 0 0 0 0 0 0 0 0 GICv3 95 Level eth0:rx-2 33: 0 0 0 0 0 0 0 0 GICv3 97 Level eth0:rx-3 34: 0 0 0 0 0 0 0 0 GICv3 99 Level eth0:rx-4 35: 0 0 0 0 0 0 0 0 GICv3 90 Level eth0:tx-0 36: 0 0 0 0 0 0 0 0 GICv3 92 Level eth0:tx-1 37: 0 0 0 0 0 0 0 0 GICv3 94 Level eth0:tx-2 38: 0 0 0 0 0 0 0 0 GICv3 96 Level eth0:tx-3 39: 0 0 0 0 0 0 0 0 GICv3 98 Level eth0:tx-4 Otherwise, if one of the prerequisite don't met, the driver continue with MAC IRQ mode: [ 1.387045] s32-dwmac 4033c000.ethernet: MAC IRQ mode selected And only MAC IRQ will be attached: root@s32g399aevb3:~# grep eth /proc/interrupts 29: 0 0 0 0 0 0 0 0 GICv3 89 Level eth0:mac What represents the original MAC IRQ mode and is fully backward compatible. Reviewed-by: Matthias Brugger Signed-off-by: Jan Petrous (OSS) Reviewed-by: Russell King (Oracle) Link: https://patch.msgid.link/20260313-dwmac_multi_irq-v12-4-b5c9d0aa13d6@oss.nxp.com Signed-off-by: Jakub Kicinski --- .../net/ethernet/stmicro/stmmac/dwmac-s32.c | 36 ++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c index 48fceadc55b1..024d8e10e918 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c @@ -2,7 +2,7 @@ /* * NXP S32G/R GMAC glue layer * - * Copyright 2019-2024 NXP + * Copyright 2019-2026 NXP * */ @@ -110,6 +110,37 @@ static void s32_gmac_exit(struct device *dev, void *priv) clk_disable_unprepare(gmac->rx_clk); } +static void s32_gmac_setup_multi_irq(struct device *dev, + struct plat_stmmacenet_data *plat, + struct stmmac_resources *res) +{ + int i; + + /* RX IRQs */ + for (i = 0; i < plat->rx_queues_to_use; i++) { + if (res->rx_irq[i] <= 0) { + dev_dbg(dev, "Missing RX queue %d interrupt\n", i); + goto mac_irq_mode; + } + } + + /* TX IRQs */ + for (i = 0; i < plat->tx_queues_to_use; i++) { + if (res->tx_irq[i] <= 0) { + dev_dbg(dev, "Missing TX queue %d interrupt\n", i); + goto mac_irq_mode; + } + } + + plat->flags |= STMMAC_FLAG_MULTI_MSI_EN; + dev_info(dev, "Multi-IRQ mode (per queue IRQs) selected\n"); + return; + +mac_irq_mode: + plat->flags &= ~STMMAC_FLAG_MULTI_MSI_EN; + dev_info(dev, "MAC IRQ mode selected\n"); +} + static int s32_dwmac_probe(struct platform_device *pdev) { struct plat_stmmacenet_data *plat; @@ -165,6 +196,9 @@ static int s32_dwmac_probe(struct platform_device *pdev) plat->core_type = DWMAC_CORE_GMAC4; plat->pmt = true; plat->flags |= STMMAC_FLAG_SPH_DISABLE; + + s32_gmac_setup_multi_irq(dev, plat, &res); + plat->rx_fifo_size = 20480; plat->tx_fifo_size = 20480;