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arm64: dts: apple: Add initial t6020/t6021/t6022 DTs
These SoCs are found in Apple devices with M2 Pro (t6020), M2 Max (t6021) and M2 Ultra (t6022) and follow the pattern of their M1 counterparts. t6020 is a cut-down version of t6021, so the former just includes the latter and disables the missing bits (This is currently just one PMGR node and all of its domains). t6022 is two connected t6021 dies. The implementation seems to use t6021 with blocks disabled (mostly on the second die). MMIO addresses on the second die have a constant offset. The interrupt controller is multi-die aware. This setup can be represented in the device tree with two top level "soc" nodes. The MMIO offset is applied via "ranges" and devices are included with preproceesor macros to make the node labels unique and to specify the die number for the interrupt definition. Device nodes are distributed over dtsi files based on whether they are present on both dies or just on the first die. The only exception is the NVMe controller which resides on the second die. Its nodes are in a separate file. Signed-off-by: Hector Martin <marcan@marcan.st> Reviewed-by: Neal Gompa <neal@gompa.dev> Co-developed-by: Janne Grunau <j@jannau.net> Signed-off-by: Janne Grunau <j@jannau.net> Reviewed-by: Sven Peter <sven@kernel.org> Signed-off-by: Sven Peter <sven@kernel.org>
This commit is contained in:
Hector Martin
Sven Peter
parent
6313115c55
commit
a8f20eb607
22
arch/arm64/boot/dts/apple/t6020.dtsi
Normal file
22
arch/arm64/boot/dts/apple/t6020.dtsi
Normal file
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@ -0,0 +1,22 @@
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// SPDX-License-Identifier: GPL-2.0+ OR MIT
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/*
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* Apple T6020 "M2 Pro" SoC
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*
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* Other names: H14J, "Rhodes Chop"
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*
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* Copyright The Asahi Linux Contributors
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*/
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/* This chip is just a cut down version of t6021, so include it and disable the missing parts */
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#include "t6021.dtsi"
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/ {
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compatible = "apple,t6020", "apple,arm-platform";
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};
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/delete-node/ &pmgr_south;
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&gpu {
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compatible = "apple,agx-g14s";
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};
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69
arch/arm64/boot/dts/apple/t6021.dtsi
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69
arch/arm64/boot/dts/apple/t6021.dtsi
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@ -0,0 +1,69 @@
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// SPDX-License-Identifier: GPL-2.0+ OR MIT
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/*
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* Apple T6021 "M2 Max" SoC
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*
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* Other names: H14J, "Rhodes"
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*
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* Copyright The Asahi Linux Contributors
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/apple-aic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/pinctrl/apple.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/spmi/spmi.h>
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#include "multi-die-cpp.h"
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#include "t602x-common.dtsi"
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/ {
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compatible = "apple,t6021", "apple,arm-platform";
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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nonposted-mmio;
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// filled via templated includes at the end of the file
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};
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};
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#define DIE
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#define DIE_NO 0
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&{/soc} {
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#include "t602x-die0.dtsi"
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#include "t602x-dieX.dtsi"
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#include "t602x-nvme.dtsi"
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};
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#include "t602x-gpio-pins.dtsi"
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#include "t602x-pmgr.dtsi"
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#undef DIE
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#undef DIE_NO
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&aic {
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affinities {
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e-core-pmu-affinity {
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apple,fiq-index = <AIC_CPU_PMU_E>;
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cpus = <&cpu_e00 &cpu_e01 &cpu_e02 &cpu_e03>;
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};
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p-core-pmu-affinity {
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apple,fiq-index = <AIC_CPU_PMU_P>;
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cpus = <&cpu_p00 &cpu_p01 &cpu_p02 &cpu_p03
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&cpu_p10 &cpu_p11 &cpu_p12 &cpu_p13>;
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};
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};
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};
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&gpu {
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compatible = "apple,agx-g14c", "apple,agx-g14s";
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};
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349
arch/arm64/boot/dts/apple/t6022.dtsi
Normal file
349
arch/arm64/boot/dts/apple/t6022.dtsi
Normal file
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@ -0,0 +1,349 @@
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// SPDX-License-Identifier: GPL-2.0+ OR MIT
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/*
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* Apple T6022 "M2 Ultra" SoC
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*
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* Other names: H14J, "Rhodes 2C"
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*
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* Copyright The Asahi Linux Contributors
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/apple-aic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/pinctrl/apple.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/spmi/spmi.h>
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#include "multi-die-cpp.h"
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#include "t602x-common.dtsi"
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/ {
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compatible = "apple,t6022", "apple,arm-platform";
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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cpu-map {
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cluster3 {
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core0 {
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cpu = <&cpu_e10>;
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};
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core1 {
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cpu = <&cpu_e11>;
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};
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core2 {
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cpu = <&cpu_e12>;
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};
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core3 {
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cpu = <&cpu_e13>;
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};
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};
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cluster4 {
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core0 {
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cpu = <&cpu_p20>;
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};
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core1 {
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cpu = <&cpu_p21>;
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};
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core2 {
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cpu = <&cpu_p22>;
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};
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core3 {
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cpu = <&cpu_p23>;
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};
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};
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cluster5 {
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core0 {
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cpu = <&cpu_p30>;
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};
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core1 {
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cpu = <&cpu_p31>;
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};
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core2 {
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cpu = <&cpu_p32>;
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};
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core3 {
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cpu = <&cpu_p33>;
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};
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};
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};
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cpu_e10: cpu@800 {
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compatible = "apple,blizzard";
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device_type = "cpu";
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reg = <0x0 0x800>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* to be filled by loader */
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next-level-cache = <&l2_cache_3>;
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i-cache-size = <0x20000>;
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d-cache-size = <0x10000>;
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operating-points-v2 = <&blizzard_opp>;
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capacity-dmips-mhz = <756>;
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performance-domains = <&cpufreq_e_die1>;
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};
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cpu_e11: cpu@801 {
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compatible = "apple,blizzard";
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device_type = "cpu";
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reg = <0x0 0x801>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* to be filled by loader */
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next-level-cache = <&l2_cache_3>;
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i-cache-size = <0x20000>;
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d-cache-size = <0x10000>;
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operating-points-v2 = <&blizzard_opp>;
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capacity-dmips-mhz = <756>;
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performance-domains = <&cpufreq_e_die1>;
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};
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cpu_e12: cpu@802 {
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compatible = "apple,blizzard";
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device_type = "cpu";
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reg = <0x0 0x802>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* to be filled by loader */
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next-level-cache = <&l2_cache_3>;
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i-cache-size = <0x20000>;
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d-cache-size = <0x10000>;
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operating-points-v2 = <&blizzard_opp>;
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capacity-dmips-mhz = <756>;
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performance-domains = <&cpufreq_e_die1>;
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};
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cpu_e13: cpu@803 {
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compatible = "apple,blizzard";
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device_type = "cpu";
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reg = <0x0 0x803>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* to be filled by loader */
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next-level-cache = <&l2_cache_3>;
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i-cache-size = <0x20000>;
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d-cache-size = <0x10000>;
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operating-points-v2 = <&blizzard_opp>;
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capacity-dmips-mhz = <756>;
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performance-domains = <&cpufreq_e_die1>;
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};
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cpu_p20: cpu@10900 {
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compatible = "apple,avalanche";
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device_type = "cpu";
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reg = <0x0 0x10900>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* To be filled by loader */
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next-level-cache = <&l2_cache_4>;
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i-cache-size = <0x30000>;
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d-cache-size = <0x20000>;
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operating-points-v2 = <&avalanche_opp>;
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capacity-dmips-mhz = <1024>;
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performance-domains = <&cpufreq_p0_die1>;
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};
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cpu_p21: cpu@10901 {
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compatible = "apple,avalanche";
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device_type = "cpu";
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reg = <0x0 0x10901>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* To be filled by loader */
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next-level-cache = <&l2_cache_4>;
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i-cache-size = <0x30000>;
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d-cache-size = <0x20000>;
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operating-points-v2 = <&avalanche_opp>;
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capacity-dmips-mhz = <1024>;
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performance-domains = <&cpufreq_p0_die1>;
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};
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cpu_p22: cpu@10902 {
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compatible = "apple,avalanche";
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device_type = "cpu";
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reg = <0x0 0x10902>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* To be filled by loader */
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next-level-cache = <&l2_cache_4>;
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i-cache-size = <0x30000>;
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d-cache-size = <0x20000>;
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operating-points-v2 = <&avalanche_opp>;
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capacity-dmips-mhz = <1024>;
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performance-domains = <&cpufreq_p0_die1>;
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};
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cpu_p23: cpu@10903 {
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compatible = "apple,avalanche";
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device_type = "cpu";
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reg = <0x0 0x10903>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* To be filled by loader */
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next-level-cache = <&l2_cache_4>;
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i-cache-size = <0x30000>;
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d-cache-size = <0x20000>;
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operating-points-v2 = <&avalanche_opp>;
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capacity-dmips-mhz = <1024>;
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performance-domains = <&cpufreq_p0_die1>;
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};
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cpu_p30: cpu@10a00 {
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compatible = "apple,avalanche";
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device_type = "cpu";
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reg = <0x0 0x10a00>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* To be filled by loader */
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next-level-cache = <&l2_cache_5>;
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i-cache-size = <0x30000>;
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d-cache-size = <0x20000>;
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operating-points-v2 = <&avalanche_opp>;
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capacity-dmips-mhz = <1024>;
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performance-domains = <&cpufreq_p1_die1>;
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};
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cpu_p31: cpu@10a01 {
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compatible = "apple,avalanche";
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device_type = "cpu";
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reg = <0x0 0x10a01>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* To be filled by loader */
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next-level-cache = <&l2_cache_5>;
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i-cache-size = <0x30000>;
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d-cache-size = <0x20000>;
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operating-points-v2 = <&avalanche_opp>;
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capacity-dmips-mhz = <1024>;
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performance-domains = <&cpufreq_p1_die1>;
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};
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cpu_p32: cpu@10a02 {
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compatible = "apple,avalanche";
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device_type = "cpu";
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reg = <0x0 0x10a02>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* To be filled by loader */
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next-level-cache = <&l2_cache_5>;
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i-cache-size = <0x30000>;
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d-cache-size = <0x20000>;
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operating-points-v2 = <&avalanche_opp>;
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capacity-dmips-mhz = <1024>;
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performance-domains = <&cpufreq_p1_die1>;
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};
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cpu_p33: cpu@10a03 {
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compatible = "apple,avalanche";
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device_type = "cpu";
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reg = <0x0 0x10a03>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* To be filled by loader */
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next-level-cache = <&l2_cache_5>;
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i-cache-size = <0x30000>;
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d-cache-size = <0x20000>;
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operating-points-v2 = <&avalanche_opp>;
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capacity-dmips-mhz = <1024>;
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performance-domains = <&cpufreq_p1_die1>;
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};
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l2_cache_3: l2-cache-3 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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cache-size = <0x400000>;
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};
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l2_cache_4: l2-cache-4 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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cache-size = <0x1000000>;
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};
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l2_cache_5: l2-cache-5 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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cache-size = <0x1000000>;
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};
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};
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die0: soc@200000000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x02 0x00000000 0x02 0x00000000 0x4 0x00000000>,
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<0x05 0x80000000 0x05 0x80000000 0x1 0x80000000>,
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<0x07 0x00000000 0x07 0x00000000 0xf 0x80000000>,
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<0x16 0x80000000 0x16 0x80000000 0x5 0x80000000>;
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nonposted-mmio;
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/* Required to get >32-bit DMA via DARTs */
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dma-ranges = <0 0 0 0 0xffffffff 0xffffc000>;
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// filled via templated includes at the end of the file
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};
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die1: soc@2200000000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x02 0x00000000 0x22 0x00000000 0x4 0x00000000>,
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<0x07 0x00000000 0x27 0x00000000 0xf 0x80000000>,
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<0x16 0x80000000 0x36 0x80000000 0x5 0x80000000>;
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nonposted-mmio;
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/* Required to get >32-bit DMA via DARTs */
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dma-ranges = <0 0 0 0 0xffffffff 0xffffc000>;
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// filled via templated includes at the end of the file
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};
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};
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#define DIE
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#define DIE_NO 0
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&die0 {
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#include "t602x-die0.dtsi"
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#include "t602x-dieX.dtsi"
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};
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#include "t602x-pmgr.dtsi"
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#include "t602x-gpio-pins.dtsi"
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#undef DIE
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#undef DIE_NO
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#define DIE _die1
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#define DIE_NO 1
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&die1 {
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#include "t602x-dieX.dtsi"
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#include "t602x-nvme.dtsi"
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};
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#include "t602x-pmgr.dtsi"
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/delete-node/ &ps_pmp_die1;
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#undef DIE
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#undef DIE_NO
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&aic {
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affinities {
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e-core-pmu-affinity {
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apple,fiq-index = <AIC_CPU_PMU_E>;
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cpus = <&cpu_e00 &cpu_e01 &cpu_e02 &cpu_e03
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&cpu_e10 &cpu_e11 &cpu_e12 &cpu_e13>;
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};
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p-core-pmu-affinity {
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apple,fiq-index = <AIC_CPU_PMU_P>;
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cpus = <&cpu_p00 &cpu_p01 &cpu_p02 &cpu_p03
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&cpu_p10 &cpu_p11 &cpu_p12 &cpu_p13
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&cpu_p20 &cpu_p21 &cpu_p22 &cpu_p23
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&cpu_p30 &cpu_p31 &cpu_p32 &cpu_p33>;
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};
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};
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};
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&ps_gfx {
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// On t6022, the die0 GPU power domain needs both AFR power domains
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power-domains = <&ps_afr>, <&ps_afr_die1>;
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};
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&gpu {
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compatible = "apple,agx-g14d", "apple,agx-g14s";
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};
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465
arch/arm64/boot/dts/apple/t602x-common.dtsi
Normal file
465
arch/arm64/boot/dts/apple/t602x-common.dtsi
Normal file
|
|
@ -0,0 +1,465 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Nodes common to all T602x family SoCs (M2 Pro/Max/Ultra)
|
||||
*
|
||||
* Other names: H14J, "Rhodes Chop", "Rhodes", "Rhodes 2C"
|
||||
*
|
||||
* Copyright The Asahi Linux Contributors
|
||||
*/
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
gpu = &gpu;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&cpu_e00>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&cpu_e01>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&cpu_e02>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&cpu_e03>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1 {
|
||||
core0 {
|
||||
cpu = <&cpu_p00>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&cpu_p01>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&cpu_p02>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&cpu_p03>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster2 {
|
||||
core0 {
|
||||
cpu = <&cpu_p10>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&cpu_p11>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&cpu_p12>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&cpu_p13>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu_e00: cpu@0 {
|
||||
compatible = "apple,blizzard";
|
||||
device_type = "cpu";
|
||||
reg = <0x0 0x0>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* to be filled by loader */
|
||||
next-level-cache = <&l2_cache_0>;
|
||||
i-cache-size = <0x20000>;
|
||||
d-cache-size = <0x10000>;
|
||||
operating-points-v2 = <&blizzard_opp>;
|
||||
capacity-dmips-mhz = <756>;
|
||||
performance-domains = <&cpufreq_e>;
|
||||
};
|
||||
|
||||
cpu_e01: cpu@1 {
|
||||
compatible = "apple,blizzard";
|
||||
device_type = "cpu";
|
||||
reg = <0x0 0x1>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* to be filled by loader */
|
||||
next-level-cache = <&l2_cache_0>;
|
||||
i-cache-size = <0x20000>;
|
||||
d-cache-size = <0x10000>;
|
||||
operating-points-v2 = <&blizzard_opp>;
|
||||
capacity-dmips-mhz = <756>;
|
||||
performance-domains = <&cpufreq_e>;
|
||||
};
|
||||
|
||||
cpu_e02: cpu@2 {
|
||||
compatible = "apple,blizzard";
|
||||
device_type = "cpu";
|
||||
reg = <0x0 0x2>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* to be filled by loader */
|
||||
next-level-cache = <&l2_cache_0>;
|
||||
i-cache-size = <0x20000>;
|
||||
d-cache-size = <0x10000>;
|
||||
operating-points-v2 = <&blizzard_opp>;
|
||||
capacity-dmips-mhz = <756>;
|
||||
performance-domains = <&cpufreq_e>;
|
||||
};
|
||||
|
||||
cpu_e03: cpu@3 {
|
||||
compatible = "apple,blizzard";
|
||||
device_type = "cpu";
|
||||
reg = <0x0 0x3>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* to be filled by loader */
|
||||
next-level-cache = <&l2_cache_0>;
|
||||
i-cache-size = <0x20000>;
|
||||
d-cache-size = <0x10000>;
|
||||
operating-points-v2 = <&blizzard_opp>;
|
||||
capacity-dmips-mhz = <756>;
|
||||
performance-domains = <&cpufreq_e>;
|
||||
};
|
||||
|
||||
cpu_p00: cpu@10100 {
|
||||
compatible = "apple,avalanche";
|
||||
device_type = "cpu";
|
||||
reg = <0x0 0x10100>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||||
next-level-cache = <&l2_cache_1>;
|
||||
i-cache-size = <0x30000>;
|
||||
d-cache-size = <0x20000>;
|
||||
operating-points-v2 = <&avalanche_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
performance-domains = <&cpufreq_p0>;
|
||||
};
|
||||
|
||||
cpu_p01: cpu@10101 {
|
||||
compatible = "apple,avalanche";
|
||||
device_type = "cpu";
|
||||
reg = <0x0 0x10101>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||||
next-level-cache = <&l2_cache_1>;
|
||||
i-cache-size = <0x30000>;
|
||||
d-cache-size = <0x20000>;
|
||||
operating-points-v2 = <&avalanche_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
performance-domains = <&cpufreq_p0>;
|
||||
};
|
||||
|
||||
cpu_p02: cpu@10102 {
|
||||
compatible = "apple,avalanche";
|
||||
device_type = "cpu";
|
||||
reg = <0x0 0x10102>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||||
next-level-cache = <&l2_cache_1>;
|
||||
i-cache-size = <0x30000>;
|
||||
d-cache-size = <0x20000>;
|
||||
operating-points-v2 = <&avalanche_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
performance-domains = <&cpufreq_p0>;
|
||||
};
|
||||
|
||||
cpu_p03: cpu@10103 {
|
||||
compatible = "apple,avalanche";
|
||||
device_type = "cpu";
|
||||
reg = <0x0 0x10103>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||||
next-level-cache = <&l2_cache_1>;
|
||||
i-cache-size = <0x30000>;
|
||||
d-cache-size = <0x20000>;
|
||||
operating-points-v2 = <&avalanche_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
performance-domains = <&cpufreq_p0>;
|
||||
};
|
||||
|
||||
cpu_p10: cpu@10200 {
|
||||
compatible = "apple,avalanche";
|
||||
device_type = "cpu";
|
||||
reg = <0x0 0x10200>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||||
next-level-cache = <&l2_cache_2>;
|
||||
i-cache-size = <0x30000>;
|
||||
d-cache-size = <0x20000>;
|
||||
operating-points-v2 = <&avalanche_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
performance-domains = <&cpufreq_p1>;
|
||||
};
|
||||
|
||||
cpu_p11: cpu@10201 {
|
||||
compatible = "apple,avalanche";
|
||||
device_type = "cpu";
|
||||
reg = <0x0 0x10201>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||||
next-level-cache = <&l2_cache_2>;
|
||||
i-cache-size = <0x30000>;
|
||||
d-cache-size = <0x20000>;
|
||||
operating-points-v2 = <&avalanche_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
performance-domains = <&cpufreq_p1>;
|
||||
};
|
||||
|
||||
cpu_p12: cpu@10202 {
|
||||
compatible = "apple,avalanche";
|
||||
device_type = "cpu";
|
||||
reg = <0x0 0x10202>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||||
next-level-cache = <&l2_cache_2>;
|
||||
i-cache-size = <0x30000>;
|
||||
d-cache-size = <0x20000>;
|
||||
operating-points-v2 = <&avalanche_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
performance-domains = <&cpufreq_p1>;
|
||||
};
|
||||
|
||||
cpu_p13: cpu@10203 {
|
||||
compatible = "apple,avalanche";
|
||||
device_type = "cpu";
|
||||
reg = <0x0 0x10203>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||||
next-level-cache = <&l2_cache_2>;
|
||||
i-cache-size = <0x30000>;
|
||||
d-cache-size = <0x20000>;
|
||||
operating-points-v2 = <&avalanche_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
performance-domains = <&cpufreq_p1>;
|
||||
};
|
||||
|
||||
l2_cache_0: l2-cache-0 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
cache-size = <0x400000>;
|
||||
};
|
||||
|
||||
l2_cache_1: l2-cache-1 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
cache-size = <0x1000000>;
|
||||
};
|
||||
|
||||
l2_cache_2: l2-cache-2 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
cache-size = <0x1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
blizzard_opp: opp-table-0 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
/* pstate #1 is a dummy clone of #2 */
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <912000000>;
|
||||
opp-level = <2>;
|
||||
clock-latency-ns = <7700>;
|
||||
};
|
||||
opp03 {
|
||||
opp-hz = /bits/ 64 <1284000000>;
|
||||
opp-level = <3>;
|
||||
clock-latency-ns = <25000>;
|
||||
};
|
||||
opp04 {
|
||||
opp-hz = /bits/ 64 <1752000000>;
|
||||
opp-level = <4>;
|
||||
clock-latency-ns = <33000>;
|
||||
};
|
||||
opp05 {
|
||||
opp-hz = /bits/ 64 <2004000000>;
|
||||
opp-level = <5>;
|
||||
clock-latency-ns = <38000>;
|
||||
};
|
||||
opp06 {
|
||||
opp-hz = /bits/ 64 <2256000000>;
|
||||
opp-level = <6>;
|
||||
clock-latency-ns = <44000>;
|
||||
};
|
||||
opp07 {
|
||||
opp-hz = /bits/ 64 <2424000000>;
|
||||
opp-level = <7>;
|
||||
clock-latency-ns = <48000>;
|
||||
};
|
||||
};
|
||||
|
||||
avalanche_opp: opp-table-1 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <702000000>;
|
||||
opp-level = <1>;
|
||||
clock-latency-ns = <7400>;
|
||||
};
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <948000000>;
|
||||
opp-level = <2>;
|
||||
clock-latency-ns = <18000>;
|
||||
};
|
||||
opp03 {
|
||||
opp-hz = /bits/ 64 <1188000000>;
|
||||
opp-level = <3>;
|
||||
clock-latency-ns = <21000>;
|
||||
};
|
||||
opp04 {
|
||||
opp-hz = /bits/ 64 <1452000000>;
|
||||
opp-level = <4>;
|
||||
clock-latency-ns = <24000>;
|
||||
};
|
||||
opp05 {
|
||||
opp-hz = /bits/ 64 <1704000000>;
|
||||
opp-level = <5>;
|
||||
clock-latency-ns = <28000>;
|
||||
};
|
||||
opp06 {
|
||||
opp-hz = /bits/ 64 <1968000000>;
|
||||
opp-level = <6>;
|
||||
clock-latency-ns = <31000>;
|
||||
};
|
||||
opp07 {
|
||||
opp-hz = /bits/ 64 <2208000000>;
|
||||
opp-level = <7>;
|
||||
clock-latency-ns = <33000>;
|
||||
};
|
||||
opp08 {
|
||||
opp-hz = /bits/ 64 <2400000000>;
|
||||
opp-level = <8>;
|
||||
clock-latency-ns = <45000>;
|
||||
};
|
||||
opp09 {
|
||||
opp-hz = /bits/ 64 <2568000000>;
|
||||
opp-level = <9>;
|
||||
clock-latency-ns = <47000>;
|
||||
};
|
||||
opp10 {
|
||||
opp-hz = /bits/ 64 <2724000000>;
|
||||
opp-level = <10>;
|
||||
clock-latency-ns = <50000>;
|
||||
};
|
||||
opp11 {
|
||||
opp-hz = /bits/ 64 <2868000000>;
|
||||
opp-level = <11>;
|
||||
clock-latency-ns = <52000>;
|
||||
};
|
||||
opp12 {
|
||||
opp-hz = /bits/ 64 <3000000000>;
|
||||
opp-level = <12>;
|
||||
clock-latency-ns = <57000>;
|
||||
};
|
||||
opp13 {
|
||||
opp-hz = /bits/ 64 <3132000000>;
|
||||
opp-level = <13>;
|
||||
clock-latency-ns = <60000>;
|
||||
};
|
||||
opp14 {
|
||||
opp-hz = /bits/ 64 <3264000000>;
|
||||
opp-level = <14>;
|
||||
clock-latency-ns = <64000>;
|
||||
};
|
||||
opp15 {
|
||||
opp-hz = /bits/ 64 <3360000000>;
|
||||
opp-level = <15>;
|
||||
clock-latency-ns = <64000>;
|
||||
turbo-mode;
|
||||
};
|
||||
opp16 {
|
||||
opp-hz = /bits/ 64 <3408000000>;
|
||||
opp-level = <16>;
|
||||
clock-latency-ns = <64000>;
|
||||
turbo-mode;
|
||||
};
|
||||
opp17 {
|
||||
opp-hz = /bits/ 64 <3504000000>;
|
||||
opp-level = <17>;
|
||||
clock-latency-ns = <64000>;
|
||||
turbo-mode;
|
||||
};
|
||||
};
|
||||
|
||||
pmu-e {
|
||||
compatible = "apple,blizzard-pmu";
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_FIQ 0 AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pmu-p {
|
||||
compatible = "apple,avalanche-pmu";
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_FIQ 0 AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupt-parent = <&aic>;
|
||||
interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt";
|
||||
interrupts = <AIC_FIQ 0 AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_FIQ 0 AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_FIQ 0 AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_FIQ 0 AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
clkref: clock-ref {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "clkref";
|
||||
};
|
||||
|
||||
clk_200m: clock-200m {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <200000000>;
|
||||
clock-output-names = "clk_200m";
|
||||
};
|
||||
|
||||
/*
|
||||
* This is a fabulated representation of the input clock
|
||||
* to NCO since we don't know the true clock tree.
|
||||
*/
|
||||
nco_clkref: clock-ref-nco {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "nco_ref";
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
gpu_globals: globals {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpu_hw_cal_a: hw-cal-a {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpu_hw_cal_b: hw-cal-b {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uat_handoff: uat-handoff {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uat_pagetables: uat-pagetables {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uat_ttbs: uat-ttbs {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
575
arch/arm64/boot/dts/apple/t602x-die0.dtsi
Normal file
575
arch/arm64/boot/dts/apple/t602x-die0.dtsi
Normal file
|
|
@ -0,0 +1,575 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Devices used on die 0 on the Apple T6022 "M2 Ultra" SoC and present on
|
||||
* Apple T6020 / T6021 "M2 Pro" / "M2 Max".
|
||||
*
|
||||
* Copyright The Asahi Linux Contributors
|
||||
*/
|
||||
|
||||
nco: clock-controller@28e03c000 {
|
||||
compatible = "apple,t6020-nco", "apple,t8103-nco";
|
||||
reg = <0x2 0x8e03c000 0x0 0x14000>;
|
||||
clocks = <&nco_clkref>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
aic: interrupt-controller@28e100000 {
|
||||
compatible = "apple,t6020-aic", "apple,aic2";
|
||||
#interrupt-cells = <4>;
|
||||
interrupt-controller;
|
||||
reg = <0x2 0x8e100000 0x0 0xc000>,
|
||||
<0x2 0x8e10c000 0x0 0x1000>;
|
||||
reg-names = "core", "event";
|
||||
power-domains = <&ps_aic>;
|
||||
};
|
||||
|
||||
nub_spmi0: spmi@29e114000 {
|
||||
compatible = "apple,t6020-spmi", "apple,t8103-spmi";
|
||||
reg = <0x2 0x9e114000 0x0 0x100>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pmic1: pmic@f {
|
||||
compatible = "apple,maverick-pmic", "apple,spmi-nvmem";
|
||||
reg = <0xb SPMI_USID>;
|
||||
|
||||
nvmem-layout {
|
||||
compatible = "fixed-layout";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
pm_setting: pm-setting@1405 {
|
||||
reg = <0x1405 0x1>;
|
||||
};
|
||||
|
||||
rtc_offset: rtc-offset@1411 {
|
||||
reg = <0x1411 0x6>;
|
||||
};
|
||||
|
||||
boot_stage: boot-stage@6001 {
|
||||
reg = <0x6001 0x1>;
|
||||
};
|
||||
|
||||
boot_error_count: boot-error-count@6002,0 {
|
||||
reg = <0x6002 0x1>;
|
||||
bits = <0 4>;
|
||||
};
|
||||
|
||||
panic_count: panic-count@6002,4 {
|
||||
reg = <0x6002 0x1>;
|
||||
bits = <4 4>;
|
||||
};
|
||||
|
||||
boot_error_stage: boot-error-stage@6003 {
|
||||
reg = <0x6003 0x1>;
|
||||
};
|
||||
|
||||
shutdown_flag: shutdown-flag@600f,3 {
|
||||
reg = <0x600f 0x1>;
|
||||
bits = <3 1>;
|
||||
};
|
||||
|
||||
fault_shadow: fault-shadow@867b {
|
||||
reg = <0x867b 0x10>;
|
||||
};
|
||||
|
||||
socd: socd@8b00 {
|
||||
reg = <0x8b00 0x400>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
wdt: watchdog@29e2c4000 {
|
||||
compatible = "apple,t6020-wdt", "apple,t8103-wdt";
|
||||
reg = <0x2 0x9e2c4000 0x0 0x4000>;
|
||||
clocks = <&clkref>;
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_IRQ 0 719 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
smc_mbox: mbox@2a2408000 {
|
||||
compatible = "apple,t6020-asc-mailbox", "apple,asc-mailbox-v4";
|
||||
reg = <0x2 0xa2408000 0x0 0x4000>;
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_IRQ 0 862 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 0 863 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 0 864 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 0 865 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "send-empty", "send-not-empty",
|
||||
"recv-empty", "recv-not-empty";
|
||||
#mbox-cells = <0>;
|
||||
};
|
||||
|
||||
smc: smc@2a2400000 {
|
||||
compatible = "apple,t6020-smc", "apple,t8103-smc";
|
||||
reg = <0x2 0xa2400000 0x0 0x4000>,
|
||||
<0x2 0xa3e00000 0x0 0x100000>;
|
||||
reg-names = "smc", "sram";
|
||||
mboxes = <&smc_mbox>;
|
||||
|
||||
smc_gpio: gpio {
|
||||
compatible = "apple,smc-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
smc_reboot: reboot {
|
||||
compatible = "apple,smc-reboot";
|
||||
nvmem-cells = <&shutdown_flag>, <&boot_stage>,
|
||||
<&boot_error_count>, <&panic_count>;
|
||||
nvmem-cell-names = "shutdown_flag", "boot_stage",
|
||||
"boot_error_count", "panic_count";
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_smc: pinctrl@2a2820000 {
|
||||
compatible = "apple,t6020-pinctrl", "apple,t8103-pinctrl";
|
||||
reg = <0x2 0xa2820000 0x0 0x4000>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pinctrl_smc 0 0 30>;
|
||||
apple,npins = <30>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_IRQ 0 851 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 0 852 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 0 853 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 0 854 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 0 855 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 0 856 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 0 857 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sio_dart: iommu@39b008000 {
|
||||
compatible = "apple,t6020-dart", "apple,t8110-dart";
|
||||
reg = <0x3 0x9b008000 0x0 0x8000>;
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_IRQ 0 1231 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#iommu-cells = <1>;
|
||||
power-domains = <&ps_sio_cpu>;
|
||||
};
|
||||
|
||||
fpwm0: pwm@39b030000 {
|
||||
compatible = "apple,t6020-fpwm", "apple,s5l-fpwm";
|
||||
reg = <0x3 0x9b030000 0x0 0x4000>;
|
||||
power-domains = <&ps_fpwm0>;
|
||||
clocks = <&clkref>;
|
||||
#pwm-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@39b040000 {
|
||||
compatible = "apple,t6020-i2c", "apple,t8103-i2c";
|
||||
reg = <0x3 0x9b040000 0x0 0x4000>;
|
||||
clocks = <&clkref>;
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_IRQ 0 1219 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
pinctrl-names = "default";
|
||||
power-domains = <&ps_i2c0>;
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
};
|
||||
|
||||
i2c1: i2c@39b044000 {
|
||||
compatible = "apple,t6020-i2c", "apple,t8103-i2c";
|
||||
reg = <0x3 0x9b044000 0x0 0x4000>;
|
||||
clocks = <&clkref>;
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_IRQ 0 1220 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
pinctrl-names = "default";
|
||||
power-domains = <&ps_i2c1>;
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@39b048000 {
|
||||
compatible = "apple,t6020-i2c", "apple,t8103-i2c";
|
||||
reg = <0x3 0x9b048000 0x0 0x4000>;
|
||||
clocks = <&clkref>;
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_IRQ 0 1221 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-0 = <&i2c2_pins>;
|
||||
pinctrl-names = "default";
|
||||
power-domains = <&ps_i2c2>;
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@39b04c000 {
|
||||
compatible = "apple,t6020-i2c", "apple,t8103-i2c";
|
||||
reg = <0x3 0x9b04c000 0x0 0x4000>;
|
||||
clocks = <&clkref>;
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_IRQ 0 1222 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-0 = <&i2c3_pins>;
|
||||
pinctrl-names = "default";
|
||||
power-domains = <&ps_i2c3>;
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@39b050000 {
|
||||
compatible = "apple,t6020-i2c", "apple,t8103-i2c";
|
||||
reg = <0x3 0x9b050000 0x0 0x4000>;
|
||||
clocks = <&clkref>;
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_IRQ 0 1223 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-0 = <&i2c4_pins>;
|
||||
pinctrl-names = "default";
|
||||
power-domains = <&ps_i2c4>;
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c5: i2c@39b054000 {
|
||||
compatible = "apple,t6020-i2c", "apple,t8103-i2c";
|
||||
reg = <0x3 0x9b054000 0x0 0x4000>;
|
||||
clocks = <&clkref>;
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_IRQ 0 1224 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-0 = <&i2c5_pins>;
|
||||
pinctrl-names = "default";
|
||||
power-domains = <&ps_i2c5>;
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c6: i2c@39b054000 {
|
||||
compatible = "apple,t6020-i2c", "apple,t8103-i2c";
|
||||
reg = <0x3 0x9b054000 0x0 0x4000>;
|
||||
clocks = <&clkref>;
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_IRQ 0 1225 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-0 = <&i2c6_pins>;
|
||||
pinctrl-names = "default";
|
||||
power-domains = <&ps_i2c6>;
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c7: i2c@39b054000 {
|
||||
compatible = "apple,t6020-i2c", "apple,t8103-i2c";
|
||||
reg = <0x3 0x9b054000 0x0 0x4000>;
|
||||
clocks = <&clkref>;
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_IRQ 0 1226 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-0 = <&i2c7_pins>;
|
||||
pinctrl-names = "default";
|
||||
power-domains = <&ps_i2c7>;
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c8: i2c@39b054000 {
|
||||
compatible = "apple,t6020-i2c", "apple,t8103-i2c";
|
||||
reg = <0x3 0x9b054000 0x0 0x4000>;
|
||||
clocks = <&clkref>;
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_IRQ 0 1227 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-0 = <&i2c8_pins>;
|
||||
pinctrl-names = "default";
|
||||
power-domains = <&ps_i2c8>;
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@39b104000 {
|
||||
compatible = "apple,t6020-spi", "apple,t8103-spi";
|
||||
reg = <0x3 0x9b104000 0x0 0x4000>;
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_IRQ 0 1206 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clk_200m>;
|
||||
pinctrl-0 = <&spi1_pins>;
|
||||
pinctrl-names = "default";
|
||||
power-domains = <&ps_spi1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi2: spi@39b108000 {
|
||||
compatible = "apple,t6020-spi", "apple,t8103-spi";
|
||||
reg = <0x3 0x9b108000 0x0 0x4000>;
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_IRQ 0 1207 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clkref>;
|
||||
pinctrl-0 = <&spi2_pins>;
|
||||
pinctrl-names = "default";
|
||||
power-domains = <&ps_spi2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi4: spi@39b110000 {
|
||||
compatible = "apple,t6020-spi", "apple,t8103-spi";
|
||||
reg = <0x3 0x9b110000 0x0 0x4000>;
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_IRQ 0 1209 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clkref>;
|
||||
pinctrl-0 = <&spi4_pins>;
|
||||
pinctrl-names = "default";
|
||||
power-domains = <&ps_spi4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial0: serial@39b200000 {
|
||||
compatible = "apple,s5l-uart";
|
||||
reg = <0x3 0x9b200000 0x0 0x4000>;
|
||||
reg-io-width = <4>;
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_IRQ 0 1198 IRQ_TYPE_LEVEL_HIGH>;
|
||||
/*
|
||||
* TODO: figure out the clocking properly, there may
|
||||
* be a third selectable clock.
|
||||
*/
|
||||
clocks = <&clkref>, <&clkref>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
power-domains = <&ps_uart0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
admac: dma-controller@39b400000 {
|
||||
compatible = "apple,t6020-admac", "apple,t8103-admac";
|
||||
reg = <0x3 0x9b400000 0x0 0x34000>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <16>;
|
||||
interrupts-extended = <0>,
|
||||
<&aic AIC_IRQ 0 1218 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0>,
|
||||
<0>;
|
||||
iommus = <&sio_dart 2>;
|
||||
power-domains = <&ps_sio_adma>;
|
||||
resets = <&ps_audio_p>;
|
||||
};
|
||||
|
||||
mca: mca@39b600000 {
|
||||
compatible = "apple,t6020-mca", "apple,t8103-mca";
|
||||
reg = <0x3 0x9b600000 0x0 0x10000>,
|
||||
<0x3 0x9b500000 0x0 0x20000>;
|
||||
clocks = <&nco 0>, <&nco 1>, <&nco 2>, <&nco 3>;
|
||||
dmas = <&admac 0>, <&admac 1>, <&admac 2>, <&admac 3>,
|
||||
<&admac 4>, <&admac 5>, <&admac 6>, <&admac 7>,
|
||||
<&admac 8>, <&admac 9>, <&admac 10>, <&admac 11>,
|
||||
<&admac 12>, <&admac 13>, <&admac 14>, <&admac 15>;
|
||||
dma-names = "tx0a", "rx0a", "tx0b", "rx0b",
|
||||
"tx1a", "rx1a", "tx1b", "rx1b",
|
||||
"tx2a", "rx2a", "tx2b", "rx2b",
|
||||
"tx3a", "rx3a", "tx3b", "rx3b";
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_IRQ 0 1211 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 0 1212 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 0 1213 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 0 1214 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&ps_audio_p>, <&ps_mca0>, <&ps_mca1>,
|
||||
<&ps_mca2>, <&ps_mca3>;
|
||||
resets = <&ps_audio_p>;
|
||||
#sound-dai-cells = <1>;
|
||||
};
|
||||
|
||||
gpu: gpu@406400000 {
|
||||
compatible = "apple,agx-g14s";
|
||||
reg = <0x4 0x6400000 0 0x40000>,
|
||||
<0x4 0x4000000 0 0x1000000>;
|
||||
reg-names = "asc", "sgx";
|
||||
mboxes = <&agx_mbox>;
|
||||
power-domains = <&ps_gfx>;
|
||||
memory-region = <&uat_ttbs>, <&uat_pagetables>, <&uat_handoff>,
|
||||
<&gpu_hw_cal_a>, <&gpu_hw_cal_b>, <&gpu_globals>;
|
||||
memory-region-names = "ttbs", "pagetables", "handoff",
|
||||
"hw-cal-a", "hw-cal-b", "globals";
|
||||
|
||||
apple,firmware-abi = <0 0 0>;
|
||||
};
|
||||
|
||||
agx_mbox: mbox@406408000 {
|
||||
compatible = "apple,t6020-asc-mailbox", "apple,asc-mailbox-v4";
|
||||
reg = <0x4 0x6408000 0x0 0x4000>;
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_IRQ 0 1143 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 0 1144 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 0 1145 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 0 1146 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "send-empty", "send-not-empty",
|
||||
"recv-empty", "recv-not-empty";
|
||||
#mbox-cells = <0>;
|
||||
};
|
||||
|
||||
pcie0: pcie@580000000 {
|
||||
compatible = "apple,t6020-pcie";
|
||||
device_type = "pci";
|
||||
|
||||
reg = <0x5 0x80000000 0x0 0x1000000>, /* config */
|
||||
<0x5 0x91000000 0x0 0x4000>, /* rc */
|
||||
<0x5 0x94008000 0x0 0x4000>, /* port0 */
|
||||
<0x5 0x95008000 0x0 0x4000>, /* port1 */
|
||||
<0x5 0x96008000 0x0 0x4000>, /* port2 */
|
||||
<0x5 0x97008000 0x0 0x4000>, /* port3 */
|
||||
<0x5 0x9e00c000 0x0 0x4000>, /* phy0 */
|
||||
<0x5 0x9e010000 0x0 0x4000>, /* phy1 */
|
||||
<0x5 0x9e014000 0x0 0x4000>, /* phy2 */
|
||||
<0x5 0x9e018000 0x0 0x4000>; /* phy3 */
|
||||
reg-names = "config", "rc",
|
||||
"port0", "port1", "port2", "port3",
|
||||
"phy0", "phy1", "phy2", "phy3";
|
||||
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_IRQ 0 1340 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 0 1344 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 0 1348 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 0 1352 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
msi-controller;
|
||||
msi-parent = <&pcie0>;
|
||||
msi-ranges = <&aic AIC_IRQ 0 1672 IRQ_TYPE_EDGE_RISING 32>;
|
||||
|
||||
iommu-map = <0x100 &pcie0_dart_0 1 1>,
|
||||
<0x200 &pcie0_dart_1 1 1>,
|
||||
<0x300 &pcie0_dart_2 1 1>,
|
||||
<0x400 &pcie0_dart_3 1 1>;
|
||||
iommu-map-mask = <0xff00>;
|
||||
|
||||
bus-range = <0 4>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x43000000 0x5 0xa0000000 0x5 0xa0000000 0x0 0x20000000>,
|
||||
<0x02000000 0x0 0xc0000000 0x5 0xc0000000 0x0 0x40000000>;
|
||||
|
||||
power-domains = <&ps_apcie_gp_sys>;
|
||||
pinctrl-0 = <&pcie_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
port00: pci@0,0 {
|
||||
device_type = "pci";
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
reset-gpios = <&pinctrl_ap 4 GPIO_ACTIVE_LOW>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &port00 0 0 0 0>,
|
||||
<0 0 0 2 &port00 0 0 0 1>,
|
||||
<0 0 0 3 &port00 0 0 0 2>,
|
||||
<0 0 0 4 &port00 0 0 0 3>;
|
||||
};
|
||||
|
||||
port01: pci@1,0 {
|
||||
device_type = "pci";
|
||||
reg = <0x800 0x0 0x0 0x0 0x0>;
|
||||
reset-gpios = <&pinctrl_ap 5 GPIO_ACTIVE_LOW>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &port01 0 0 0 0>,
|
||||
<0 0 0 2 &port01 0 0 0 1>,
|
||||
<0 0 0 3 &port01 0 0 0 2>,
|
||||
<0 0 0 4 &port01 0 0 0 3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
port02: pci@2,0 {
|
||||
device_type = "pci";
|
||||
reg = <0x1000 0x0 0x0 0x0 0x0>;
|
||||
reset-gpios = <&pinctrl_ap 6 GPIO_ACTIVE_LOW>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &port02 0 0 0 0>,
|
||||
<0 0 0 2 &port02 0 0 0 1>,
|
||||
<0 0 0 3 &port02 0 0 0 2>,
|
||||
<0 0 0 4 &port02 0 0 0 3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
port03: pci@3,0 {
|
||||
device_type = "pci";
|
||||
reg = <0x1800 0x0 0x0 0x0 0x0>;
|
||||
reset-gpios = <&pinctrl_ap 7 GPIO_ACTIVE_LOW>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &port03 0 0 0 0>,
|
||||
<0 0 0 2 &port03 0 0 0 1>,
|
||||
<0 0 0 3 &port03 0 0 0 2>,
|
||||
<0 0 0 4 &port03 0 0 0 3>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_dart_0: iommu@594000000 {
|
||||
compatible = "apple,t6020-dart", "apple,t8110-dart";
|
||||
reg = <0x5 0x94000000 0x0 0x4000>;
|
||||
#iommu-cells = <1>;
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_IRQ 0 1341 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&ps_apcie_gp_sys>;
|
||||
};
|
||||
|
||||
pcie0_dart_1: iommu@595000000 {
|
||||
compatible = "apple,t6020-dart", "apple,t8110-dart";
|
||||
reg = <0x5 0x95000000 0x0 0x4000>;
|
||||
#iommu-cells = <1>;
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_IRQ 0 1345 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&ps_apcie_gp_sys>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie0_dart_2: iommu@596000000 {
|
||||
compatible = "apple,t6020-dart", "apple,t8110-dart";
|
||||
reg = <0x5 0x96000000 0x0 0x4000>;
|
||||
#iommu-cells = <1>;
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_IRQ 0 1349 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&ps_apcie_gp_sys>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie0_dart_3: iommu@597000000 {
|
||||
compatible = "apple,t6020-dart", "apple,t8110-dart";
|
||||
reg = <0x5 0x97000000 0x0 0x4000>;
|
||||
#iommu-cells = <1>;
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_IRQ 0 1353 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&ps_apcie_gp_sys>;
|
||||
status = "disabled";
|
||||
};
|
||||
128
arch/arm64/boot/dts/apple/t602x-dieX.dtsi
Normal file
128
arch/arm64/boot/dts/apple/t602x-dieX.dtsi
Normal file
|
|
@ -0,0 +1,128 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Nodes present on both dies of T6022 (M2 Ultra) and present on M2 Pro/Max.
|
||||
*
|
||||
* Copyright The Asahi Linux Contributors
|
||||
*/
|
||||
|
||||
DIE_NODE(cpufreq_e): cpufreq@210e20000 {
|
||||
compatible = "apple,t6020-cluster-cpufreq", "apple,t8112-cluster-cpufreq";
|
||||
reg = <0x2 0x10e20000 0 0x1000>;
|
||||
#performance-domain-cells = <0>;
|
||||
};
|
||||
|
||||
DIE_NODE(cpufreq_p0): cpufreq@211e20000 {
|
||||
compatible = "apple,t6020-cluster-cpufreq", "apple,t8112-cluster-cpufreq";
|
||||
reg = <0x2 0x11e20000 0 0x1000>;
|
||||
#performance-domain-cells = <0>;
|
||||
};
|
||||
|
||||
DIE_NODE(cpufreq_p1): cpufreq@212e20000 {
|
||||
compatible = "apple,t6020-cluster-cpufreq", "apple,t8112-cluster-cpufreq";
|
||||
reg = <0x2 0x12e20000 0 0x1000>;
|
||||
#performance-domain-cells = <0>;
|
||||
};
|
||||
|
||||
DIE_NODE(pmgr): power-management@28e080000 {
|
||||
compatible = "apple,t6020-pmgr", "apple,t8103-pmgr", "syscon", "simple-mfd";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x2 0x8e080000 0 0x8000>;
|
||||
};
|
||||
|
||||
DIE_NODE(pmgr_south): power-management@28e680000 {
|
||||
compatible = "apple,t6020-pmgr", "apple,t8103-pmgr", "syscon", "simple-mfd";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x2 0x8e680000 0 0x8000>;
|
||||
};
|
||||
|
||||
DIE_NODE(pmgr_east): power-management@290280000 {
|
||||
compatible = "apple,t6020-pmgr", "apple,t8103-pmgr", "syscon", "simple-mfd";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x2 0x90280000 0 0xc000>;
|
||||
};
|
||||
|
||||
DIE_NODE(pinctrl_nub): pinctrl@29e1f0000 {
|
||||
compatible = "apple,t6020-pinctrl", "apple,t8103-pinctrl";
|
||||
reg = <0x2 0x9e1f0000 0x0 0x4000>;
|
||||
power-domains = <&DIE_NODE(ps_nub_gpio)>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&DIE_NODE(pinctrl_nub) 0 0 30>;
|
||||
apple,npins = <30>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_IRQ DIE_NO 711 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ DIE_NO 712 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ DIE_NO 713 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ DIE_NO 714 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ DIE_NO 715 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ DIE_NO 716 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ DIE_NO 717 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
DIE_NODE(pmgr_mini): power-management@29e280000 {
|
||||
compatible = "apple,t6020-pmgr", "apple,t8103-pmgr", "syscon", "simple-mfd";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x2 0x9e280000 0 0x4000>;
|
||||
};
|
||||
|
||||
DIE_NODE(pinctrl_aop): pinctrl@2a6820000 {
|
||||
compatible = "apple,t6020-pinctrl", "apple,t8103-pinctrl";
|
||||
reg = <0x2 0xa6820000 0x0 0x4000>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&DIE_NODE(pinctrl_aop) 0 0 72>;
|
||||
apple,npins = <72>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_IRQ DIE_NO 598 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ DIE_NO 599 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ DIE_NO 600 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ DIE_NO 601 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ DIE_NO 602 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ DIE_NO 603 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ DIE_NO 604 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
DIE_NODE(pinctrl_ap): pinctrl@39b028000 {
|
||||
compatible = "apple,t6020-pinctrl", "apple,t8103-pinctrl";
|
||||
reg = <0x3 0x9b028000 0x0 0x4000>;
|
||||
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_IRQ DIE_NO 458 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ DIE_NO 459 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ DIE_NO 460 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ DIE_NO 461 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ DIE_NO 462 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ DIE_NO 463 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ DIE_NO 464 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&clkref>;
|
||||
power-domains = <&DIE_NODE(ps_gpio)>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&DIE_NODE(pinctrl_ap) 0 0 255>;
|
||||
apple,npins = <255>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
DIE_NODE(pmgr_gfx): power-management@404e80000 {
|
||||
compatible = "apple,t6020-pmgr", "apple,t8103-pmgr", "syscon", "simple-mfd";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
reg = <0x4 0x4e80000 0 0x4000>;
|
||||
};
|
||||
81
arch/arm64/boot/dts/apple/t602x-gpio-pins.dtsi
Normal file
81
arch/arm64/boot/dts/apple/t602x-gpio-pins.dtsi
Normal file
|
|
@ -0,0 +1,81 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* GPIO pin mappings for Apple T602x SoCs.
|
||||
*
|
||||
* Copyright The Asahi Linux Contributors
|
||||
*/
|
||||
|
||||
&pinctrl_ap {
|
||||
i2c0_pins: i2c0-pins {
|
||||
pinmux = <APPLE_PINMUX(63, 1)>,
|
||||
<APPLE_PINMUX(64, 1)>;
|
||||
};
|
||||
|
||||
i2c1_pins: i2c1-pins {
|
||||
pinmux = <APPLE_PINMUX(65, 1)>,
|
||||
<APPLE_PINMUX(66, 1)>;
|
||||
};
|
||||
|
||||
i2c2_pins: i2c2-pins {
|
||||
pinmux = <APPLE_PINMUX(67, 1)>,
|
||||
<APPLE_PINMUX(68, 1)>;
|
||||
};
|
||||
|
||||
i2c3_pins: i2c3-pins {
|
||||
pinmux = <APPLE_PINMUX(69, 1)>,
|
||||
<APPLE_PINMUX(70, 1)>;
|
||||
};
|
||||
|
||||
i2c4_pins: i2c4-pins {
|
||||
pinmux = <APPLE_PINMUX(71, 1)>,
|
||||
<APPLE_PINMUX(72, 1)>;
|
||||
};
|
||||
|
||||
i2c5_pins: i2c5-pins {
|
||||
pinmux = <APPLE_PINMUX(73, 1)>,
|
||||
<APPLE_PINMUX(74, 1)>;
|
||||
};
|
||||
|
||||
i2c6_pins: i2c6-pins {
|
||||
pinmux = <APPLE_PINMUX(75, 1)>,
|
||||
<APPLE_PINMUX(76, 1)>;
|
||||
};
|
||||
|
||||
i2c7_pins: i2c7-pins {
|
||||
pinmux = <APPLE_PINMUX(77, 1)>,
|
||||
<APPLE_PINMUX(78, 1)>;
|
||||
};
|
||||
|
||||
i2c8_pins: i2c8-pins {
|
||||
pinmux = <APPLE_PINMUX(79, 1)>,
|
||||
<APPLE_PINMUX(80, 1)>;
|
||||
};
|
||||
|
||||
spi1_pins: spi1-pins {
|
||||
pinmux = <APPLE_PINMUX(155, 1)>, /* SDI */
|
||||
<APPLE_PINMUX(156, 1)>, /* SDO */
|
||||
<APPLE_PINMUX(157, 1)>, /* SCK */
|
||||
<APPLE_PINMUX(158, 1)>; /* CS */
|
||||
};
|
||||
|
||||
spi2_pins: spi2-pins {
|
||||
pinmux = <APPLE_PINMUX(159, 1)>, /* SDI */
|
||||
<APPLE_PINMUX(160, 1)>, /* SDO */
|
||||
<APPLE_PINMUX(161, 1)>, /* SCK */
|
||||
<APPLE_PINMUX(162, 1)>; /* CS */
|
||||
};
|
||||
|
||||
spi4_pins: spi4-pins {
|
||||
pinmux = <APPLE_PINMUX(167, 1)>, /* SDI */
|
||||
<APPLE_PINMUX(168, 1)>, /* SDO */
|
||||
<APPLE_PINMUX(169, 1)>, /* SCK */
|
||||
<APPLE_PINMUX(170, 1)>; /* CS */
|
||||
};
|
||||
|
||||
pcie_pins: pcie-pins {
|
||||
pinmux = <APPLE_PINMUX(0, 1)>,
|
||||
<APPLE_PINMUX(1, 1)>,
|
||||
<APPLE_PINMUX(2, 1)>,
|
||||
<APPLE_PINMUX(3, 1)>;
|
||||
};
|
||||
};
|
||||
42
arch/arm64/boot/dts/apple/t602x-nvme.dtsi
Normal file
42
arch/arm64/boot/dts/apple/t602x-nvme.dtsi
Normal file
|
|
@ -0,0 +1,42 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* NVMe related devices for Apple T602x SoCs.
|
||||
*
|
||||
* Copyright The Asahi Linux Contributors
|
||||
*/
|
||||
|
||||
DIE_NODE(ans_mbox): mbox@347408000 {
|
||||
compatible = "apple,t6020-asc-mailbox", "apple,asc-mailbox-v4";
|
||||
reg = <0x3 0x47408000 0x0 0x4000>;
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_IRQ DIE_NO 1169 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ DIE_NO 1170 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ DIE_NO 1171 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ DIE_NO 1172 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "send-empty", "send-not-empty",
|
||||
"recv-empty", "recv-not-empty";
|
||||
power-domains = <&DIE_NODE(ps_ans2)>;
|
||||
#mbox-cells = <0>;
|
||||
};
|
||||
|
||||
DIE_NODE(sart): sart@34bc50000 {
|
||||
compatible = "apple,t6020-sart", "apple,t6000-sart";
|
||||
reg = <0x3 0x4bc50000 0x0 0x10000>;
|
||||
power-domains = <&DIE_NODE(ps_ans2)>;
|
||||
};
|
||||
|
||||
DIE_NODE(nvme): nvme@34bcc0000 {
|
||||
compatible = "apple,t6020-nvme-ans2", "apple,t8103-nvme-ans2";
|
||||
reg = <0x3 0x4bcc0000 0x0 0x40000>, <0x3 0x47400000 0x0 0x4000>;
|
||||
reg-names = "nvme", "ans";
|
||||
interrupt-parent = <&aic>;
|
||||
/* The NVME interrupt is always routed to die 0 */
|
||||
interrupts = <AIC_IRQ 0 1832 IRQ_TYPE_LEVEL_HIGH>;
|
||||
mboxes = <&DIE_NODE(ans_mbox)>;
|
||||
apple,sart = <&DIE_NODE(sart)>;
|
||||
power-domains = <&DIE_NODE(ps_ans2)>,
|
||||
<&DIE_NODE(ps_apcie_st_sys)>,
|
||||
<&DIE_NODE(ps_apcie_st1_sys)>;
|
||||
power-domain-names = "ans", "apcie0", "apcie1";
|
||||
resets = <&DIE_NODE(ps_ans2)>;
|
||||
};
|
||||
2265
arch/arm64/boot/dts/apple/t602x-pmgr.dtsi
Normal file
2265
arch/arm64/boot/dts/apple/t602x-pmgr.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user