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phy/rockchip: mipi_dphy: Add support for RK1808
The innoslicon GF22FDX MIPI D-PHY integrates a MIPI 1.2 compatible PHY that supports up to 2.5Gbps high speed data transmitter, plus a MIPI low-power low speed transceiver that support data transfer in the bi-directional mode. The IP supports the full specifications described in the D-PHY spec 1.2. The D-PHY is built in with a standard digital interface to talk to any third party host controller. Change-Id: Iad7b9dc8fedaa1a5741830e9c02a593f544c2423 Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
This commit is contained in:
Wyon Bi
Tao Huang
parent
2ba3dad0f8
commit
a8c0f12f4e
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@ -3,6 +3,7 @@ ROCKCHIP MIPI DPHY WITH INNO IP BLOCK
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Required properties:
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- compatible : must be one of:
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"rockchip,px30-mipi-dphy";
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"rockchip,rk1808-mipi-dphy";
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"rockchip,rk3128-mipi-dphy";
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"rockchip,rk3366-mipi-dphy";
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"rockchip,rk3368-mipi-dphy";
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@ -209,9 +209,21 @@ struct mipi_dphy_timing {
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unsigned int wakeup;
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};
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struct inno_mipi_dphy_timing {
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unsigned int max_lane_mbps;
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u8 lpx;
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u8 hs_prepare;
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u8 clk_lane_hs_zero;
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u8 data_lane_hs_zero;
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u8 hs_trail;
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};
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struct inno_video_phy_socdata {
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bool pinmux;
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bool has_h2p_clk;
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bool post_div_enable;
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const struct inno_mipi_dphy_timing *timings;
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unsigned int num_timings;
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};
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struct inno_mipi_dphy {
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@ -247,26 +259,41 @@ enum {
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REGISTER_PART_DATA3_LANE,
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};
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struct inno_mipi_dphy_timing {
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unsigned int max_lane_mbps;
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u8 hs_prepare;
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u8 clk_lane_hs_zero;
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u8 data_lane_hs_zero;
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u8 hs_trail;
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static const struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table[] = {
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{ 110, 0x00, 0x20, 0x16, 0x02, 0x22},
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{ 150, 0x00, 0x06, 0x16, 0x03, 0x45},
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{ 200, 0x00, 0x18, 0x17, 0x04, 0x0b},
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{ 250, 0x00, 0x05, 0x17, 0x05, 0x16},
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{ 300, 0x00, 0x51, 0x18, 0x06, 0x2c},
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{ 400, 0x00, 0x64, 0x19, 0x07, 0x33},
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{ 500, 0x00, 0x20, 0x1b, 0x07, 0x4e},
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{ 600, 0x00, 0x6a, 0x1d, 0x08, 0x3a},
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{ 700, 0x00, 0x3e, 0x1e, 0x08, 0x6a},
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{ 800, 0x00, 0x21, 0x1f, 0x09, 0x29},
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{1000, 0x00, 0x09, 0x20, 0x09, 0x27},
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};
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static const struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table[] = {
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{ 110, 0x20, 0x16, 0x02, 0x22},
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{ 150, 0x06, 0x16, 0x03, 0x45},
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{ 200, 0x18, 0x17, 0x04, 0x0b},
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{ 250, 0x05, 0x17, 0x05, 0x16},
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{ 300, 0x51, 0x18, 0x06, 0x2c},
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{ 400, 0x64, 0x19, 0x07, 0x33},
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{ 500, 0x20, 0x1b, 0x07, 0x4e},
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{ 600, 0x6a, 0x1d, 0x08, 0x3a},
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{ 700, 0x3e, 0x1e, 0x08, 0x6a},
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{ 800, 0x21, 0x1f, 0x09, 0x29},
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{1000, 0x09, 0x20, 0x09, 0x27},
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static const
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struct inno_mipi_dphy_timing inno_mipi_dphy_gf22fdx_timing_table[] = {
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{ 110, 0x02, 0x7f, 0x16, 0x02, 0x02},
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{ 150, 0x02, 0x7f, 0x16, 0x03, 0x02},
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{ 200, 0x02, 0x7f, 0x17, 0x04, 0x02},
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{ 250, 0x02, 0x7f, 0x17, 0x05, 0x04},
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{ 300, 0x02, 0x7f, 0x18, 0x06, 0x04},
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{ 400, 0x03, 0x7e, 0x19, 0x07, 0x04},
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{ 500, 0x03, 0x7c, 0x1b, 0x07, 0x08},
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{ 600, 0x03, 0x70, 0x1d, 0x08, 0x10},
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{ 700, 0x05, 0x40, 0x1e, 0x08, 0x30},
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{ 800, 0x05, 0x02, 0x1f, 0x09, 0x30},
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{1000, 0x05, 0x08, 0x20, 0x09, 0x30},
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{1200, 0x06, 0x03, 0x32, 0x14, 0x0f},
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{1400, 0x09, 0x03, 0x32, 0x14, 0x0f},
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{1600, 0x0d, 0x42, 0x36, 0x0e, 0x0f},
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{1800, 0x0e, 0x47, 0x7a, 0x0e, 0x0f},
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{2000, 0x11, 0x64, 0x7a, 0x0e, 0x0b},
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{2200, 0x13, 0x64, 0x7e, 0x15, 0x0b},
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{2400, 0x13, 0x33, 0x7f, 0x15, 0x6a},
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{2500, 0x15, 0x54, 0x7f, 0x15, 0x6a},
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};
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static const struct pinctrl_pin_desc inno_video_phy_pins[] = {
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@ -494,6 +521,9 @@ static void inno_mipi_dphy_pll_enable(struct inno_mipi_dphy *inno)
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REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv >> 8));
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inno_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
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REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv));
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if (inno->socdata->post_div_enable)
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inno_update_bits(inno, REGISTER_PART_ANALOG, 0x08,
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PLL_POST_DIV_ENABLE_MASK, PLL_POST_DIV_ENABLE);
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inno_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
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REG_LDOPD_MASK | REG_PLLPD_MASK,
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REG_LDOPD_POWER_ON | REG_PLLPD_POWER_ON);
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@ -535,18 +565,19 @@ static void mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing,
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}
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static const struct inno_mipi_dphy_timing *
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inno_mipi_dphy_get_timing(unsigned int lane_mbps)
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inno_mipi_dphy_get_timing(struct inno_mipi_dphy *inno)
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{
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unsigned int lane_mbps = inno->lane_rate / USEC_PER_SEC;
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(inno_mipi_dphy_timing_table); i++)
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if (lane_mbps <= inno_mipi_dphy_timing_table[i].max_lane_mbps)
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for (i = 0; i < inno->socdata->num_timings; i++)
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if (lane_mbps <= inno->socdata->timings[i].max_lane_mbps)
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break;
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if (i == ARRAY_SIZE(inno_mipi_dphy_timing_table))
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if (i == inno->socdata->num_timings)
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--i;
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return &inno_mipi_dphy_timing_table[i];
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return &inno->socdata->timings[i];
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}
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static void inno_mipi_dphy_timing_init(struct inno_mipi_dphy *inno)
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@ -571,7 +602,7 @@ static void inno_mipi_dphy_timing_init(struct inno_mipi_dphy *inno)
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txbyteclk, ui, sys_clk);
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mipi_dphy_timing_get_default(&gotp, ui);
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timing = inno_mipi_dphy_get_timing(inno->lane_rate / USEC_PER_SEC);
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timing = inno_mipi_dphy_get_timing(inno);
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hs_exit = DIV_ROUND_UP(gotp.hsexit * txbyteclk, NSEC_PER_SEC);
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clk_post = DIV_ROUND_UP(gotp.clkpost * txbyteclk, NSEC_PER_SEC);
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@ -581,9 +612,14 @@ static void inno_mipi_dphy_timing_init(struct inno_mipi_dphy *inno)
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if (wakeup > 0x3ff)
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wakeup = 0x3ff;
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lpx = DIV_ROUND_UP(txbyteclk * gotp.lpx, NSEC_PER_SEC);
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if (lpx >= 2)
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lpx -= 2;
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if (timing->lpx) {
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lpx = timing->lpx;
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} else {
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/* Tlpx = Tpin_txbyteclkhs * (2 + value) */
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lpx = DIV_ROUND_UP(txbyteclk * gotp.lpx, NSEC_PER_SEC);
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if (lpx >= 2)
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lpx -= 2;
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}
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ta_go = DIV_ROUND_UP(gotp.tago * txclkesc, NSEC_PER_SEC);
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ta_sure = DIV_ROUND_UP(gotp.tasure * txclkesc, NSEC_PER_SEC);
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@ -640,12 +676,15 @@ static void inno_mipi_dphy_timing_init(struct inno_mipi_dphy *inno)
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}
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}
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static unsigned long inno_mipi_dphy_pll_rate_fixup(unsigned long fin,
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static unsigned long inno_mipi_dphy_pll_round_rate(struct inno_mipi_dphy *inno,
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unsigned long prate,
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unsigned long rate,
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u8 *prediv, u16 *fbdiv)
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{
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const struct inno_mipi_dphy_timing *timings = inno->socdata->timings;
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unsigned int num_timings = inno->socdata->num_timings;
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unsigned long best_freq = 0;
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unsigned long fout;
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unsigned int fin, fout, max_fout;
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u8 min_prediv, max_prediv;
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u8 _prediv, best_prediv = 1;
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u16 _fbdiv, best_fbdiv = 1;
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@ -656,34 +695,34 @@ static unsigned long inno_mipi_dphy_pll_rate_fixup(unsigned long fin,
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* PLL_Output_Frequency = (FREF / PREDIV * FBDIV) / 2
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* PLL_Output_Frequency: it is equal to DDR-Clock-Frequency * 2
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*/
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fout = 2 * rate;
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fin = prate / USEC_PER_SEC;
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fout = 2 * (rate / USEC_PER_SEC);
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max_fout = 2 * timings[num_timings - 1].max_lane_mbps;
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if (fout > max_fout)
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fout = max_fout;
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/* constraint: 5Mhz < Fref / prediv < 40MHz */
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min_prediv = DIV_ROUND_UP(fin, 40000000);
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max_prediv = fin / 5000000;
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min_prediv = DIV_ROUND_UP(fin, 40);
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max_prediv = fin / 5;
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for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) {
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u64 tmp;
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u32 delta;
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u32 delta, tmp;
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tmp = (u64)fout * _prediv;
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do_div(tmp, fin);
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_fbdiv = tmp;
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_fbdiv = fout * _prediv / fin;
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/*
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* The all possible settings of feedback divider are
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* 12, 13, 14, 16, ~ 511
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*/
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if ((_fbdiv == 15) || (_fbdiv < 12) || (_fbdiv > 511))
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continue;
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tmp = (u64)_fbdiv * fin;
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do_div(tmp, _prediv);
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tmp = _fbdiv * fin / _prediv;
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delta = abs(fout - tmp);
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if (delta < min_delta) {
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best_prediv = _prediv;
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best_fbdiv = _fbdiv;
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min_delta = delta;
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best_freq = tmp;
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best_freq = tmp * USEC_PER_SEC;
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}
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}
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@ -744,7 +783,8 @@ static long inno_mipi_dphy_pll_clk_round_rate(struct clk_hw *hw,
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u16 fbdiv = 1;
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u8 prediv = 1;
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fout = inno_mipi_dphy_pll_rate_fixup(fin, rate, &prediv, &fbdiv);
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fout = inno_mipi_dphy_pll_round_rate(inno, fin, rate,
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&prediv, &fbdiv);
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dev_dbg(inno->dev, "%s: fin=%lu, req_rate=%lu\n",
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__func__, *prate, rate);
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@ -965,25 +1005,46 @@ static int inno_mipi_dphy_remove(struct platform_device *pdev)
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static const struct inno_video_phy_socdata px30_socdata = {
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.has_h2p_clk = false,
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.pinmux = false,
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.post_div_enable = false,
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.timings = inno_mipi_dphy_timing_table,
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.num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table),
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};
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static const struct inno_video_phy_socdata rk1808_socdata = {
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.has_h2p_clk = false,
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.pinmux = false,
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.post_div_enable = true,
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.timings = inno_mipi_dphy_gf22fdx_timing_table,
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.num_timings = ARRAY_SIZE(inno_mipi_dphy_gf22fdx_timing_table),
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};
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static const struct inno_video_phy_socdata rk3128_socdata = {
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.has_h2p_clk = true,
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.pinmux = false,
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.post_div_enable = false,
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.timings = inno_mipi_dphy_timing_table,
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.num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table),
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};
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static const struct inno_video_phy_socdata rk3366_socdata = {
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.has_h2p_clk = false,
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.pinmux = false,
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.post_div_enable = false,
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.timings = inno_mipi_dphy_timing_table,
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.num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table),
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};
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static const struct inno_video_phy_socdata rk3368_socdata = {
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.has_h2p_clk = false,
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.pinmux = true,
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.post_div_enable = false,
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.timings = inno_mipi_dphy_timing_table,
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.num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table),
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};
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static const struct of_device_id inno_mipi_dphy_of_match[] = {
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{ .compatible = "rockchip,px30-mipi-dphy", .data = &px30_socdata },
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{ .compatible = "rockchip,rk1808-mipi-dphy", .data = &rk1808_socdata },
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{ .compatible = "rockchip,rk3128-mipi-dphy", .data = &rk3128_socdata },
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{ .compatible = "rockchip,rk3366-mipi-dphy", .data = &rk3366_socdata },
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{ .compatible = "rockchip,rk3368-mipi-dphy", .data = &rk3368_socdata },
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