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spi: rzv2h-rspi: set TX FIFO threshold to 0

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In PIO mode we send data word-by-word, and wait for the received data
to be available after each sent word, making no use of the TX interrupt.

In DMA mode, we need to set the RX and TX FIFO thresholds to 0, as
described in the User Manual.

In preparation for implementing DMA support, set TX FIFO threshold to 0,
as RX FIFO threshold is already 0.

Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Link: https://patch.msgid.link/20251201134229.600817-8-cosmin-gabriel.tanislav.xa@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Cosmin Tanislav 2025-12-01 15:42:23 +02:00 committed by Mark Brown
parent 6f9026b5a1
commit a886baaaa6
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1 changed files with 1 additions and 1 deletions
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2
drivers/spi/spi-rzv2h-rspi.c
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@ -501,7 +501,7 @@ static int rzv2h_rspi_prepare_message(struct spi_controller *ctlr,
writeb(0, rspi->base + RSPI_SSLP);
/* Setup FIFO thresholds */
conf16 = FIELD_PREP(RSPI_SPDCR2_TTRG, rspi->info->fifo_size - 1);
conf16 = FIELD_PREP(RSPI_SPDCR2_TTRG, 0);
conf16 |= FIELD_PREP(RSPI_SPDCR2_RTRG, 0);
writew(conf16, rspi->base + RSPI_SPDCR2);