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drm/amdgpu/display: re-add surface size calculation in dcn30_hwseq.c

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This is required for MALL.  Was accidently removed in PSR update.

Fixes: 48e48e5984 ("drm/amd/display: Disable idle optimization when PSR is enabled")
Fixes: 52f2e83e2f ("drm/amdgpu/display: add MALL support (v2)")
Acked-by: Slava Abramov <slava.abramov@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2020-10-26 12:11:29 -04:00
parent fddc611ca3
commit a87a9a73d0
1 changed files with 15 additions and 0 deletions
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15
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
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@ -715,6 +715,21 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
break;
}
if (dc->current_state->stream_count == 1 // single display only
&& dc->current_state->stream_status[0].plane_count == 1 // single surface only
&& dc->current_state->stream_status[0].plane_states[0]->address.page_table_base.quad_part == 0 // no VM
// Only 8 and 16 bit formats
&& dc->current_state->stream_status[0].plane_states[0]->format <= SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F
&& dc->current_state->stream_status[0].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888) {
surface_size = dc->current_state->stream_status[0].plane_states[0]->plane_size.surface_pitch *
dc->current_state->stream_status[0].plane_states[0]->plane_size.surface_size.height *
(dc->current_state->stream_status[0].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ?
8 : 4);
} else {
// TODO: remove hard code size
surface_size = 128 * 1024 * 1024;
}
// TODO: remove hard code size
if (surface_size < 128 * 1024 * 1024) {
refresh_hz = div_u64((unsigned long long) dc->current_state->streams[0]->timing.pix_clk_100hz *