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Microchip AT91 device tree updates for v6.12

Browse Source 
It contains:
 - SAMA7G5-EK DTS was updated with EEPROM nodes containing Ethernet
   addresses (needed, at least, when U-Boot is removed from the booting
   chain)
 - 5V supplies were added to to MCP16502 PMIC nodes for better hardware
   description
 - cleanups around pinctrl nodes which removed many dtbs_check warnings;
   along with it the pinctrl documentation was converted to json schema
 - fixes for the RTC and RTT supply clocks on SAMA7G5 and SAM9X60
 - other cleanups to fix dtbs_check warnings
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Merge tag 'at91-dt-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/dt

Microchip AT91 device tree updates for v6.12

It contains:
- SAMA7G5-EK DTS was updated with EEPROM nodes containing Ethernet
  addresses (needed, at least, when U-Boot is removed from the booting
  chain)
- 5V supplies were added to to MCP16502 PMIC nodes for better hardware
  description
- cleanups around pinctrl nodes which removed many dtbs_check warnings;
  along with it the pinctrl documentation was converted to json schema
- fixes for the RTC and RTT supply clocks on SAMA7G5 and SAM9X60
- other cleanups to fix dtbs_check warnings

* tag 'at91-dt-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
  ARM: dts: microchip: sama7g5: Fix RTT clock
  ARM: dts: microchip: sam9x60: Fix rtc/rtt clocks
  dt-bindings: pinctrl: Convert Atmel PIO3 pinctrl to json-schema
  ARM: dts: microchip: sam9x60: Remove additional compatible string from GPIO node
  ARM: dts: microchip: Remove additional compatible string from PIO3 pinctrl nodes
  ARM: dts: microchip: change to simple-mfd from simple-bus for PIO3 pinumux controller
  ARM: dts: microchip: sama5d29_curiosity: Add reg_5v to supply PMIC nodes
  ARM: dts: microchip: at91-sama5d27_wlsom1: Add reg_5v to supply PMIC nodes
  ARM: dts: microchip: at91-sama5d2_icp: Add reg_5v to supply PMIC nodes
  ARM: dts: microchip: at91-sama7g54_curiosity: Add reg_5v to supply PMIC nodes
  ARM: dts: microchip: at91-sama7g5ek: Add reg_5v to supply PMIC nodes
  ARM: dts: microchip: at91: align LED node name with bindings
  ARM: dts: microchip: sam9x60: Move i2c address/size to dtsi
  ARM: dts: microchip: at91-sama7g5ek: add EEPROMs

Link: https://lore.kernel.org/r/20240901133110.2038675-2-claudiu.beznea@tuxon.dev
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2024-09-03 10:36:57 +00:00
commit a86f3dc85f
25 changed files with 352 additions and 221 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

178
Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
View File

@ -1,178 +0,0 @@
* Atmel AT91 Pinmux Controller
The AT91 Pinmux Controller, enables the IC
to share one PAD to several functional blocks. The sharing is done by
multiplexing the PAD input/output signals. For each PAD there are up to
8 muxing options (called periph modes). Since different modules require
different PAD settings (like pull up, keeper, etc) the controller controls
also the PAD settings parameters.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
Atmel AT91 pin configuration node is a node of a group of pins which can be
used for a specific device or function. This node represents both mux and config
of the pins in that group. The 'pins' selects the function mode(also named pin
mode) this pin can work on and the 'config' configures various pad settings
such as pull-up, multi drive, etc.
Required properties for iomux controller:
- compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
or "atmel,sama5d3-pinctrl" or "microchip,sam9x60-pinctrl"
or "microchip,sam9x7-pinctrl", "microchip,sam9x60-pinctrl"
- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
configured in this periph mode. All the periph and bank need to be describe.
How to create such array:
Each column will represent the possible peripheral of the pinctrl
Each line will represent a pio bank
Take an example on the 9260
Peripheral: 2 ( A and B)
Bank: 3 (A, B and C)
=>
/* A B */
0xffffffff 0xffc00c3b /* pioA */
0xffffffff 0x7fff3ccf /* pioB */
0xffffffff 0x007fffff /* pioC */
For each peripheral/bank we will describe in a u32 if a pin can be
configured in it by putting 1 to the pin bit (1 << pin)
Let's take the pioA on peripheral B
From the datasheet Table 10-2.
Peripheral B
PA0 MCDB0
PA1 MCCDB
PA2
PA3 MCDB3
PA4 MCDB2
PA5 MCDB1
PA6
PA7
PA8
PA9
PA10 ETX2
PA11 ETX3
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22 ETXER
PA23 ETX2
PA24 ETX3
PA25 ERX2
PA26 ERX3
PA27 ERXCK
PA28 ECRS
PA29 ECOL
PA30 RXD4
PA31 TXD4
=> 0xffc00c3b
Required properties for pin configuration node:
- atmel,pins: 4 integers array, represents a group of pins mux and config
setting. The format is atmel,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>.
The PERIPH 0 means gpio, PERIPH 1 is periph A, PERIPH 2 is periph B...
PIN_BANK 0 is pioA, PIN_BANK 1 is pioB...
Bits used for CONFIG:
PULL_UP (1 << 0): indicate this pin needs a pull up.
MULTIDRIVE (1 << 1): indicate this pin needs to be configured as multi-drive.
Multi-drive is equivalent to open-drain type output.
DEGLITCH (1 << 2): indicate this pin needs deglitch.
PULL_DOWN (1 << 3): indicate this pin needs a pull down.
DIS_SCHMIT (1 << 4): indicate this pin needs to the disable schmitt trigger.
DRIVE_STRENGTH (3 << 5): indicate the drive strength of the pin using the
following values:
00 - No change (reset state value kept)
01 - Low
10 - Medium
11 - High
OUTPUT (1 << 7): indicate this pin need to be configured as an output.
OUTPUT_VAL (1 << 8): output val (1 = high, 0 = low)
SLEWRATE (1 << 9): slew rate of the pin: 0 = disable, 1 = enable
DEBOUNCE (1 << 16): indicate this pin needs debounce.
DEBOUNCE_VAL (0x3fff << 17): debounce value.
NOTE:
Some requirements for using atmel,at91rm9200-pinctrl binding:
1. We have pin function node defined under at91 controller node to represent
what pinmux functions this SoC supports.
2. The driver can use the function node's name and pin configuration node's
name describe the pin function and group hierarchy.
For example, Linux at91 pinctrl driver takes the function node's name
as the function name and pin configuration node's name as group name to
create the map table.
3. Each pin configuration node should have a phandle, devices can set pins
configurations by referring to the phandle of that pin configuration node.
4. The gpio controller must be describe in the pinctrl simple-bus.
For each bank the required properties are:
- compatible: "atmel,at91sam9x5-gpio" or "atmel,at91rm9200-gpio" or
"microchip,sam9x60-gpio"
or "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio"
- reg: physical base address and length of the controller's registers
- interrupts: interrupt outputs from the controller
- interrupt-controller: marks the device node as an interrupt controller
- #interrupt-cells: should be 2; refer to ../interrupt-controller/interrupts.txt
for more details.
- gpio-controller
- #gpio-cells: should be 2; the first cell is the GPIO number and the second
cell specifies GPIO flags as defined in <dt-bindings/gpio/gpio.h>.
- clocks: bank clock
Examples:
pinctrl@fffff400 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
reg = <0xfffff400 0x600>;
pioA: gpio@fffff400 {
compatible = "atmel,at91sam9x5-gpio";
reg = <0xfffff400 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
};
atmel,mux-mask = <
/* A B */
0xffffffff 0xffc00c3b /* pioA */
0xffffffff 0x7fff3ccf /* pioB */
0xffffffff 0x007fffff /* pioC */
>;
/* shared pinctrl settings */
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
<1 14 0x1 0x0 /* PB14 periph A */
1 15 0x1 0x1>; /* PB15 periph A with pullup */
};
};
};
dbgu: serial@fffff200 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffff200 0x200>;
interrupts = <1 4 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
};

184
Documentation/devicetree/bindings/pinctrl/atmel,at91rm9200-pinctrl.yaml Normal file
View File

@ -0,0 +1,184 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/atmel,at91rm9200-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip PIO3 Pinmux Controller
maintainers:
- Manikandan Muralidharan <manikandan.m@microchip.com>
description:
The AT91 Pinmux Controller, enables the IC to share one PAD to several
functional blocks. The sharing is done by multiplexing the PAD input/output
signals. For each PAD there are up to 8 muxing options (called periph modes).
Since different modules require different PAD settings (like pull up, keeper,
etc) the controller controls also the PAD settings parameters.
properties:
compatible:
oneOf:
- items:
- enum:
- atmel,at91rm9200-pinctrl
- atmel,at91sam9x5-pinctrl
- atmel,sama5d3-pinctrl
- microchip,sam9x60-pinctrl
- const: simple-mfd
- items:
- enum:
- microchip,sam9x7-pinctrl
- const: microchip,sam9x60-pinctrl
- const: simple-mfd
'#address-cells':
const: 1
'#size-cells':
const: 1
ranges: true
atmel,mux-mask:
$ref: /schemas/types.yaml#/definitions/uint32-matrix
description: |
Array of mask (periph per bank) to describe if a pin can be
configured in this periph mode. All the periph and bank need to
be described.
#How to create such array:
Each column will represent the possible peripheral of the pinctrl
Each line will represent a pio bank
#Example:
In at91sam9260.dtsi,
Peripheral: 2 ( A and B)
Bank: 3 (A, B and C)
# A B
0xffffffff 0xffc00c3b # pioA
0xffffffff 0x7fff3ccf # pioB
0xffffffff 0x007fffff # pioC
For each peripheral/bank we will describe in a u32 if a pin can be
configured in it by putting 1 to the pin bit (1 << pin)
Let's take the pioA on peripheral B whose value is 0xffc00c3b
From the datasheet Table 10-2.
Peripheral B
PA0 MCDB0
PA1 MCCDB
PA2
PA3 MCDB3
PA4 MCDB2
PA5 MCDB1
PA6
PA7
PA8
PA9
PA10 ETX2
PA11 ETX3
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22 ETXER
PA23 ETX2
PA24 ETX3
PA25 ERX2
PA26 ERX3
PA27 ERXCK
PA28 ECRS
PA29 ECOL
PA30 RXD4
PA31 TXD4
allOf:
- $ref: pinctrl.yaml#
required:
- compatible
- ranges
- "#address-cells"
- "#size-cells"
- atmel,mux-mask
patternProperties:
'gpio@[0-9a-f]+$':
$ref: /schemas/gpio/atmel,at91rm9200-gpio.yaml
unevaluatedProperties: false
additionalProperties:
type: object
additionalProperties:
type: object
additionalProperties: false
properties:
atmel,pins:
$ref: /schemas/types.yaml#/definitions/uint32-matrix
description: |
Each entry consists of 4 integers and represents the pins
mux and config setting.The format is
atmel,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>.
Supported pin number and mux varies for different SoCs, and
are defined in <include/dt-bindings/pinctrl/at91.h>.
items:
items:
- description:
Pin bank
- description:
Pin bank index
- description:
Peripheral function
- description:
Pad configuration
examples:
- |
#include <dt-bindings/clock/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/at91.h>
pinctrl@fffff400 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at91rm9200-pinctrl", "simple-mfd";
ranges = <0xfffff400 0xfffff400 0x600>;
atmel,mux-mask = <
/* A B */
0xffffffff 0xffc00c3b /* pioA */
0xffffffff 0x7fff3ccf /* pioB */
0xffffffff 0x007fffff /* pioC */
>;
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
<AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
pioA: gpio@fffff400 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
};
};
...

2
arch/arm/boot/dts/microchip/at91-sam9x60_curiosity.dts
View File

@ -198,8 +198,6 @@ i2c0: i2c@600 {
dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx0_default>;
#address-cells = <1>;
#size-cells = <0>;
i2c-analog-filter;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;

4
arch/arm/boot/dts/microchip/at91-sam9x60ek.dts
View File

@ -207,8 +207,6 @@ &flx0 {
status = "okay";
i2c0: i2c@600 {
#address-cells = <1>;
#size-cells = <0>;
dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx0_default>;
@ -254,8 +252,6 @@ &flx6 {
status = "okay";
i2c6: i2c@600 {
#address-cells = <1>;
#size-cells = <0>;
dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx6_default>;

13
arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi
View File

@ -31,6 +31,14 @@ main_xtal {
};
};
reg_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "VDD_MAIN";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-wilc1000";
reset-gpios = <&pioA PIN_PA27 GPIO_ACTIVE_HIGH>;
@ -70,6 +78,11 @@ &i2c1 {
mcp16502@5b {
compatible = "microchip,mcp16502";
reg = <0x5b>;
lvin-supply = <&reg_5v>;
pvin1-supply = <&reg_5v>;
pvin2-supply = <&reg_5v>;
pvin3-supply = <&reg_5v>;
pvin4-supply = <&reg_5v>;
status = "okay";
lpm-gpios = <&pioBU 0 GPIO_ACTIVE_LOW>;

13
arch/arm/boot/dts/microchip/at91-sama5d29_curiosity.dts
View File

@ -84,6 +84,14 @@ memory@20000000 {
device_type = "memory";
reg = <0x20000000 0x20000000>;
};
reg_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "5V_MAIN";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
};
&adc {
@ -144,6 +152,11 @@ &i2c0 {
mcp16502@5b {
compatible = "microchip,mcp16502";
reg = <0x5b>;
lvin-supply = <&reg_5v>;
pvin1-supply = <&reg_5v>;
pvin2-supply = <&reg_5v>;
pvin3-supply = <&reg_5v>;
pvin4-supply = <&reg_5v>;
status = "okay";
lpm-gpios = <&pioBU 0 GPIO_ACTIVE_LOW>;

13
arch/arm/boot/dts/microchip/at91-sama5d2_icp.dts
View File

@ -78,6 +78,14 @@ led-blue {
linux,default-trigger = "heartbeat";
};
};
reg_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "VDD_MAIN_5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
};
&adc {
@ -190,6 +198,11 @@ i2c6: i2c@600 {
mcp16502@5b {
compatible = "microchip,mcp16502";
reg = <0x5b>;
lvin-supply = <&reg_5v>;
pvin1-supply = <&reg_5v>;
pvin2-supply = <&reg_5v>;
pvin3-supply = <&reg_5v>;
pvin4-supply = <&reg_5v>;
status = "okay";
lpm-gpios = <&pioBU 7 GPIO_ACTIVE_LOW>;

13
arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dts
View File

@ -72,6 +72,14 @@ memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x10000000>; /* 256 MiB DDR3L-1066 16-bit */
};
reg_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "5V_MAIN";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
};
&adc {
@ -189,6 +197,11 @@ eeprom@51 {
pmic@5b {
compatible = "microchip,mcp16502";
reg = <0x5b>;
lvin-supply = <&reg_5v>;
pvin1-supply = <&reg_5v>;
pvin2-supply = <&reg_5v>;
pvin3-supply = <&reg_5v>;
pvin4-supply = <&reg_5v>;
regulators {
vdd_3v3: VDD_IO {

53
arch/arm/boot/dts/microchip/at91-sama7g5ek.dts
View File

@ -88,6 +88,14 @@ memory@60000000 {
reg = <0x60000000 0x20000000>;
};
reg_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "5V_MAIN";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
sound: sound {
compatible = "simple-audio-card";
simple-audio-card,name = "sama7g5ek audio";
@ -239,6 +247,11 @@ i2c1: i2c@600 {
mcp16502@5b {
compatible = "microchip,mcp16502";
reg = <0x5b>;
lvin-supply = <&reg_5v>;
pvin1-supply = <&reg_5v>;
pvin2-supply = <&reg_5v>;
pvin3-supply = <&reg_5v>;
pvin4-supply = <&reg_5v>;
status = "okay";
regulators {
@ -403,6 +416,42 @@ i2c8: i2c@600 {
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
status = "okay";
eeprom0: eeprom@52 {
compatible = "microchip,24aa025e48";
reg = <0x52>;
size = <256>;
pagesize = <16>;
vcc-supply = <&vdd_3v3>;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
eeprom0_eui48: eui48@fa {
reg = <0xfa 0x6>;
};
};
};
eeprom1: eeprom@53 {
compatible = "microchip,24aa025e48";
reg = <0x53>;
size = <256>;
pagesize = <16>;
vcc-supply = <&vdd_3v3>;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
eeprom1_eui48: eui48@fa {
reg = <0xfa 0x6>;
};
};
};
};
};
@ -440,6 +489,8 @@ &pinctrl_gmac0_mdio_default
&pinctrl_gmac0_txck_default
&pinctrl_gmac0_phy_irq>;
phy-mode = "rgmii-id";
nvmem-cells = <&eeprom0_eui48>;
nvmem-cell-names = "mac-address";
status = "okay";
ethernet-phy@7 {
@ -457,6 +508,8 @@ &gmac1 {
&pinctrl_gmac1_mdio_default
&pinctrl_gmac1_phy_irq>;
phy-mode = "rmii";
nvmem-cells = <&eeprom1_eui48>;
nvmem-cell-names = "mac-address";
status = "okay"; /* Conflict with pdmc0. */
ethernet-phy@0 {

2
arch/arm/boot/dts/microchip/at91rm9200.dtsi
View File

@ -225,7 +225,7 @@ macb0: ethernet@fffbc000 {
pinctrl@fffff400 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
compatible = "atmel,at91rm9200-pinctrl", "simple-mfd";
ranges = <0xfffff400 0xfffff400 0x800>;
atmel,mux-mask = <

2
arch/arm/boot/dts/microchip/at91sam9260.dtsi
View File

@ -170,7 +170,7 @@ tcb1: timer@fffdc000 {
pinctrl: pinctrl@fffff400 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
compatible = "atmel,at91rm9200-pinctrl", "simple-mfd";
ranges = <0xfffff400 0xfffff400 0x600>;
atmel,mux-mask = <

2
arch/arm/boot/dts/microchip/at91sam9261.dtsi
View File

@ -317,7 +317,7 @@ dbgu: serial@fffff200 {
pinctrl@fffff400 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
compatible = "atmel,at91rm9200-pinctrl", "simple-mfd";
ranges = <0xfffff400 0xfffff400 0x600>;
atmel,mux-mask =

2
arch/arm/boot/dts/microchip/at91sam9263.dtsi
View File

@ -167,7 +167,7 @@ poweroff@fffffd10 {
pinctrl@fffff200 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
compatible = "atmel,at91rm9200-pinctrl", "simple-mfd";
ranges = <0xfffff200 0xfffff200 0xa00>;
atmel,mux-mask = <

4
arch/arm/boot/dts/microchip/at91sam9g20ek_2mmc.dts
View File

@ -40,13 +40,13 @@ pinctrl_board_mmc0_slot0: mmc0_slot0-board {
leds {
compatible = "gpio-leds";
ds1 {
led-ds1 {
label = "ds1";
gpios = <&pioB 9 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
ds5 {
led-ds5 {
label = "ds5";
gpios = <&pioB 8 GPIO_ACTIVE_LOW>;
};

24
arch/arm/boot/dts/microchip/at91sam9g25-gardena-smart-gateway.dts
View File

@ -37,71 +37,71 @@ button {
leds {
compatible = "gpio-leds";
power_blue {
led-power-blue {
label = "smartgw:power:blue";
gpios = <&pioC 21 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
power_green {
led-power-green {
label = "smartgw:power:green";
gpios = <&pioC 20 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
power_red {
led-power-red {
label = "smartgw:power:red";
gpios = <&pioC 19 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
radio_blue {
led-radio-blue {
label = "smartgw:radio:blue";
gpios = <&pioC 18 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
radio_green {
led-radio-green {
label = "smartgw:radio:green";
gpios = <&pioC 17 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
radio_red {
led-radio-red {
label = "smartgw:radio:red";
gpios = <&pioC 16 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
internet_blue {
led-internet-blue {
label = "smartgw:internet:blue";
gpios = <&pioC 15 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
internet_green {
led-internet-green {
label = "smartgw:internet:green";
gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
internet_red {
led-internet-red {
label = "smartgw:internet:red";
gpios = <&pioC 13 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
heartbeat {
led-heartbeat {
label = "smartgw:heartbeat";
gpios = <&pioB 8 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
pb18 {
led-pb18 {
status = "disabled";
};
pd21 {
led-pd21 {
status = "disabled";
};
};

2
arch/arm/boot/dts/microchip/at91sam9g45.dtsi
View File

@ -190,7 +190,7 @@ dma: dma-controller@ffffec00 {
pinctrl@fffff200 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
compatible = "atmel,at91rm9200-pinctrl", "simple-mfd";
ranges = <0xfffff200 0xfffff200 0xa00>;
atmel,mux-mask = <

2
arch/arm/boot/dts/microchip/at91sam9n12.dtsi
View File

@ -226,7 +226,7 @@ dma: dma-controller@ffffec00 {
pinctrl@fffff400 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
compatible = "atmel,at91sam9x5-pinctrl", "simple-mfd";
ranges = <0xfffff400 0xfffff400 0x800>;
atmel,mux-mask = <

6
arch/arm/boot/dts/microchip/at91sam9n12ek.dts
View File

@ -207,19 +207,19 @@ bl_reg: backlight_regulator {
leds {
compatible = "gpio-leds";
d8 {
led-d8 {
label = "d8";
gpios = <&pioB 4 GPIO_ACTIVE_LOW>;
linux,default-trigger = "mmc0";
};
d9 {
led-d9 {
label = "d9";
gpios = <&pioB 5 GPIO_ACTIVE_LOW>;
linux,default-trigger = "nand-disk";
};
d10 {
led-d10 {
label = "d10";
gpios = <&pioB 6 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";

2
arch/arm/boot/dts/microchip/at91sam9rl.dtsi
View File

@ -339,7 +339,7 @@ dbgu: serial@fffff200 {
pinctrl@fffff400 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
compatible = "atmel,at91rm9200-pinctrl", "simple-mfd";
ranges = <0xfffff400 0xfffff400 0x800>;
atmel,mux-mask =

2
arch/arm/boot/dts/microchip/at91sam9x5.dtsi
View File

@ -202,7 +202,7 @@ dma1: dma-controller@ffffee00 {
pinctrl: pinctrl@fffff400 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
compatible = "atmel,at91sam9x5-pinctrl", "simple-mfd";
ranges = <0xfffff400 0xfffff400 0x800>;
/* shared pinctrl settings */

4
arch/arm/boot/dts/microchip/at91sam9x5cm.dtsi
View File

@ -120,13 +120,13 @@ rootfs@800000 {
leds {
compatible = "gpio-leds";
pb18 {
led-pb18 {
label = "pb18";
gpios = <&pioB 18 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
pd21 {
led-pd21 {
label = "pd21";
gpios = <&pioD 21 GPIO_ACTIVE_HIGH>;
};

40
arch/arm/boot/dts/microchip/sam9x60.dtsi
View File

@ -215,6 +215,8 @@ i2c4: i2c@600 {
compatible = "microchip,sam9x60-i2c";
reg = <0x600 0x200>;
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
@ -284,6 +286,8 @@ i2c5: i2c@600 {
compatible = "microchip,sam9x60-i2c";
reg = <0x600 0x200>;
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
@ -394,6 +398,8 @@ i2c11: i2c@600 {
compatible = "microchip,sam9x60-i2c";
reg = <0x600 0x200>;
interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
@ -443,6 +449,8 @@ i2c12: i2c@600 {
compatible = "microchip,sam9x60-i2c";
reg = <0x600 0x200>;
interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
@ -600,6 +608,8 @@ i2c6: i2c@600 {
compatible = "microchip,sam9x60-i2c";
reg = <0x600 0x200>;
interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
@ -649,6 +659,8 @@ i2c7: i2c@600 {
compatible = "microchip,sam9x60-i2c";
reg = <0x600 0x200>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
@ -698,6 +710,8 @@ i2c8: i2c@600 {
compatible = "microchip,sam9x60-i2c";
reg = <0x600 0x200>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
@ -766,6 +780,8 @@ i2c0: i2c@600 {
compatible = "microchip,sam9x60-i2c";
reg = <0x600 0x200>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
@ -834,6 +850,8 @@ i2c1: i2c@600 {
compatible = "microchip,sam9x60-i2c";
reg = <0x600 0x200>;
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
@ -902,6 +920,8 @@ i2c2: i2c@600 {
compatible = "microchip,sam9x60-i2c";
reg = <0x600 0x200>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
@ -970,6 +990,8 @@ i2c3: i2c@600 {
compatible = "microchip,sam9x60-i2c";
reg = <0x600 0x200>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
@ -1074,6 +1096,8 @@ i2c9: i2c@600 {
compatible = "microchip,sam9x60-i2c";
reg = <0x600 0x200>;
interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
@ -1123,6 +1147,8 @@ i2c10: i2c@600 {
compatible = "microchip,sam9x60-i2c";
reg = <0x600 0x200>;
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
@ -1223,7 +1249,7 @@ AT91_XDMAC_DT_PERID(28))>,
pinctrl: pinctrl@fffff400 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "microchip,sam9x60-pinctrl", "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
compatible = "microchip,sam9x60-pinctrl", "simple-mfd";
ranges = <0xfffff400 0xfffff400 0x800>;
/* mux-mask corresponding to sam9x60 SoC in TFBGA228L package */
@ -1236,7 +1262,7 @@ pinctrl: pinctrl@fffff400 {
>;
pioA: gpio@fffff400 {
compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
compatible = "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
@ -1247,7 +1273,7 @@ pioA: gpio@fffff400 {
};
pioB: gpio@fffff600 {
compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
compatible = "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
@ -1259,7 +1285,7 @@ pioB: gpio@fffff600 {
};
pioC: gpio@fffff800 {
compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
compatible = "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x200>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
@ -1270,7 +1296,7 @@ pioC: gpio@fffff800 {
};
pioD: gpio@fffffa00 {
compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
compatible = "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffffa00 0x200>;
interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
@ -1312,7 +1338,7 @@ rtt: rtc@fffffe20 {
compatible = "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
reg = <0xfffffe20 0x20>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&clk32k 0>;
clocks = <&clk32k 1>;
};
pit: timer@fffffe40 {
@ -1338,7 +1364,7 @@ rtc: rtc@fffffea8 {
compatible = "microchip,sam9x60-rtc", "atmel,at91sam9x5-rtc";
reg = <0xfffffea8 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&clk32k 0>;
clocks = <&clk32k 1>;
};
watchdog: watchdog@ffffff80 {

2
arch/arm/boot/dts/microchip/sama5d3.dtsi
View File

@ -493,7 +493,7 @@ aic: interrupt-controller@fffff000 {
pinctrl: pinctrl@fffff200 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus";
compatible = "atmel,sama5d3-pinctrl", "simple-mfd";
ranges = <0xfffff200 0xfffff200 0xa00>;
atmel,mux-mask = <
/* A B C */

2
arch/arm/boot/dts/microchip/sama5d4.dtsi
View File

@ -791,7 +791,7 @@ dbgu: serial@fc069000 {
pinctrl: pinctrl@fc06a000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus";
compatible = "atmel,sama5d3-pinctrl", "simple-mfd";
ranges = <0xfc068000 0xfc068000 0x100
0xfc06a000 0xfc06a000 0x4000>;
/* WARNING: revisit as pin spec has changed */

2
arch/arm/boot/dts/microchip/sama7g5.dtsi
View File

@ -272,7 +272,7 @@ rtt: rtc@e001d020 {
compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
reg = <0xe001d020 0x30>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk32k 0>;
clocks = <&clk32k 1>;
};
clk32k: clock-controller@e001d050 {