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wifi: rtw89: 8852b: add basic baseband chip_ops

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chip_ops::bb_reset is to reset baseband state after loading parameters,
because its state could be unpredictable at that moment. The other is
chip_ops::bb_sethw that is to set some baseband settings not including in
parameter tables.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20221009125403.19662-4-pkshih@realtek.com
This commit is contained in:
Ping-Ke Shih 2022-10-09 20:53:57 +08:00 committed by Kalle Valo
parent b23b36efbd
commit a804479839
1 changed files with 42 additions and 0 deletions
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42
drivers/net/wireless/realtek/rtw89/rtw8852b.c
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@ -1066,6 +1066,46 @@ static void rtw8852b_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band,
}
}
static void rtw8852b_bb_reset(struct rtw89_dev *rtwdev,
enum rtw89_phy_idx phy_idx)
{
rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
rtw8852b_bb_reset_all(rtwdev, phy_idx);
rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
}
static void rtw8852b_bb_macid_ctrl_init(struct rtw89_dev *rtwdev,
enum rtw89_phy_idx phy_idx)
{
u32 addr;
for (addr = R_AX_PWR_MACID_LMT_TABLE0;
addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4)
rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0);
}
static void rtw8852b_bb_sethw(struct rtw89_dev *rtwdev)
{
struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP);
rtw89_phy_write32_clr(rtwdev, R_P1_EN_SOUND_WO_NDP, B_P1_EN_SOUND_WO_NDP);
rtw8852b_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0);
/* read these registers after loading BB parameters */
gain->offset_base[RTW89_PHY_0] =
rtw89_phy_read32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK);
gain->rssi_base[RTW89_PHY_0] =
rtw89_phy_read32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK);
}
static void rtw8852b_set_channel_bb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
enum rtw89_phy_idx phy_idx)
{
@ -1413,6 +1453,8 @@ static int rtw8852b_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
static const struct rtw89_chip_ops rtw8852b_chip_ops = {
.enable_bb_rf = rtw8852b_mac_enable_bb_rf,
.disable_bb_rf = rtw8852b_mac_disable_bb_rf,
.bb_reset = rtw8852b_bb_reset,
.bb_sethw = rtw8852b_bb_sethw,
.set_channel = rtw8852b_set_channel,
.set_channel_help = rtw8852b_set_channel_help,
.read_efuse = rtw8852b_read_efuse,