From a7d17fdc65930aaf37b283259654b02b477c2d8e Mon Sep 17 00:00:00 2001 From: Zheng Yang Date: Wed, 6 Dec 2017 15:54:52 +0800 Subject: [PATCH] drm: bridge: dw-hdmi: fix tmds clk in status show According to HDMI 2.0 chapter 6.1, for TMDS character Rates avove 340Mcsc, the TMDS Clock Rate shall be one fourth of the TMDS Character Rate. Change-Id: I4cc78aa1a5fbf6cec93e787dde49e482d0b4d342 Signed-off-by: Zheng Yang --- drivers/gpu/drm/bridge/dw-hdmi.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/bridge/dw-hdmi.c b/drivers/gpu/drm/bridge/dw-hdmi.c index 9254002971b6..b8ae3a5c77fd 100644 --- a/drivers/gpu/drm/bridge/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/dw-hdmi.c @@ -2973,7 +2973,7 @@ static int dw_hdmi_status_show(struct seq_file *s, void *v) struct dw_hdmi *hdmi = s->private; u32 val; - seq_puts(s, "PHY "); + seq_puts(s, "PHY: "); if (!hdmi->phy.enabled) { seq_puts(s, "disabled\n"); return 0; @@ -2983,9 +2983,12 @@ static int dw_hdmi_status_show(struct seq_file *s, void *v) seq_puts(s, "HDMI\n"); else seq_puts(s, "DVI\n"); + if (hdmi->hdmi_data.video_mode.mtmdsclock > 340000000) + val = hdmi->hdmi_data.video_mode.mtmdsclock / 4; + else + val = hdmi->hdmi_data.video_mode.mtmdsclock; seq_printf(s, "Pixel Clk: %uHz\t\tTMDS Clk: %uHz\n", - hdmi->hdmi_data.video_mode.mpixelclock, - hdmi->hdmi_data.video_mode.mtmdsclock); + hdmi->hdmi_data.video_mode.mpixelclock, val); seq_puts(s, "Color Format: "); if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) seq_puts(s, "RGB");