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Octeontx2-af: Broadcast XON on all channels
The NIX block receives traffic from multiple channels, including:
MAC block (RPM)
Loopback module (LBK)
CPT block
RPM
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LBK --| NIX |
-----------------
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CPT
Due to a hardware errata, CN10k and earlier Octeon silicon series,
the hardware may incorrectly assert XOFF on certain channels during
reset. As a workaround, a write operation to the NIX_AF_RX_CHANX_CFG
register can be performed to broadcast XON signals on the affected
channels
Signed-off-by: Hariprasad Kelam <hkelam@marvell.com>
Link: https://patch.msgid.link/20250820064625.1464361-1-hkelam@marvell.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
parent
62d7f40503
commit
a7bd721580
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@ -1164,6 +1164,9 @@ static int rvu_setup_hw_resources(struct rvu *rvu)
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rvu_program_channels(rvu);
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cgx_start_linkup(rvu);
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rvu_block_bcast_xon(rvu, BLKADDR_NIX0);
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rvu_block_bcast_xon(rvu, BLKADDR_NIX1);
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err = rvu_mcs_init(rvu);
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if (err) {
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dev_err(rvu->dev, "%s: Failed to initialize mcs\n", __func__);
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@ -1017,6 +1017,7 @@ int rvu_nix_mcast_update_mcam_entry(struct rvu *rvu, u16 pcifunc,
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void rvu_nix_flr_free_bpids(struct rvu *rvu, u16 pcifunc);
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int rvu_alloc_cint_qint_mem(struct rvu *rvu, struct rvu_pfvf *pfvf,
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int blkaddr, int nixlf);
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void rvu_block_bcast_xon(struct rvu *rvu, int blkaddr);
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/* NPC APIs */
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void rvu_npc_freemem(struct rvu *rvu);
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int rvu_npc_get_pkind(struct rvu *rvu, u16 pf);
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@ -6616,3 +6616,19 @@ int rvu_mbox_handler_nix_mcast_grp_update(struct rvu *rvu,
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return ret;
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}
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/* On CN10k and older series of silicons, hardware may incorrectly
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* assert XOFF on certain channels. Issue a write on NIX_AF_RX_CHANX_CFG
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* to broadcacst XON on the same.
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*/
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void rvu_block_bcast_xon(struct rvu *rvu, int blkaddr)
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{
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struct rvu_block *block = &rvu->hw->block[blkaddr];
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u64 cfg;
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if (!block->implemented || is_cn20k(rvu->pdev))
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return;
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cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(0));
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rvu_write64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(0), cfg);
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}
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