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MLK-11859: dts: Fix imx7D mipi csi reset bit error

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There is a error in i.MX7D RM RevB.
Actually the register of SRC_MIPIPHY_RCR(src offset 0x28)
bit 1 for MIPI PHY Master Reset
bit 2 for MIPI PHY Slave Reset.

Signed-off-by: Sandor Yu <R01008@freescale.com>
(cherry picked from commit 4f3128a79c023319c9e21690be866dc46a9d6816)
This commit is contained in:
Sandor Yu 2015-11-17 17:20:51 +08:00 committed by Nitin Garg
parent a5c6731837
commit a798e63e95
1 changed files with 1 additions and 1 deletions
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2
arch/arm/boot/dts/imx7d.dtsi
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@ -857,7 +857,7 @@ mipi_csi: mipi-csi@30750000 {
<&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
clock-names = "mipi_clk", "phy_clk";
mipi-phy-supply = <&reg_1p0d>;
csis-phy-reset = <&src 0x28 1>;
csis-phy-reset = <&src 0x28 2>;
bus-width = <4>;
status = "disabled";
};