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dt-bindings: gpio: add Axiado AX3005 SGPIO controller
Add a Devicetree binding for the SGPIO controller found on the Axiado AX3005 SoC. Each SGPIO position provides one fixed-direction input GPIO and one fixed-direction output GPIO. Input GPIOs support edge-triggered interrupts. The controller serializes output values and samples input values over dedicated data, clock, and latch signals. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Petar Stepanovic <pstepanovic@axiado.com> Link: https://patch.msgid.link/20260921-axiado-ax3000-sgpio-controller-v4-1-79c444be7faf@axiado.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
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Documentation/devicetree/bindings/gpio/axiado,ax3005-sgpio.yaml
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Documentation/devicetree/bindings/gpio/axiado,ax3005-sgpio.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/gpio/axiado,ax3005-sgpio.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Axiado AX3005 SGPIO Controller
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maintainers:
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- Petar Stepanovic <pstepanovic@axiado.com>
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- SriNavmani A <srinavmani@axiado.com>
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- Prasad Bolisetty <pbolisetty@axiado.com>
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description: |
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The Axiado SGPIO controller provides a serial GPIO expansion interface
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that multiplexes multiple GPIO signals over a small set of physical lines.
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The controller serializes output values on a data output line (DOUT) and
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samples input values from a data input line (DIN) in synchronization with
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a shift clock (SCLK). A latch signal (LATCH) updates the output states
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after each transfer cycle.
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SGPIO positions are organized in banks of 32, with registers controlling
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output values, input sampling, and interrupt status. The number of SGPIO
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positions supported depends on the controller configuration.
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The controller detects changes on input GPIOs. Interrupt events are
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aggregated and signaled through a single interrupt line to the parent
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interrupt controller.
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Register access is performed over the APB bus. The SGPIO shift clock is
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derived from the APB clock using a programmable divider.
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Each SGPIO position provides one input and one output, and both are
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exposed as GPIO lines. Position N is described by two consecutive lines:
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line 2 * N is the input and line 2 * N + 1 is the output. Directions are
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fixed by the hardware, so even lines are always inputs and odd lines are
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always outputs.
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Only input lines can generate interrupts. Rising, falling, and both-edge
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interrupts are supported.
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properties:
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compatible:
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const: axiado,ax3005-sgpio
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reg:
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maxItems: 1
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clocks:
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description: APB interface clock
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maxItems: 1
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bus-frequency:
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description: Desired SGPIO shift clock frequency in Hz
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minimum: 1
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gpio-controller: true
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'#gpio-cells':
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const: 2
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interrupt-controller: true
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'#interrupt-cells':
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const: 2
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interrupts:
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maxItems: 1
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ngpios:
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description: |
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Total number of GPIO lines provided by the controller. Each SGPIO
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position wired up on the board contributes one input and one output
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line, so this is twice the number of positions and must be even. It
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may be lower than the maximum supported by the hardware.
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minimum: 2
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maximum: 1024
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multipleOf: 2
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required:
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- compatible
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- reg
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- clocks
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- bus-frequency
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- gpio-controller
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- '#gpio-cells'
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- interrupts
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- interrupt-controller
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- '#interrupt-cells'
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- ngpios
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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gpio@33201c00 {
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compatible = "axiado,ax3005-sgpio";
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reg = <0x33201c00 0x400>;
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clocks = <&apb_clk>;
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bus-frequency = <1000000>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gic500>;
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interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
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ngpios = <256>;
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};
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@ -4439,6 +4439,14 @@ S: Orphan
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F: Documentation/devicetree/bindings/sound/axentia,*
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F: sound/soc/atmel/tse850-pcm5142.c
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AXIADO SGPIO DRIVER
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M: Petar Stepanovic <pstepanovic@axiado.com>
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M: SriNavmani A <srinavmani@axiado.com>
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M: Prasad Bolisetty <pbolisetty@axiado.com>
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L: linux-gpio@vger.kernel.org
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S: Supported
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F: Documentation/devicetree/bindings/gpio/axiado,ax3005-sgpio.yaml
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AXIS ARTPEC ARM64 SoC SUPPORT
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M: Jesper Nilsson <jesper.nilsson@axis.com>
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M: Lars Persson <lars.persson@axis.com>
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