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cxl: update documentation structure in prep for new docs
Restructure the cxl folder to make adding docs per-page cleaner. Signed-off-by: Gregory Price <gourry@gourry.net> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://patch.msgid.link/20250512162134.3596150-2-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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Compute Express Link
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====================
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CXL device configuration has a complex handoff between platform (Hardware,
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BIOS, EFI), OS (early boot, core kernel, driver), and user policy decisions
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that have impacts on each other. The docs here break up configurations steps.
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.. toctree::
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:maxdepth: 1
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memory-devices
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access-coordinates
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:maxdepth: 2
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:caption: Overview
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theory-of-operation
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maturity-map
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.. toctree::
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:maxdepth: 1
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:caption: Linux Kernel Configuration
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linux/access-coordinates
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.. only:: subproject and html
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@ -1,9 +1,9 @@
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.. SPDX-License-Identifier: GPL-2.0
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.. include:: <isonum.txt>
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===================================
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Compute Express Link Memory Devices
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===================================
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===============================================
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Compute Express Link Driver Theory of Operation
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===============================================
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A Compute Express Link Memory Device is a CXL component that implements the
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CXL.mem protocol. It contains some amount of volatile memory, persistent memory,
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@ -14,8 +14,8 @@ that optionally define a device's contribution to an interleaved address
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range across multiple devices underneath a host-bridge or interleaved
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across host-bridges.
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CXL Bus: Theory of Operation
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============================
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The CXL Bus
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===========
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Similar to how a RAID driver takes disk objects and assembles them into a new
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logical device, the CXL subsystem is tasked to take PCIe and ACPI objects and
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assemble them into a CXL.mem decode topology. The need for runtime configuration
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