cxl: update documentation structure in prep for new docs

Restructure the cxl folder to make adding docs per-page cleaner.

Signed-off-by: Gregory Price <gourry@gourry.net>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Link: https://patch.msgid.link/20250512162134.3596150-2-gourry@gourry.net
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
This commit is contained in:
Gregory Price 2025-05-12 12:21:18 -04:00 committed by Dave Jiang
parent b4432656b3
commit a770647294
3 changed files with 19 additions and 9 deletions

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@ -4,12 +4,22 @@
Compute Express Link
====================
CXL device configuration has a complex handoff between platform (Hardware,
BIOS, EFI), OS (early boot, core kernel, driver), and user policy decisions
that have impacts on each other. The docs here break up configurations steps.
.. toctree::
:maxdepth: 1
memory-devices
access-coordinates
:maxdepth: 2
:caption: Overview
theory-of-operation
maturity-map
.. toctree::
:maxdepth: 1
:caption: Linux Kernel Configuration
linux/access-coordinates
.. only:: subproject and html

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@ -1,9 +1,9 @@
.. SPDX-License-Identifier: GPL-2.0
.. include:: <isonum.txt>
===================================
Compute Express Link Memory Devices
===================================
===============================================
Compute Express Link Driver Theory of Operation
===============================================
A Compute Express Link Memory Device is a CXL component that implements the
CXL.mem protocol. It contains some amount of volatile memory, persistent memory,
@ -14,8 +14,8 @@ that optionally define a device's contribution to an interleaved address
range across multiple devices underneath a host-bridge or interleaved
across host-bridges.
CXL Bus: Theory of Operation
============================
The CXL Bus
===========
Similar to how a RAID driver takes disk objects and assembles them into a new
logical device, the CXL subsystem is tasked to take PCIe and ACPI objects and
assemble them into a CXL.mem decode topology. The need for runtime configuration