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Merge branch 'net-add-1600gbps-1-6t-link-mode-support'

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Tariq Toukan says:

====================
net: Add 1600Gbps (1.6T) link mode support

This series by Yael adds 1600Gbps (1.6T) link mode support.
See detailed description by Yael below.
====================

Link: https://patch.msgid.link/1763585297-1243980-1-git-send-email-tariqt@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski 2025-11-20 18:21:32 -08:00
commit a7687b292e
8 changed files with 34 additions and 1 deletions
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9
drivers/net/bonding/bond_3ad.c
View File

@ -76,6 +76,7 @@ enum ad_link_speed_type {
AD_LINK_SPEED_200000MBPS,
AD_LINK_SPEED_400000MBPS,
AD_LINK_SPEED_800000MBPS,
AD_LINK_SPEED_1600000MBPS,
};
/* compare MAC addresses */
@ -300,6 +301,7 @@ static inline int __check_agg_selection_timer(struct port *port)
* %AD_LINK_SPEED_200000MBPS
* %AD_LINK_SPEED_400000MBPS
* %AD_LINK_SPEED_800000MBPS
* %AD_LINK_SPEED_1600000MBPS
*/
static u16 __get_link_speed(struct port *port)
{
@ -379,6 +381,10 @@ static u16 __get_link_speed(struct port *port)
speed = AD_LINK_SPEED_800000MBPS;
break;
case SPEED_1600000:
speed = AD_LINK_SPEED_1600000MBPS;
break;
default:
/* unknown speed value from ethtool. shouldn't happen */
if (slave->speed != SPEED_UNKNOWN)
@ -822,6 +828,9 @@ static u32 __get_agg_bandwidth(struct aggregator *aggregator)
case AD_LINK_SPEED_800000MBPS:
bandwidth = nports * 800000;
break;
case AD_LINK_SPEED_1600000MBPS:
bandwidth = nports * 1600000;
break;
default:
bandwidth = 0; /* to silence the compiler */
}

5
drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c
View File

@ -261,6 +261,11 @@ void mlx5e_build_ptys2ethtool_map(void)
ETHTOOL_LINK_MODE_800000baseDR4_2_Full_BIT,
ETHTOOL_LINK_MODE_800000baseSR4_Full_BIT,
ETHTOOL_LINK_MODE_800000baseVR4_Full_BIT);
MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1600TAUI_8_1600TBASE_CR8_KR8, ext,
ETHTOOL_LINK_MODE_1600000baseCR8_Full_BIT,
ETHTOOL_LINK_MODE_1600000baseKR8_Full_BIT,
ETHTOOL_LINK_MODE_1600000baseDR8_Full_BIT,
ETHTOOL_LINK_MODE_1600000baseDR8_2_Full_BIT);
}
static void mlx5e_ethtool_get_speed_arr(bool ext,

1
drivers/net/ethernet/mellanox/mlx5/core/port.c
View File

@ -1108,6 +1108,7 @@ mlx5e_ext_link_info[MLX5E_EXT_LINK_MODES_NUMBER] = {
[MLX5E_200GAUI_1_200GBASE_CR1_KR1] = {.speed = 200000, .lanes = 1},
[MLX5E_400GAUI_2_400GBASE_CR2_KR2] = {.speed = 400000, .lanes = 2},
[MLX5E_800GAUI_4_800GBASE_CR4_KR4] = {.speed = 800000, .lanes = 4},
[MLX5E_1600TAUI_8_1600TBASE_CR8_KR8] = {.speed = 1600000, .lanes = 8},
};
int mlx5_port_query_eth_proto(struct mlx5_core_dev *dev, u8 port, bool ext,

1
drivers/net/phy/phy-caps.h
View File

@ -29,6 +29,7 @@ enum {
LINK_CAPA_200000FD,
LINK_CAPA_400000FD,
LINK_CAPA_800000FD,
LINK_CAPA_1600000FD,
__LINK_CAPA_MAX,
};

4
drivers/net/phy/phy-core.c
View File

@ -17,7 +17,7 @@
*/
const char *phy_speed_to_str(int speed)
{
BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 121,
BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 125,
"Enum ethtool_link_mode_bit_indices and phylib are out of sync. "
"If a speed or mode has been added please update phy_speed_to_str "
"and the PHY settings array.\n");
@ -55,6 +55,8 @@ const char *phy_speed_to_str(int speed)
return "400Gbps";
case SPEED_800000:
return "800Gbps";
case SPEED_1600000:
return "1600Gbps";
case SPEED_UNKNOWN:
return "Unknown";
default:

2
drivers/net/phy/phy_caps.c
View File

@ -25,6 +25,7 @@ static struct link_capabilities link_caps[__LINK_CAPA_MAX] __ro_after_init = {
{ SPEED_200000, DUPLEX_FULL, {0} }, /* LINK_CAPA_200000FD */
{ SPEED_400000, DUPLEX_FULL, {0} }, /* LINK_CAPA_400000FD */
{ SPEED_800000, DUPLEX_FULL, {0} }, /* LINK_CAPA_800000FD */
{ SPEED_1600000, DUPLEX_FULL, {0} }, /* LINK_CAPA_1600000FD */
};
static int speed_duplex_to_capa(int speed, unsigned int duplex)
@ -52,6 +53,7 @@ static int speed_duplex_to_capa(int speed, unsigned int duplex)
case SPEED_200000: return LINK_CAPA_200000FD;
case SPEED_400000: return LINK_CAPA_400000FD;
case SPEED_800000: return LINK_CAPA_800000FD;
case SPEED_1600000: return LINK_CAPA_1600000FD;
}
return -EINVAL;

5
include/uapi/linux/ethtool.h
View File

@ -2077,6 +2077,10 @@ enum ethtool_link_mode_bit_indices {
ETHTOOL_LINK_MODE_800000baseDR4_2_Full_BIT = 118,
ETHTOOL_LINK_MODE_800000baseSR4_Full_BIT = 119,
ETHTOOL_LINK_MODE_800000baseVR4_Full_BIT = 120,
ETHTOOL_LINK_MODE_1600000baseCR8_Full_BIT = 121,
ETHTOOL_LINK_MODE_1600000baseKR8_Full_BIT = 122,
ETHTOOL_LINK_MODE_1600000baseDR8_Full_BIT = 123,
ETHTOOL_LINK_MODE_1600000baseDR8_2_Full_BIT = 124,
/* must be last entry */
__ETHTOOL_LINK_MODE_MASK_NBITS
@ -2190,6 +2194,7 @@ enum ethtool_link_mode_bit_indices {
#define SPEED_200000 200000
#define SPEED_400000 400000
#define SPEED_800000 800000
#define SPEED_1600000 1600000
#define SPEED_UNKNOWN -1

8
net/ethtool/common.c
View File

@ -233,6 +233,10 @@ const char link_mode_names[][ETH_GSTRING_LEN] = {
__DEFINE_LINK_MODE_NAME(800000, DR4_2, Full),
__DEFINE_LINK_MODE_NAME(800000, SR4, Full),
__DEFINE_LINK_MODE_NAME(800000, VR4, Full),
__DEFINE_LINK_MODE_NAME(1600000, CR8, Full),
__DEFINE_LINK_MODE_NAME(1600000, KR8, Full),
__DEFINE_LINK_MODE_NAME(1600000, DR8, Full),
__DEFINE_LINK_MODE_NAME(1600000, DR8_2, Full),
};
static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS);
@ -422,6 +426,10 @@ const struct link_mode_info link_mode_params[] = {
__DEFINE_LINK_MODE_PARAMS(800000, DR4_2, Full),
__DEFINE_LINK_MODE_PARAMS(800000, SR4, Full),
__DEFINE_LINK_MODE_PARAMS(800000, VR4, Full),
__DEFINE_LINK_MODE_PARAMS(1600000, CR8, Full),
__DEFINE_LINK_MODE_PARAMS(1600000, KR8, Full),
__DEFINE_LINK_MODE_PARAMS(1600000, DR8, Full),
__DEFINE_LINK_MODE_PARAMS(1600000, DR8_2, Full),
};
static_assert(ARRAY_SIZE(link_mode_params) == __ETHTOOL_LINK_MODE_MASK_NBITS);
EXPORT_SYMBOL_GPL(link_mode_params);