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arm64: dts: rockchip: px30: add cif and isp node
Change-Id: Ic6f6780acf315ab46bd1023f449ca2eca97132fe Signed-off-by: Zhang Yunlong <dalon.zhang@rock-chips.com>
This commit is contained in:
Zhang Yunlong
Tao Huang
parent
d35c257365
commit
a75b4427e1
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@ -899,6 +899,65 @@ rk_rga: rk_rga@ff480000 {
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status = "disabled";
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};
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cif: cif@ff490000 {
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compatible = "rockchip,cif";
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reg = <0x0 0xff490000 0x0 0x200>;
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interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>, <&cru PCLK_CIF>, <&cru SCLK_CIF_OUT>;
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clock-names = "aclk_cif0", "hclk_cif0", "pclk_cif", "cif0_out";
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resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, <&cru SRST_CIF_PCLKIN>;
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reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_pclkin";
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pinctrl-names = "cif_pin_all";
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pinctrl-0 = <&dvp_d2d9_m0>;
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status = "disabled";
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};
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vip_mmu: iommu@ff490800{
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compatible = "rockchip,iommu";
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reg = <0x0 0xff490800 0x0 0x100>;
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interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "vip_mmu";
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clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>;
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clock-names = "aclk", "hclk";
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rk_iommu,disable_reset_quirk;
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#iommu-cells = <0>;
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status = "disabled";
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};
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rk_isp: rk_isp@ff4a0000 {
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compatible = "rockchip,px30-isp", "rockchip,isp";
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reg = <0x0 0xff4a0000 0x0 0x4000>;
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru SCLK_ISP>, <&cru SCLK_ISP>,
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<&cru PCLK_ISP>, <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>, <&cru PCLK_MIPICSIPHY>;
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clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe",
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"pclkin_isp", "clk_cif_pll", "clk_cif_out", "pclk_dphyrx";
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resets = <&cru SRST_ISP>, <&cru SRST_MIPICSIPHY_P>;
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reset-names = "rst_isp", "rst_mipicsiphy";
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pinctrl-names = "default";
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pinctrl-0 = <&cif_clkout_m0>;
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rockchip,isp,mipiphy = <1>;
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rockchip,isp,cifphy = <1>;
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rockchip,isp,csiphy,reg = <0xff2f0000 0x4000>;
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rockchip,grf = <&grf>;
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rockchip,cru = <&cru>;
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rockchip,isp,iommu-enable = <1>;
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iommus = <&isp_mmu>;
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status = "disabled";
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};
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isp_mmu: iommu@ff4a8000 {
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compatible = "rockchip,iommu";
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reg = <0x0 0xff4a8000 0x0 0x100>;
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "isp_mmu";
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clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
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clock-names = "aclk", "hclk";
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rk_iommu,disable_reset_quirk;
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#iommu-cells = <0>;
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status = "disabled";
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};
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qos_gmac: qos@ff518000 {
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compatible = "syscon";
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reg = <0x0 0xff518000 0x0 0x20>;
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@ -1978,4 +2037,72 @@ rmii_pins: rmii-pins {
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};
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};
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cif-m0 {
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cif_clkout_m0: cif-clkout-m0 {
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rockchip,pins = <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;/* cif_clkout */
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};
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dvp_d2d9_m0: dvp-d2d9-m0 {
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rockchip,pins =
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<2 RK_PA0 RK_FUNC_1 &pcfg_pull_none>,/* cif_data2 */
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<2 RK_PA1 RK_FUNC_1 &pcfg_pull_none>,/* cif_data3 */
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<2 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,/* cif_data4 */
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<2 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,/* cif_data5 */
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<2 RK_PA4 RK_FUNC_1 &pcfg_pull_none>,/* cif_data6 */
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<2 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,/* cif_data7 */
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<2 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,/* cif_data8 */
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<2 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data9 */
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<2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,/* cif_sync */
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<2 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,/* cif_href */
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<2 RK_PB2 RK_FUNC_1 &pcfg_pull_none>,/* cif_clkin */
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<2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;/* cif_clkout */
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};
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dvp_d0d1_m0: dvp-d0d1-m0 {
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rockchip,pins =
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<2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,/* cif_data0 */
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<2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>;/* cif_data1 */
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};
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dvp_d10d11_m0:d10-d11-m0 {
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rockchip,pins =
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<2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data10 */
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<2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>;/* cif_data11 */
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};
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};
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cif-m1 {
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cif_clkout_m1: cif-clkout-m1 {
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rockchip,pins = <3 RK_PD0 RK_FUNC_3 &pcfg_pull_none>;/* cif_clkout */
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};
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dvp_d2d9_m1: dvp-d2d9-m1 {
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rockchip,pins =
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<3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,/* cif_data2 */
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<3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,/* cif_data3 */
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<3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data4 */
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<3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,/* cif_data5 */
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<3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,/* cif_data6 */
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<3 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,/* cif_data7 */
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<3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,/* cif_data8 */
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<3 RK_PB7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data9 */
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<3 RK_PD1 RK_FUNC_3 &pcfg_pull_none>,/* cif_sync */
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<3 RK_PD2 RK_FUNC_2 &pcfg_pull_none>,/* cif_href */
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<3 RK_PD3 RK_FUNC_2 &pcfg_pull_none>,/* cif_clkin */
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<3 RK_PD0 RK_FUNC_3 &pcfg_pull_none>;/* cif_clkout */
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};
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dvp_d0d1_m1: dvp-d0d1-m1 {
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rockchip,pins =
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<3 RK_PA1 RK_FUNC_3 &pcfg_pull_none>,/* cif_data0 */
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<3 RK_PA2 RK_FUNC_3 &pcfg_pull_none>;/* cif_data1 */
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};
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dvp_d10d11_m1:d10-d11-m1 {
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rockchip,pins =
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<3 RK_PC6 RK_FUNC_3 &pcfg_pull_none>,/* cif_data10 */
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<3 RK_PC7 RK_FUNC_3 &pcfg_pull_none>;/* cif_data11 */
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};
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};
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isp {
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isp_prelight: isp-prelight {
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rockchip,pins = <3 RK_PD1 RK_FUNC_4 &pcfg_pull_none>;/* ISP_PRELIGHTTRIG */
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};
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};
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};
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