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mfd: cs42l43: Add support for the B variant
Introducing CS42L43B codec, a variant of CS42L43 which can be driven by the same driver. Changes in CS42L43 driver specific for CS42L43B: - Decimator 1 and 2 are dedicated to ADC, can't be selected for PDM - Decimators 3 and 4 are connected to PDM1 - Added Decimator 5 and 6 for PDM2 - Supports SoundWire Clock Gearing - Updated ROM requiring no patching - Reduced RAM space - Each ISRC has 4 decimators now Signed-off-by: Maciej Strozek <mstrozek@opensource.cirrus.com> Acked-by: Lee Jones <lee@kernel.org> Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://patch.msgid.link/20260306152829.3130530-4-mstrozek@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Maciej Strozek
Mark Brown
parent
301db52317
commit
a6fe20d67d
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@ -47,6 +47,7 @@ static int cs42l43_i2c_probe(struct i2c_client *i2c)
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cs42l43->irq = i2c->irq;
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/* A device on an I2C is always attached by definition. */
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cs42l43->attached = true;
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cs42l43->variant_id = (long)device_get_match_data(cs42l43->dev);
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cs42l43->regmap = devm_regmap_init_i2c(i2c, &cs42l43_i2c_regmap);
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if (IS_ERR(cs42l43->regmap))
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@ -58,7 +59,8 @@ static int cs42l43_i2c_probe(struct i2c_client *i2c)
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#if IS_ENABLED(CONFIG_OF)
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static const struct of_device_id cs42l43_of_match[] = {
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{ .compatible = "cirrus,cs42l43", },
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{ .compatible = "cirrus,cs42l43", .data = (void *)CS42L43_DEVID_VAL },
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{ .compatible = "cirrus,cs42l43b", .data = (void *)CS42L43B_DEVID_VAL },
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{}
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};
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MODULE_DEVICE_TABLE(of, cs42l43_of_match);
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@ -66,7 +68,8 @@ MODULE_DEVICE_TABLE(of, cs42l43_of_match);
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#if IS_ENABLED(CONFIG_ACPI)
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static const struct acpi_device_id cs42l43_acpi_match[] = {
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{ "CSC4243", 0 },
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{ "CSC4243", CS42L43_DEVID_VAL },
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{ "CSC2A3B", CS42L43B_DEVID_VAL },
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{}
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};
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MODULE_DEVICE_TABLE(acpi, cs42l43_acpi_match);
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@ -178,6 +178,7 @@ static int cs42l43_sdw_probe(struct sdw_slave *sdw, const struct sdw_device_id *
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cs42l43->dev = dev;
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cs42l43->sdw = sdw;
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cs42l43->variant_id = (long)id->driver_data;
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cs42l43->regmap = devm_regmap_init_sdw(sdw, &cs42l43_sdw_regmap);
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if (IS_ERR(cs42l43->regmap))
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@ -188,7 +189,8 @@ static int cs42l43_sdw_probe(struct sdw_slave *sdw, const struct sdw_device_id *
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}
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static const struct sdw_device_id cs42l43_sdw_id[] = {
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SDW_SLAVE_ENTRY(0x01FA, 0x4243, 0),
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SDW_SLAVE_ENTRY(0x01FA, 0x4243, (void *) CS42L43_DEVID_VAL),
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SDW_SLAVE_ENTRY(0x01FA, 0x2A3B, (void *) CS42L43B_DEVID_VAL),
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{}
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};
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MODULE_DEVICE_TABLE(sdw, cs42l43_sdw_id);
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@ -115,9 +115,14 @@ const struct reg_default cs42l43_reg_default[CS42L43_N_DEFAULTS] = {
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{ CS42L43_DECIM_HPF_WNF_CTRL2, 0x00000001 },
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{ CS42L43_DECIM_HPF_WNF_CTRL3, 0x00000001 },
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{ CS42L43_DECIM_HPF_WNF_CTRL4, 0x00000001 },
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{ CS42L43B_DECIM_HPF_WNF_CTRL5, 0x00000001 },
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{ CS42L43B_DECIM_HPF_WNF_CTRL6, 0x00000001 },
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{ CS42L43_DMIC_PDM_CTRL, 0x00000000 },
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{ CS42L43_DECIM_VOL_CTRL_CH1_CH2, 0x20122012 },
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{ CS42L43_DECIM_VOL_CTRL_CH3_CH4, 0x20122012 },
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{ CS42L43B_DECIM_VOL_CTRL_CH1_CH2, 0x20122012 },
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{ CS42L43B_DECIM_VOL_CTRL_CH3_CH4, 0x20122012 },
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{ CS42L43B_DECIM_VOL_CTRL_CH5_CH6, 0x20122012 },
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{ CS42L43_INTP_VOLUME_CTRL1, 0x00000180 },
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{ CS42L43_INTP_VOLUME_CTRL2, 0x00000180 },
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{ CS42L43_AMP1_2_VOL_RAMP, 0x00000022 },
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@ -155,8 +160,12 @@ const struct reg_default cs42l43_reg_default[CS42L43_N_DEFAULTS] = {
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{ CS42L43_SWIRE_DP2_CH2_INPUT, 0x00000000 },
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{ CS42L43_SWIRE_DP3_CH1_INPUT, 0x00000000 },
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{ CS42L43_SWIRE_DP3_CH2_INPUT, 0x00000000 },
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{ CS42L43B_SWIRE_DP3_CH3_INPUT, 0x00000000 },
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{ CS42L43B_SWIRE_DP3_CH4_INPUT, 0x00000000 },
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{ CS42L43_SWIRE_DP4_CH1_INPUT, 0x00000000 },
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{ CS42L43_SWIRE_DP4_CH2_INPUT, 0x00000000 },
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{ CS42L43B_SWIRE_DP4_CH3_INPUT, 0x00000000 },
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{ CS42L43B_SWIRE_DP4_CH4_INPUT, 0x00000000 },
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{ CS42L43_ASRC_INT1_INPUT1, 0x00000000 },
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{ CS42L43_ASRC_INT2_INPUT1, 0x00000000 },
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{ CS42L43_ASRC_INT3_INPUT1, 0x00000000 },
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@ -169,10 +178,14 @@ const struct reg_default cs42l43_reg_default[CS42L43_N_DEFAULTS] = {
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{ CS42L43_ISRC1INT2_INPUT1, 0x00000000 },
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{ CS42L43_ISRC1DEC1_INPUT1, 0x00000000 },
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{ CS42L43_ISRC1DEC2_INPUT1, 0x00000000 },
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{ CS42L43B_ISRC1DEC3_INPUT1, 0x00000000 },
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{ CS42L43B_ISRC1DEC4_INPUT1, 0x00000000 },
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{ CS42L43_ISRC2INT1_INPUT1, 0x00000000 },
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{ CS42L43_ISRC2INT2_INPUT1, 0x00000000 },
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{ CS42L43_ISRC2DEC1_INPUT1, 0x00000000 },
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{ CS42L43_ISRC2DEC2_INPUT1, 0x00000000 },
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{ CS42L43B_ISRC2DEC3_INPUT1, 0x00000000 },
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{ CS42L43B_ISRC2DEC4_INPUT1, 0x00000000 },
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{ CS42L43_EQ1MIX_INPUT1, 0x00800000 },
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{ CS42L43_EQ1MIX_INPUT2, 0x00800000 },
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{ CS42L43_EQ1MIX_INPUT3, 0x00800000 },
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@ -269,6 +282,8 @@ EXPORT_SYMBOL_NS_GPL(cs42l43_reg_default, "MFD_CS42L43");
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bool cs42l43_readable_register(struct device *dev, unsigned int reg)
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{
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struct cs42l43 *cs42l43 = dev_get_drvdata(dev);
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switch (reg) {
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case CS42L43_DEVID:
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case CS42L43_REVID:
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@ -292,7 +307,6 @@ bool cs42l43_readable_register(struct device *dev, unsigned int reg)
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case CS42L43_ADC_B_CTRL1 ... CS42L43_ADC_B_CTRL2:
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case CS42L43_DECIM_HPF_WNF_CTRL1 ... CS42L43_DECIM_HPF_WNF_CTRL4:
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case CS42L43_DMIC_PDM_CTRL:
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case CS42L43_DECIM_VOL_CTRL_CH1_CH2 ... CS42L43_DECIM_VOL_CTRL_CH3_CH4:
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case CS42L43_INTP_VOLUME_CTRL1 ... CS42L43_INTP_VOLUME_CTRL2:
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case CS42L43_AMP1_2_VOL_RAMP:
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case CS42L43_ASP_CTRL:
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@ -387,8 +401,16 @@ bool cs42l43_readable_register(struct device *dev, unsigned int reg)
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case CS42L43_BOOT_CONTROL:
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case CS42L43_BLOCK_EN:
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case CS42L43_SHUTTER_CONTROL:
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case CS42L43_MCU_SW_REV ... CS42L43_MCU_RAM_MAX:
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return true;
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case CS42L43B_MCU_SW_REV ... CS42L43B_MCU_RAM_MAX:
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return true; // registers present on all variants
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case CS42L43_MCU_SW_REV ... CS42L43B_MCU_SW_REV - 1:
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case CS42L43B_MCU_RAM_MAX + 1 ... CS42L43_MCU_RAM_MAX:
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case CS42L43_DECIM_VOL_CTRL_CH1_CH2 ... CS42L43_DECIM_VOL_CTRL_CH3_CH4:
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return cs42l43->variant_id == CS42L43_DEVID_VAL; // regs only in CS42L43 variant
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case CS42L43B_DECIM_VOL_CTRL_CH1_CH2 ... CS42L43B_DECIM_HPF_WNF_CTRL6:
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case CS42L43B_SWIRE_DP3_CH3_INPUT ... CS42L43B_SWIRE_DP4_CH4_INPUT:
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case CS42L43B_ISRC1DEC3_INPUT1 ... CS42L43B_ISRC2DEC4_INPUT1:
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return cs42l43->variant_id == CS42L43B_DEVID_VAL; // regs only in CS42L43B variant
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default:
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return false;
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}
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@ -597,15 +619,27 @@ static int cs42l43_wait_for_attach(struct cs42l43 *cs42l43)
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static int cs42l43_mcu_stage_2_3(struct cs42l43 *cs42l43, bool shadow)
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{
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unsigned int need_reg = CS42L43_NEED_CONFIGS;
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unsigned int boot_reg;
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unsigned int val;
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int ret;
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if (shadow)
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need_reg = CS42L43_FW_SH_BOOT_CFG_NEED_CONFIGS;
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switch (cs42l43->variant_id) {
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case CS42L43_DEVID_VAL:
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if (shadow)
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need_reg = CS42L43_FW_SH_BOOT_CFG_NEED_CONFIGS;
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boot_reg = CS42L43_BOOT_STATUS;
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break;
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case CS42L43B_DEVID_VAL:
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need_reg = CS42L43B_NEED_CONFIGS;
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boot_reg = CS42L43B_BOOT_STATUS;
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break;
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default:
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return -EINVAL;
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}
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regmap_write(cs42l43->regmap, need_reg, 0);
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ret = regmap_read_poll_timeout(cs42l43->regmap, CS42L43_BOOT_STATUS,
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ret = regmap_read_poll_timeout(cs42l43->regmap, boot_reg,
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val, (val == CS42L43_MCU_BOOT_STAGE3),
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CS42L43_MCU_POLL_US, CS42L43_MCU_CMD_TIMEOUT_US);
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if (ret) {
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@ -644,13 +678,25 @@ static int cs42l43_mcu_stage_3_2(struct cs42l43 *cs42l43)
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*/
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static int cs42l43_mcu_disable(struct cs42l43 *cs42l43)
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{
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unsigned int val;
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unsigned int val, cfg_reg, ctrl_reg;
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int ret;
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regmap_write(cs42l43->regmap, CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_REG,
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CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_DISABLE_VAL);
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regmap_write(cs42l43->regmap, CS42L43_FW_MISSION_CTRL_MM_CTRL_SELECTION,
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CS42L43_FW_MM_CTRL_MCU_SEL_MASK);
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switch (cs42l43->variant_id) {
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case CS42L43_DEVID_VAL:
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cfg_reg = CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_REG;
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ctrl_reg = CS42L43_FW_MISSION_CTRL_MM_CTRL_SELECTION;
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break;
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case CS42L43B_DEVID_VAL:
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cfg_reg = CS42L43B_FW_MISSION_CTRL_MM_MCU_CFG_REG;
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ctrl_reg = CS42L43B_FW_MISSION_CTRL_MM_CTRL_SELECTION;
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break;
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default:
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return -EINVAL;
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}
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regmap_write(cs42l43->regmap, cfg_reg, CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_DISABLE_VAL);
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regmap_write(cs42l43->regmap, ctrl_reg, CS42L43_FW_MM_CTRL_MCU_SEL_MASK);
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regmap_write(cs42l43->regmap, CS42L43_MCU_SW_INTERRUPT, CS42L43_CONTROL_IND_MASK);
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regmap_write(cs42l43->regmap, CS42L43_MCU_SW_INTERRUPT, 0);
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@ -740,18 +786,32 @@ static int cs42l43_mcu_update_step(struct cs42l43 *cs42l43)
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{
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unsigned int mcu_rev, bios_rev, boot_status, secure_cfg;
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bool patched, shadow;
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int boot_status_reg, mcu_sw_rev_reg;
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int ret;
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switch (cs42l43->variant_id) {
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case CS42L43_DEVID_VAL:
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boot_status_reg = CS42L43_BOOT_STATUS;
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mcu_sw_rev_reg = CS42L43_MCU_SW_REV;
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break;
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case CS42L43B_DEVID_VAL:
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boot_status_reg = CS42L43B_BOOT_STATUS;
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mcu_sw_rev_reg = CS42L43B_MCU_SW_REV;
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break;
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default:
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return -EINVAL;
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}
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/* Clear any stale software interrupt bits. */
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regmap_read(cs42l43->regmap, CS42L43_SOFT_INT, &mcu_rev);
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ret = regmap_read(cs42l43->regmap, CS42L43_BOOT_STATUS, &boot_status);
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ret = regmap_read(cs42l43->regmap, boot_status_reg, &boot_status);
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if (ret) {
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dev_err(cs42l43->dev, "Failed to read boot status: %d\n", ret);
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return ret;
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}
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ret = regmap_read(cs42l43->regmap, CS42L43_MCU_SW_REV, &mcu_rev);
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ret = regmap_read(cs42l43->regmap, mcu_sw_rev_reg, &mcu_rev);
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if (ret) {
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dev_err(cs42l43->dev, "Failed to read firmware revision: %d\n", ret);
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return ret;
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@ -918,6 +978,13 @@ static void cs42l43_boot_work(struct work_struct *work)
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switch (devid) {
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case CS42L43_DEVID_VAL:
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case CS42L43B_DEVID_VAL:
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if (devid != cs42l43->variant_id) {
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dev_err(cs42l43->dev,
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"Device ID (0x%06x) does not match variant ID (0x%06lx)\n",
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devid, cs42l43->variant_id);
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goto err;
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}
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break;
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default:
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dev_err(cs42l43->dev, "Unrecognised devid: 0x%06x\n", devid);
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@ -9,7 +9,7 @@
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#ifndef CS42L43_CORE_INT_H
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#define CS42L43_CORE_INT_H
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#define CS42L43_N_DEFAULTS 176
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#define CS42L43_N_DEFAULTS 189
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struct dev_pm_ops;
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struct device;
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@ -1181,4 +1181,80 @@
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/* CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_REG */
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#define CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_DISABLE_VAL 0xF05AA50F
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/* CS42L43B VARIANT REGISTERS */
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#define CS42L43B_DEVID_VAL 0x0042A43B
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#define CS42L43B_DECIM_VOL_CTRL_CH1_CH2 0x00008280
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#define CS42L43B_DECIM_VOL_CTRL_CH3_CH4 0x00008284
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#define CS42L43B_DECIM_VOL_CTRL_CH5_CH6 0x00008290
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#define CS42L43B_DECIM_VOL_CTRL_UPDATE 0x0000829C
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#define CS42L43B_DECIM_HPF_WNF_CTRL5 0x000082A0
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#define CS42L43B_DECIM_HPF_WNF_CTRL6 0x000082A4
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#define CS42L43B_SWIRE_DP3_CH3_INPUT 0x0000C320
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#define CS42L43B_SWIRE_DP3_CH4_INPUT 0x0000C330
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#define CS42L43B_SWIRE_DP4_CH3_INPUT 0x0000C340
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#define CS42L43B_SWIRE_DP4_CH4_INPUT 0x0000C350
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#define CS42L43B_ISRC1DEC3_INPUT1 0x0000C780
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#define CS42L43B_ISRC1DEC4_INPUT1 0x0000C790
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#define CS42L43B_ISRC2DEC3_INPUT1 0x0000C7A0
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#define CS42L43B_ISRC2DEC4_INPUT1 0x0000C7B0
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#define CS42L43B_FW_MISSION_CTRL_NEED_CONFIGS 0x00117E00
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#define CS42L43B_FW_MISSION_CTRL_HAVE_CONFIGS 0x00117E04
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#define CS42L43B_FW_MISSION_CTRL_PATCH_START_ADDR_REG 0x00117E08
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#define CS42L43B_FW_MISSION_CTRL_MM_CTRL_SELECTION 0x00117E0C
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#define CS42L43B_FW_MISSION_CTRL_MM_MCU_CFG_REG 0x00117E10
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#define CS42L43B_MCU_SW_REV 0x00117314
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#define CS42L43B_PATCH_START_ADDR 0x00117318
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#define CS42L43B_CONFIG_SELECTION 0x0011731C
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#define CS42L43B_NEED_CONFIGS 0x00117320
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#define CS42L43B_BOOT_STATUS 0x00117330
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#define CS42L43B_FW_MISSION_CTRL_NEED_CONFIGS 0x00117E00
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#define CS42L43B_FW_MISSION_CTRL_HAVE_CONFIGS 0x00117E04
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#define CS42L43B_FW_MISSION_CTRL_PATCH_START_ADDR_REG 0x00117E08
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#define CS42L43B_FW_MISSION_CTRL_MM_CTRL_SELECTION 0x00117E0C
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#define CS42L43B_FW_MISSION_CTRL_MM_MCU_CFG_REG 0x00117E10
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#define CS42L43B_MCU_RAM_MAX 0x00117FFF
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/* CS42L43B_DECIM_DECIM_VOL_CTRL_CH5_CH6 */
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#define CS42L43B_DECIM6_MUTE_MASK 0x80000000
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#define CS42L43B_DECIM6_MUTE_SHIFT 31
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#define CS42L43B_DECIM6_VOL_MASK 0x3FC00000
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#define CS42L43B_DECIM6_VOL_SHIFT 22
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#define CS42L43B_DECIM6_PATH1_VOL_FALL_RATE_MASK 0x00380000
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#define CS42L43B_DECIM6_PATH1_VOL_FALL_RATE_SHIFT 19
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#define CS42L43B_DECIM6_PATH1_VOL_RISE_RATE_MASK 0x00070000
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#define CS42L43B_DECIM6_PATH1_VOL_RISE_RATE_SHIFT 16
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#define CS42L43B_DECIM5_MUTE_MASK 0x00008000
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#define CS42L43B_DECIM5_MUTE_SHIFT 15
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#define CS42L43B_DECIM5_VOL_MASK 0x00003FC0
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#define CS42L43B_DECIM5_VOL_SHIFT 6
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#define CS42L43B_DECIM5_PATH1_VOL_FALL_RATE_MASK 0x00000038
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#define CS42L43B_DECIM5_PATH1_VOL_FALL_RATE_SHIFT 3
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#define CS42L43B_DECIM5_PATH1_VOL_RISE_RATE_MASK 0x00000007
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#define CS42L43B_DECIM5_PATH1_VOL_RISE_RATE_SHIFT 0
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/* CS42L43B_DECIM_VOL_CTRL_UPDATE */
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#define CS42L43B_DECIM6_PATH1_VOL_TRIG_MASK 0x00000800
|
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#define CS42L43B_DECIM6_PATH1_VOL_TRIG_SHIFT 11
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#define CS42L43B_DECIM5_PATH1_VOL_TRIG_MASK 0x00000100
|
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#define CS42L43B_DECIM5_PATH1_VOL_TRIG_SHIFT 8
|
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#define CS42L43B_DECIM4_VOL_UPDATE_MASK 0x00000020
|
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#define CS42L43B_DECIM4_VOL_UPDATE_SHIFT 5
|
||||
|
||||
/* CS42L43_ISRC1_CTRL..CS42L43_ISRC2_CTRL */
|
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#define CS42L43B_ISRC_DEC4_EN_MASK 0x00000008
|
||||
#define CS42L43B_ISRC_DEC4_EN_SHIFT 3
|
||||
#define CS42L43B_ISRC_DEC4_EN_WIDTH 1
|
||||
#define CS42L43B_ISRC_DEC3_EN_MASK 0x00000004
|
||||
#define CS42L43B_ISRC_DEC3_EN_SHIFT 2
|
||||
#define CS42L43B_ISRC_DEC3_EN_WIDTH 1
|
||||
|
||||
#endif /* CS42L43_CORE_REGS_H */
|
||||
|
|
|
|||
|
|
@ -98,6 +98,7 @@ struct cs42l43 {
|
|||
bool sdw_pll_active;
|
||||
bool attached;
|
||||
bool hw_lock;
|
||||
long variant_id;
|
||||
};
|
||||
|
||||
#endif /* CS42L43_CORE_EXT_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user