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drm/amd/display: Check DCCG_AUDIO_DTO2 register mask exist

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[Why&How]
Check DCCG_AUDIO_DTO2 register mask exist before access.
Also,  add a existing DIO_CLOCK_control register for later use.

Reviewed-by: Roman Li <roman.li@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Charlene Liu 2025-10-27 21:40:21 -04:00 committed by Alex Deucher
parent 8ffa289f90
commit a6ec172632
2 changed files with 4 additions and 2 deletions
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3
drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
View File

@ -1143,7 +1143,8 @@ void dce_aud_wall_dto_setup(
REG_UPDATE(DCCG_AUDIO_DTO1_PHASE,
DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase);
REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
if (aud->masks->DCCG_AUDIO_DTO2_USE_512FBR_DTO)
REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1);
}

3
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
View File

@ -227,7 +227,8 @@ void dcn401_prepare_mcache_programming(struct dc *dc, struct dc_state *context);
#define LE_DCN401_REG_LIST_RI(id) \
LE_DCN3_REG_LIST_RI(id), \
SRI_ARR(DP_DPHY_INTERNAL_CTRL, DP, id), \
SRI_ARR(DIG_BE_CLK_CNTL, DIG, id)
SRI_ARR(DIG_BE_CLK_CNTL, DIG, id),\
SR_ARR(DIO_CLK_CNTL, id)
/* DPP */
#define DPP_REG_LIST_DCN401_COMMON_RI(id) \