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drm/msm/a6xx: Enable IFPC on Adreno X1-85

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Add the IFPC restore register list and enable IFPC support on Adreno
X1-85 gpu.

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/673384/
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
This commit is contained in:
Akhil P Oommen 2025-09-08 13:57:08 +05:30 committed by Rob Clark
parent 870d72d000
commit a6a0157cc6
3 changed files with 79 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

68
drivers/gpu/drm/msm/adreno/a6xx_catalog.c
View File

@ -1353,6 +1353,69 @@ static const uint32_t a7xx_pwrup_reglist_regs[] = {
DECLARE_ADRENO_REGLIST_LIST(a7xx_pwrup_reglist); DECLARE_ADRENO_REGLIST_LIST(a7xx_pwrup_reglist);
/* Applicable for X185, A750 */
static const u32 a750_ifpc_reglist_regs[] = {
REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0,
REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1,
REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2,
REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3,
REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4,
REG_A6XX_TPL1_NC_MODE_CNTL,
REG_A6XX_SP_NC_MODE_CNTL,
REG_A6XX_CP_DBG_ECO_CNTL,
REG_A6XX_CP_PROTECT_CNTL,
REG_A6XX_CP_PROTECT(0),
REG_A6XX_CP_PROTECT(1),
REG_A6XX_CP_PROTECT(2),
REG_A6XX_CP_PROTECT(3),
REG_A6XX_CP_PROTECT(4),
REG_A6XX_CP_PROTECT(5),
REG_A6XX_CP_PROTECT(6),
REG_A6XX_CP_PROTECT(7),
REG_A6XX_CP_PROTECT(8),
REG_A6XX_CP_PROTECT(9),
REG_A6XX_CP_PROTECT(10),
REG_A6XX_CP_PROTECT(11),
REG_A6XX_CP_PROTECT(12),
REG_A6XX_CP_PROTECT(13),
REG_A6XX_CP_PROTECT(14),
REG_A6XX_CP_PROTECT(15),
REG_A6XX_CP_PROTECT(16),
REG_A6XX_CP_PROTECT(17),
REG_A6XX_CP_PROTECT(18),
REG_A6XX_CP_PROTECT(19),
REG_A6XX_CP_PROTECT(20),
REG_A6XX_CP_PROTECT(21),
REG_A6XX_CP_PROTECT(22),
REG_A6XX_CP_PROTECT(23),
REG_A6XX_CP_PROTECT(24),
REG_A6XX_CP_PROTECT(25),
REG_A6XX_CP_PROTECT(26),
REG_A6XX_CP_PROTECT(27),
REG_A6XX_CP_PROTECT(28),
REG_A6XX_CP_PROTECT(29),
REG_A6XX_CP_PROTECT(30),
REG_A6XX_CP_PROTECT(31),
REG_A6XX_CP_PROTECT(32),
REG_A6XX_CP_PROTECT(33),
REG_A6XX_CP_PROTECT(34),
REG_A6XX_CP_PROTECT(35),
REG_A6XX_CP_PROTECT(36),
REG_A6XX_CP_PROTECT(37),
REG_A6XX_CP_PROTECT(38),
REG_A6XX_CP_PROTECT(39),
REG_A6XX_CP_PROTECT(40),
REG_A6XX_CP_PROTECT(41),
REG_A6XX_CP_PROTECT(42),
REG_A6XX_CP_PROTECT(43),
REG_A6XX_CP_PROTECT(44),
REG_A6XX_CP_PROTECT(45),
REG_A6XX_CP_PROTECT(46),
REG_A6XX_CP_PROTECT(47),
};
DECLARE_ADRENO_REGLIST_LIST(a750_ifpc_reglist);
static const struct adreno_info a7xx_gpus[] = { static const struct adreno_info a7xx_gpus[] = {
{ {
.chip_ids = ADRENO_CHIP_IDS(0x07000200), .chip_ids = ADRENO_CHIP_IDS(0x07000200),
@ -1442,12 +1505,14 @@ static const struct adreno_info a7xx_gpus[] = {
.inactive_period = DRM_MSM_INACTIVE_PERIOD, .inactive_period = DRM_MSM_INACTIVE_PERIOD,
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
ADRENO_QUIRK_HAS_HW_APRIV | ADRENO_QUIRK_HAS_HW_APRIV |
ADRENO_QUIRK_PREEMPTION, ADRENO_QUIRK_PREEMPTION |
ADRENO_QUIRK_IFPC,
.init = a6xx_gpu_init, .init = a6xx_gpu_init,
.a6xx = &(const struct a6xx_info) { .a6xx = &(const struct a6xx_info) {
.hwcg = a740_hwcg, .hwcg = a740_hwcg,
.protect = &a730_protect, .protect = &a730_protect,
.pwrup_reglist = &a7xx_pwrup_reglist, .pwrup_reglist = &a7xx_pwrup_reglist,
.ifpc_reglist = &a750_ifpc_reglist,
.gmu_chipid = 0x7050001, .gmu_chipid = 0x7050001,
.gmu_cgc_mode = 0x00020202, .gmu_cgc_mode = 0x00020202,
.bcms = (const struct a6xx_bcm[]) { .bcms = (const struct a6xx_bcm[]) {
@ -1487,6 +1552,7 @@ static const struct adreno_info a7xx_gpus[] = {
.a6xx = &(const struct a6xx_info) { .a6xx = &(const struct a6xx_info) {
.protect = &a730_protect, .protect = &a730_protect,
.pwrup_reglist = &a7xx_pwrup_reglist, .pwrup_reglist = &a7xx_pwrup_reglist,
.ifpc_reglist = &a750_ifpc_reglist,
.gmu_chipid = 0x7090100, .gmu_chipid = 0x7090100,
.gmu_cgc_mode = 0x00020202, .gmu_cgc_mode = 0x00020202,
.bcms = (const struct a6xx_bcm[]) { .bcms = (const struct a6xx_bcm[]) {

15
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
View File

@ -828,11 +828,10 @@ static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu)
u32 *dest = (u32 *)&lock->regs[0]; u32 *dest = (u32 *)&lock->regs[0];
int i; int i;
reglist = adreno_gpu->info->a6xx->pwrup_reglist;
lock->gpu_req = lock->cpu_req = lock->turn = 0; lock->gpu_req = lock->cpu_req = lock->turn = 0;
lock->ifpc_list_len = 0;
lock->preemption_list_len = reglist->count; reglist = adreno_gpu->info->a6xx->ifpc_reglist;
lock->ifpc_list_len = reglist->count;
/* /*
* For each entry in each of the lists, write the offset and the current * For each entry in each of the lists, write the offset and the current
@ -843,6 +842,14 @@ static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu)
*dest++ = gpu_read(gpu, reglist->regs[i]); *dest++ = gpu_read(gpu, reglist->regs[i]);
} }
reglist = adreno_gpu->info->a6xx->pwrup_reglist;
lock->preemption_list_len = reglist->count;
for (i = 0; i < reglist->count; i++) {
*dest++ = reglist->regs[i];
*dest++ = gpu_read(gpu, reglist->regs[i]);
}
/* /*
* The overall register list is composed of * The overall register list is composed of
* 1. Static IFPC-only registers * 1. Static IFPC-only registers

1
drivers/gpu/drm/msm/adreno/a6xx_gpu.h
View File

@ -45,6 +45,7 @@ struct a6xx_info {
const struct adreno_reglist *hwcg; const struct adreno_reglist *hwcg;
const struct adreno_protect *protect; const struct adreno_protect *protect;
const struct adreno_reglist_list *pwrup_reglist; const struct adreno_reglist_list *pwrup_reglist;
const struct adreno_reglist_list *ifpc_reglist;
u32 gmu_chipid; u32 gmu_chipid;
u32 gmu_cgc_mode; u32 gmu_cgc_mode;
u32 prim_fifo_threshold; u32 prim_fifo_threshold;