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drm/amd: Enable SMU 15_0_0 firmware headers
Add SMU 15_0_0 firmware headers v2: squash in updates (Alex) Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Pratik Vishwakarma
Alex Deucher
parent
52cd9bc47f
commit
a68654bfb7
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@ -0,0 +1,231 @@
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/*
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* Copyright 2025 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
|
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* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
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* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef SMU15_DRIVER_IF_V15_0_0_H
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#define SMU15_DRIVER_IF_V15_0_0_H
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typedef struct {
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int32_t value;
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uint32_t numFractionalBits;
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} FloatInIntFormat_t;
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typedef enum {
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DSPCLK_DCFCLK = 0,
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DSPCLK_DISPCLK,
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DSPCLK_PIXCLK,
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DSPCLK_PHYCLK,
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DSPCLK_COUNT,
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} DSPCLK_e;
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typedef struct {
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uint16_t Freq; // in MHz
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uint16_t Vid; // min voltage in SVI3 VID
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} DisplayClockTable_t;
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typedef struct {
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uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
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uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
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uint16_t MinMclk;
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uint16_t MaxMclk;
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uint8_t WmSetting;
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uint8_t WmType; // Used for normal pstate change or memory retraining
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uint8_t Padding[2];
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} WatermarkRowGeneric_t;
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#define NUM_WM_RANGES 4
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#define WM_PSTATE_CHG 0
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#define WM_RETRAINING 1
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typedef enum {
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WM_SOCCLK = 0,
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WM_DCFCLK,
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WM_COUNT,
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} WM_CLOCK_e;
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typedef struct {
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// Watermarks
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WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
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uint32_t MmHubPadding[7]; // SMU internal use
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} Watermarks_t;
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typedef enum {
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CUSTOM_DPM_SETTING_GFXCLK,
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CUSTOM_DPM_SETTING_CCLK,
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CUSTOM_DPM_SETTING_FCLK_CCX,
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CUSTOM_DPM_SETTING_FCLK_GFX,
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CUSTOM_DPM_SETTING_FCLK_STALLS,
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CUSTOM_DPM_SETTING_LCLK,
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CUSTOM_DPM_SETTING_COUNT,
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} CUSTOM_DPM_SETTING_e;
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typedef struct {
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uint8_t ActiveHystLimit;
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uint8_t IdleHystLimit;
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uint8_t FPS;
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uint8_t MinActiveFreqType;
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FloatInIntFormat_t MinActiveFreq;
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FloatInIntFormat_t PD_Data_limit;
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FloatInIntFormat_t PD_Data_time_constant;
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FloatInIntFormat_t PD_Data_error_coeff;
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FloatInIntFormat_t PD_Data_error_rate_coeff;
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} DpmActivityMonitorCoeffExt_t;
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typedef struct {
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DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT];
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} CustomDpmSettings_t;
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#define NUM_DCFCLK_DPM_LEVELS 8
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#define NUM_DISPCLK_DPM_LEVELS 8
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#define NUM_DPPCLK_DPM_LEVELS 8
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#define NUM_SOCCLK_DPM_LEVELS 8
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#define NUM_VCN_DPM_LEVELS 8
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#define NUM_SOC_VOLTAGE_LEVELS 8
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#define NUM_VPE_DPM_LEVELS 8
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#define NUM_FCLK_DPM_LEVELS 8
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#define NUM_MEM_PSTATE_LEVELS 4
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typedef struct {
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uint32_t UClk;
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uint32_t MemClk;
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uint32_t Voltage;
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uint8_t WckRatio;
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uint8_t Spare[3];
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} MemPstateTable_t;
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//Freq in MHz
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//Voltage in milli volts with 2 fractional bits
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typedef struct {
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uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
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uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
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uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
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uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
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uint32_t VClocks[NUM_VCN_DPM_LEVELS];
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uint32_t DClocks[NUM_VCN_DPM_LEVELS];
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uint32_t VPEClocks[NUM_VPE_DPM_LEVELS];
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uint32_t FclkClocks_Freq[NUM_FCLK_DPM_LEVELS];
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uint32_t FclkClocks_Voltage[NUM_FCLK_DPM_LEVELS];
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uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];
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MemPstateTable_t MemPstateTable[NUM_MEM_PSTATE_LEVELS];
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uint8_t NumDcfClkLevelsEnabled;
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uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk
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uint8_t NumSocClkLevelsEnabled;
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uint8_t VcnClkLevelsEnabled; //Applies to both Vclk and Dclk
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uint8_t VpeClkLevelsEnabled;
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uint8_t NumMemPstatesEnabled;
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uint8_t NumFclkLevelsEnabled;
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uint8_t spare;
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uint32_t MinGfxClk;
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uint32_t MaxGfxClk;
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} DpmClocks_t;
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typedef struct {
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uint16_t CoreFrequency[16]; //Target core frequency [MHz]
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uint16_t CorePower[16]; //CAC calculated core power [mW]
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uint16_t CoreTemperature[16]; //TSEN measured core temperature [centi-C]
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uint16_t GfxTemperature; //TSEN measured GFX temperature [centi-C]
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uint16_t SocTemperature; //TSEN measured SOC temperature [centi-C]
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uint16_t StapmOpnLimit; //Maximum IRM defined STAPM power limit [mW]
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uint16_t StapmCurrentLimit; //Time filtered STAPM power limit [mW]
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uint16_t InfrastructureCpuMaxFreq; //CCLK frequency limit enforced on classic cores [MHz]
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uint16_t InfrastructureGfxMaxFreq; //GFXCLK frequency limit enforced on GFX [MHz]
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uint16_t SkinTemp; //Maximum skin temperature reported by APU and HS2 chassis sensors [centi-C]
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uint16_t GfxclkFrequency; //Time filtered target GFXCLK frequency [MHz]
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uint16_t FclkFrequency; //Time filtered target FCLK frequency [MHz]
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uint16_t GfxActivity; //Time filtered GFX busy % [0-100]
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uint16_t SocclkFrequency; //Time filtered target SOCCLK frequency [MHz]
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uint16_t VclkFrequency; //Time filtered target VCLK frequency [MHz]
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uint16_t VcnActivity; //Time filtered VCN busy % [0-100]
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uint16_t VpeclkFrequency; //Time filtered target VPECLK frequency [MHz]
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uint16_t NpuclkFrequency; //Time filtered target NPUCLK frequency [MHz]
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uint16_t NpuBusy[8]; //Time filtered NPU per-column busy % [0-100]
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uint16_t DRAMReads; //Time filtered DRAM read bandwidth [MB/sec]
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uint16_t DRAMWrites; //Time filtered DRAM write bandwidth [MB/sec]
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uint16_t CoreC0Residency[16]; //Time filtered per-core C0 residency % [0-100]
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uint16_t NpuPower; //Time filtered NPU power [mW]
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uint32_t ApuPower; //Time filtered APU power [mW]
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uint32_t GfxPower; //Time filtered GFX power [mW]
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uint32_t dGpuPower; //Time filtered dGPU power [mW]
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uint32_t SocketPower; //Time filtered power used for PPT/STAPM [APU+dGPU] [mW]
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uint32_t AllCorePower; //Time filtered sum of core power across all cores in the socket [mW]
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uint32_t FilterAlphaValue; //Metrics table alpha filter time constant [us]
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uint32_t MetricsCounter; //Counter that is incremented on every metrics table update [PM_TIMER cycles]
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uint16_t MemclkFrequency; //Time filtered target MEMCLK frequency [MHz]
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uint16_t AieclkFrequency; //Time filtered target AIECLK frequency [MHz]
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uint16_t NpuReads; //Time filtered NPU read bandwidth [MB/sec]
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uint16_t NpuWrites; //Time filtered NPU write bandwidth [MB/sec]
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uint32_t ThrottleResidency_PROCHOT; //Counter that is incremented on every metrics table update when PROCHOT was engaged [PM_TIMER cycles]
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uint32_t ThrottleResidency_SPL; //Counter that is incremented on every metrics table update when SPL was engaged [PM_TIMER cycles]
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uint32_t ThrottleResidency_FPPT; //Counter that is incremented on every metrics table update when fast PPT was engaged [PM_TIMER cycles]
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uint32_t ThrottleResidency_SPPT; //Counter that is incremented on every metrics table update when slow PPT was engaged [PM_TIMER cycles]
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uint32_t ThrottleResidency_THM_VDD; //Counter that is incremented on every metrics table update when VDD thermal throttling was engaged [PM_TIMER cycles]
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uint32_t ThrottleResidency_THM_SOC; //Counter that is incremented on every metrics table update when SOC thermal throttling was engaged [PM_TIMER cycles]
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uint16_t Psys; //Time filtered Psys power [mW]
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uint16_t spare1;
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uint32_t spare[6];
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} SmuMetrics_t;
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//ISP tile definitions
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typedef enum {
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TILE_XTILE = 0, //ONO0
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TILE_MTILE, //ONO1
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TILE_PDP, //ONO2
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TILE_CSTAT, //ONO2
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TILE_LME, //ONO3
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TILE_BYRP, //ONO4
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TILE_GRBP, //ONO4
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TILE_MCFP, //ONO4
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TILE_YUVP, //ONO4
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TILE_MCSC, //ONO4
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TILE_GDC, //ONO5
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TILE_MAX
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} TILE_NUM_e;
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// Tile Selection (Based on arguments)
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#define ISP_TILE_SEL(tile) (1<<tile)
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#define ISP_TILE_SEL_ALL 0x7FF
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// Workload bits
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#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0
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#define WORKLOAD_PPLIB_VIDEO_BIT 2
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#define WORKLOAD_PPLIB_VR_BIT 3
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#define WORKLOAD_PPLIB_COMPUTE_BIT 4
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#define WORKLOAD_PPLIB_CUSTOM_BIT 5
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#define WORKLOAD_PPLIB_COUNT 6
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#define TABLE_BIOS_IF 0 // Called by BIOS
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#define TABLE_WATERMARKS 1 // Called by DAL through VBIOS, for Medusa generation this should no longer be used
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#define TABLE_CUSTOM_DPM 2 // Called by Driver
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#define TABLE_BIOS_GPIO_CONFIG 3 // Called by BIOS
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#define TABLE_DPMCLOCKS 4 // Called by Driver and VBIOS
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#define TABLE_SPARE0 5 // Unused
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#define TABLE_SPARE1 6 // Unused
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#define TABLE_SMU_METRICS 7 // Called by Driver and SMF/PMF
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#define TABLE_COUNT 8
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#endif
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160
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v15_0_0_pmfw.h
Normal file
160
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v15_0_0_pmfw.h
Normal file
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@ -0,0 +1,160 @@
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/*
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* Copyright 2025 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
|
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef SMU15_DRIVER_IF_V15_0_H
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#define SMU15_DRIVER_IF_V15_0_H
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#include "smu15_driver_if_v15_0_0.h"
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#pragma pack(push, 1)
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#define ENABLE_DEBUG_FEATURES
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// Firmware features
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// Feature Control Defines
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#define FEATURE_CCLK_DPM_BIT 0
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#define FEATURE_FAN_CONTROLLER_BIT 1
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#define FEATURE_DATA_CALCULATION_BIT 2
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#define FEATURE_PPT_BIT 3
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#define FEATURE_TDC_BIT 4
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#define FEATURE_THERMAL_BIT 5
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#define FEATURE_FIT_BIT 6
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#define FEATURE_EDC_BIT 7
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#define FEATURE_PLL_POWER_DOWN_BIT 8
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#define FEATURE_VDDOFF_BIT 9
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#define FEATURE_VCN_DPM_BIT 10
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#define FEATURE_DS_MPM_BIT 11
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#define FEATURE_FCLK_DPM_BIT 12
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#define FEATURE_SOCCLK_DPM_BIT 13
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#define FEATURE_DS_MPIO_BIT 14
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#define FEATURE_LCLK_DPM_BIT 15
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#define FEATURE_SHUBCLK_DPM_BIT 16
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#define FEATURE_DCFCLK_DPM_BIT 17
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#define FEATURE_ISP_DPM_BIT 18
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#define FEATURE_NPU_DPM_BIT 19
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#define FEATURE_GFX_DPM_BIT 20
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#define FEATURE_DS_GFXCLK_BIT 21
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#define FEATURE_DS_SOCCLK_BIT 22
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#define FEATURE_DS_LCLK_BIT 23
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#define FEATURE_LOW_POWER_DCNCLKS_BIT 24 // for all DISP clks
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#define FEATURE_DS_SHUBCLK_BIT 25
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#define FEATURE_VRHOT_BIT 26
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#define FEATURE_Z8_BIT 27
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#define FEATURE_PCC_BIT 28
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#define FEATURE_DS_FCLK_BIT 29
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#define FEATURE_DS_SMNCLK_BIT 30
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#define FEATURE_DS_MP1CLK_BIT 31
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#define FEATURE_SPM_BIT 32
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#define FEATURE_SMU_LOW_POWER_BIT 33
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#define FEATURE_SMART_L3_RINSER_BIT 34 // Amit: it is spare
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#define FEATURE_DS_DACCCLK_BIT 35
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#define FEATURE_PSI_BIT 36
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#define FEATURE_PROCHOT_BIT 37
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#define FEATURE_CPUOFF_BIT 38
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#define FEATURE_STAPM_BIT 39
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#define FEATURE_S0I3_BIT 40
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#define FEATURE_DF_LIGHT_CSTATE 41
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#define FEATURE_PERF_LIMIT_BIT 42
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#define FEATURE_CORE_DLDO_BIT 43
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#define FEATURE_DVO_BIT 44
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#define FEATURE_DS_VCN_BIT 45
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#define FEATURE_CPPC_BIT 46
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#define FEATURE_CPPC_PREFERRED_CORES 47
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#define FEATURE_DF_CSTATES_BIT 48
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#define FEATURE_CSTATE_BOOST_BIT 49
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#define FEATURE_ATHUB_PG_BIT 50
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#define FEATURE_VDDOFF_ECO_BIT 51
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#define FEATURE_SC_DIDT_BIT 52 //SC_DIDT
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#define FEATURE_CC6_BIT 53
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#define FEATURE_DS_UMCCLK_BIT 54
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#define FEATURE_DS_ISPCLK_BIT 55
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#define FEATURE_DS_HSPCLK_BIT 56
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#define FEATURE_P3T_BIT 57
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#define FEATURE_DS_NPUCLK_BIT 58
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#define FEATURE_DS_VPECLK_BIT 59
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#define FEATURE_VPE_DPM_BIT 60
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#define FEATURE_DACCCLK_DPM_BIT 61
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#define FEATURE_FP_DIDT 62
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#define FEATURE_MMHUB_PG_BIT 63
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#define NUM_FEATURES 64
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// Firmware Header/Footer
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struct SMU_Firmware_Footer {
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uint32_t Signature;
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};
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typedef struct SMU_Firmware_Footer SMU_Firmware_Footer;
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// PSP3.0 Header Definition
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typedef struct {
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uint32_t ImageVersion;
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uint32_t ImageVersion2; // This is repeated because DW0 cannot be written in SRAM due to HW bug.
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uint32_t Padding0[3];
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uint32_t SizeFWSigned;
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uint32_t Padding1[25];
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uint32_t FirmwareType;
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uint32_t Filler[32];
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} SMU_Firmware_Header;
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typedef struct {
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// MP1_EXT_SCRATCH0
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uint32_t DpmHandlerID : 8;
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uint32_t ActivityMonitorID : 8;
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uint32_t DpmTimerID : 8;
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uint32_t DpmHubID : 4;
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uint32_t DpmHubTask : 4;
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// MP1_EXT_SCRATCH1
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uint32_t CclkSyncStatus : 8;
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uint32_t Ccx0CpuOff : 2;
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uint32_t Ccx1CpuOff : 2;
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uint32_t Ccx2CpuOff : 2;
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uint32_t GfxOffStatus : 2;
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uint32_t VddOff : 1;
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uint32_t InWhisperMode : 1;
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uint32_t ZstateStatus : 4;
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uint32_t DcnIps2Status : 2;
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uint32_t DstateFun : 4;
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uint32_t DstateDev : 4;
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// MP1_EXT_SCRATCH2
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uint32_t P2JobHandler :24;
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uint32_t RsmuPmiP2PendingCnt : 8;
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// MP1_EXT_SCRATCH3
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uint32_t PostCode :32;
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// MP1_EXT_SCRATCH4
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uint32_t MsgPortBusy :24;
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uint32_t RsmuPmiP1Pending : 1;
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uint32_t DfCstateExitPending : 1;
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uint32_t Ccx0Pc6ExitPending : 1;
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uint32_t Ccx1Pc6ExitPending : 1;
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uint32_t Ccx2Pc6ExitPending : 1;
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uint32_t WarmResetPending : 1;
|
||||
uint32_t spare1 : 2;
|
||||
// MP1_EXT_SCRATCH5
|
||||
uint32_t IdleMask :32;
|
||||
// MP1_EXT_SCRATCH6 = RTOS threads' status
|
||||
// MP1_EXT_SCRATCH7 = RTOS Current Job
|
||||
} FwStatus_t;
|
||||
|
||||
|
||||
#pragma pack(pop)
|
||||
|
||||
#endif
|
||||
133
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v15_0_0_ppsmc.h
Normal file
133
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v15_0_0_ppsmc.h
Normal file
|
|
@ -0,0 +1,133 @@
|
|||
/*
|
||||
* Copyright 2025 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __SMU_V15_0_0_PPSMC_H__
|
||||
#define __SMU_V15_0_0_PPSMC_H__
|
||||
|
||||
|
||||
/**
|
||||
* @file ppsmc.h
|
||||
*
|
||||
* @brief pplib (driver/host) to PMFW Interface
|
||||
*
|
||||
* Clients: Driver/Host via pplib.
|
||||
* Protocols:
|
||||
*
|
||||
* @date 2016 - 2024
|
||||
*/
|
||||
|
||||
/*! @mainpage PMFW-PPS (PPLib) Message Interface
|
||||
This documentation contains the subsections:\n\n
|
||||
@ref ResponseCodes\n
|
||||
@ref definitions\n
|
||||
@ref enums\n
|
||||
*/
|
||||
|
||||
/** @def PPS_PMFW_IF_VER
|
||||
* PPS (PPLib) to PMFW IF version 1.0
|
||||
*/
|
||||
#define PPS_PMFW_IF_VER "1.0" ///< Major.Minor
|
||||
|
||||
/** @defgroup ResponseCodes PMFW Response Codes
|
||||
* @{
|
||||
*/
|
||||
// SMU Response Codes:
|
||||
#define PPSMC_Result_OK 0x1 ///< Message Response OK
|
||||
#define PPSMC_Result_Failed 0xFF ///< Message Response Failed
|
||||
#define PPSMC_Result_UnknownCmd 0xFE ///< Message Response Unknown Command
|
||||
#define PPSMC_Result_CmdRejectedPrereq 0xFD ///< Message Response Command Failed Prerequisite
|
||||
#define PPSMC_Result_CmdRejectedBusy 0xFC ///< Message Response Command Rejected due to PMFW is busy. Sender should retry sending this message
|
||||
/** @}*/
|
||||
|
||||
/** @defgroup definitions Message definitions
|
||||
* @{
|
||||
*/
|
||||
// Message Definitions:
|
||||
#define PPSMC_MSG_TestMessage 0x01 ///< To check if PMFW is alive and responding. Requirement specified by PMFW team
|
||||
#define PPSMC_MSG_GetPmfwVersion 0x02 ///< Get PMFW version
|
||||
#define PPSMC_MSG_GetDriverIfVersion 0x03 ///< Get PMFW_DRIVER_IF version
|
||||
#define PPSMC_MSG_PowerDownVcn 0x04 ///< Power down VCN
|
||||
#define PPSMC_MSG_PowerUpVcn 0x05 ///< Power up VCN; VCN is power gated by default
|
||||
#define PPSMC_MSG_SetSoftMinGfxclk 0x06 ///< Set SoftMin for GFXCLK, argument is frequency in MHz
|
||||
#define PPSMC_MSG_PrepareMp1ForUnload 0x07 ///< Prepare PMFW for GFX driver unload
|
||||
#define PPSMC_MSG_TransferTableSmu2Dram 0x08 ///< Transfer driver interface table from PMFW SRAM to DRAM
|
||||
#define PPSMC_MSG_TransferTableDram2Smu 0x09 ///< Transfer driver interface table from DRAM to PMFW SRAM
|
||||
#define PPSMC_MSG_GfxDeviceDriverReset 0x0A ///< Request GFX mode 2 reset
|
||||
#define PPSMC_MSG_GetEnabledSmuFeatures 0x0B ///< Get enabled features in PMFW
|
||||
#define PPSMC_MSG_SetSoftMinFclk 0x0C ///< Set hard min for FCLK
|
||||
#define PPSMC_MSG_SetSoftMinVcn 0x0D ///< Set soft min for VCN clocks (VCLK and DCLK)
|
||||
|
||||
#define PPSMC_MSG_EnableGfxImu 0x0E ///< Enable GFX IMU
|
||||
|
||||
#define PPSMC_MSG_AllowGfxOff 0x0F ///< Inform PMFW of allowing GFXOFF entry
|
||||
#define PPSMC_MSG_DisallowGfxOff 0x10 ///< Inform PMFW of disallowing GFXOFF entry
|
||||
#define PPSMC_MSG_SetSoftMaxGfxClk 0x11 ///< Set soft max for GFX CLK
|
||||
|
||||
#define PPSMC_MSG_SetSoftMaxSocclkByFreq 0x12 ///< Set soft max for SOC CLK
|
||||
#define PPSMC_MSG_SetSoftMaxFclkByFreq 0x13 ///< Set soft max for FCLK
|
||||
#define PPSMC_MSG_SetSoftMaxVcn 0x14 ///< Set soft max for VCN clocks (VCLK and DCLK)
|
||||
#define PPSMC_MSG_PowerDownJpeg 0x15 ///< Power down Jpeg
|
||||
#define PPSMC_MSG_PowerUpJpeg 0x16 ///< Power up Jpeg; VCN is power gated by default
|
||||
|
||||
#define PPSMC_MSG_SetSoftMinSocclkByFreq 0x17 ///< Set soft min for SOC CLK
|
||||
#define PPSMC_MSG_AllowZstates 0x18 ///< Inform PMFM of allowing Zstate entry, i.e. no Miracast activity
|
||||
#define PPSMC_MSG_GetSmartShiftStatus 0x19 ///< Returns SmartShift enable vs disable
|
||||
#define PPSMC_MSG_PowerDownUmsch 0x1A ///< Power down VCN.UMSCH (aka VSCH) scheduler
|
||||
#define PPSMC_MSG_PowerUpUmsch 0x1B ///< Power up VCN.UMSCH (aka VSCH) scheduler
|
||||
#define PPSMC_MSG_PowerUpVpe 0x1C ///< Power up VPE
|
||||
#define PPSMC_MSG_PowerDownVpe 0x1D ///< Power down VPE
|
||||
#define PPSMC_MSG_EnableLSdma 0x1E ///< Enable LSDMA
|
||||
#define PPSMC_MSG_DisableLSdma 0x1F ///< Disable LSDMA
|
||||
#define PPSMC_MSG_SetSoftMaxVpe 0x20 ///<
|
||||
#define PPSMC_MSG_SetSoftMinVpe 0x21 ///<
|
||||
#define PPSMC_Message_Count 0x22 ///< Total number of PPSMC messages
|
||||
/** @}*/
|
||||
|
||||
/**
|
||||
* @defgroup enums Enum Definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @enum Mode_Reset_e
|
||||
* Mode reset type, argument for PPSMC_MSG_GfxDeviceDriverReset
|
||||
*/
|
||||
//argument for PPSMC_MSG_GfxDeviceDriverReset
|
||||
typedef enum {
|
||||
MODE1_RESET = 1, ///< Mode reset type 1
|
||||
MODE2_RESET = 2 ///< Mode reset type 2
|
||||
} Mode_Reset_e;
|
||||
|
||||
/** @}*/
|
||||
|
||||
/** @enum ZStates_e
|
||||
* Zstate types, argument for PPSMC_MSG_AllowZstates
|
||||
*/
|
||||
//Argument for PPSMC_MSG_AllowZstates
|
||||
typedef enum {
|
||||
DISALLOW_ZSTATES = 0, ///< Disallow Zstates
|
||||
ALLOW_ZSTATES_Z8 = 8, ///< Allows Z8 only
|
||||
ALLOW_ZSTATES_Z9 = 9, ///< Allows Z9 and Z8
|
||||
} ZStates_e;
|
||||
|
||||
/** @}*/
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user