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drm/amd/display: Enable dcn42 in DM
Add support for DCN 4.2 in Display Manager Signed-off-by: Roman Li <Roman.Li@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Roman Li
Alex Deucher
parent
6b2dd7d37b
commit
a6713b890c
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: MIT
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/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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* Copyright 2015-2026 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@ -152,6 +152,9 @@ MODULE_FIRMWARE(FIRMWARE_DCN_36_DMUB);
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#define FIRMWARE_DCN_401_DMUB "amdgpu/dcn_4_0_1_dmcub.bin"
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MODULE_FIRMWARE(FIRMWARE_DCN_401_DMUB);
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#define FIRMWARE_DCN_42_DMUB "amdgpu/dcn_4_2_dmcub.bin"
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MODULE_FIRMWARE(FIRMWARE_DCN_42_DMUB);
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/**
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* DOC: overview
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*
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@ -1368,6 +1371,7 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)
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case IP_VERSION(3, 5, 0):
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case IP_VERSION(3, 5, 1):
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case IP_VERSION(3, 6, 0):
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case IP_VERSION(4, 2, 0):
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hw_params.ips_sequential_ono = adev->external_rev_id > 0x10;
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hw_params.lower_hbr3_phy_ssc = true;
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break;
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@ -1815,6 +1819,9 @@ static void *dm_dmub_get_vbios_bounding_box(struct amdgpu_device *adev)
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case IP_VERSION(4, 0, 1):
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bb_size = sizeof(struct dml2_soc_bb);
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break;
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case IP_VERSION(4, 2, 0):
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bb_size = sizeof(struct dml2_soc_bb);
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break;
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default:
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return NULL;
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}
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@ -1859,6 +1866,9 @@ static enum dmub_ips_disable_type dm_get_default_ips_mode(
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case IP_VERSION(3, 5, 1):
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ret = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;
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break;
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case IP_VERSION(4, 2, 0):
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ret = DMUB_IPS_DISABLE_ALL;
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break;
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default:
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/* ASICs older than DCN35 do not have IPSs */
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if (amdgpu_ip_version(adev, DCE_HWIP, 0) < IP_VERSION(3, 5, 0))
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@ -2002,6 +2012,13 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
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if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0))
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init_data.num_virtual_links = 1;
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/* DCN42 and above dpia switch to unified link training path */
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if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(4, 2, 0)) {
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init_data.flags.consolidated_dpia_dp_lt = true;
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init_data.flags.enable_dpia_pre_training = true;
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init_data.flags.unify_link_enc_assignment = true;
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init_data.flags.usb4_bw_alloc_support = true;
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}
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retrieve_dmi_info(&adev->dm);
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if (adev->dm.edp0_on_dp1_quirk)
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init_data.flags.support_edp0_on_dp1 = true;
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@ -2369,6 +2386,7 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
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case IP_VERSION(3, 5, 1):
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case IP_VERSION(3, 6, 0):
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case IP_VERSION(4, 0, 1):
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case IP_VERSION(4, 2, 0):
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return 0;
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default:
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break;
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@ -2502,7 +2520,9 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
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case IP_VERSION(4, 0, 1):
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dmub_asic = DMUB_ASIC_DCN401;
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break;
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case IP_VERSION(4, 2, 0):
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dmub_asic = DMUB_ASIC_DCN42;
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break;
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default:
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/* ASIC doesn't support DMUB. */
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return 0;
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@ -5449,6 +5469,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
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case IP_VERSION(3, 5, 1):
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case IP_VERSION(3, 6, 0):
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case IP_VERSION(4, 0, 1):
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case IP_VERSION(4, 2, 0):
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if (register_outbox_irq_handlers(dm->adev)) {
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drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n");
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goto fail;
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@ -5473,6 +5494,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
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case IP_VERSION(3, 5, 1):
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case IP_VERSION(3, 6, 0):
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case IP_VERSION(4, 0, 1):
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case IP_VERSION(4, 2, 0):
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psr_feature_enabled = true;
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break;
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default:
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@ -5650,6 +5672,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
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case IP_VERSION(3, 5, 1):
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case IP_VERSION(3, 6, 0):
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case IP_VERSION(4, 0, 1):
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case IP_VERSION(4, 2, 0):
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if (dcn10_register_irq_handlers(dm->adev)) {
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drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n");
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goto fail;
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@ -5798,6 +5821,9 @@ static int dm_init_microcode(struct amdgpu_device *adev)
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case IP_VERSION(4, 0, 1):
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fw_name_dmub = FIRMWARE_DCN_401_DMUB;
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break;
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case IP_VERSION(4, 2, 0):
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fw_name_dmub = FIRMWARE_DCN_42_DMUB;
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break;
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default:
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/* ASIC doesn't support DMUB. */
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return 0;
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@ -5925,6 +5951,7 @@ static int dm_early_init(struct amdgpu_ip_block *ip_block)
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case IP_VERSION(3, 5, 1):
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case IP_VERSION(3, 6, 0):
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case IP_VERSION(4, 0, 1):
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case IP_VERSION(4, 2, 0):
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adev->mode_info.num_crtc = 4;
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adev->mode_info.num_hpd = 4;
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adev->mode_info.num_dig = 4;
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@ -12223,10 +12250,11 @@ static int dm_crtc_get_cursor_mode(struct amdgpu_device *adev,
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int i;
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/* Overlay cursor not supported on HW before DCN
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* DCN401 does not have the cursor-on-scaled-plane or cursor-on-yuv-plane restrictions
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* as previous DCN generations, so enable native mode on DCN401
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* DCN401/420 does not have the cursor-on-scaled-plane or cursor-on-yuv-plane restrictions
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* as previous DCN generations, so enable native mode on DCN401/420
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*/
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if (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1)) {
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if (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1) ||
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amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 2, 0)) {
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*cursor_mode = DM_CURSOR_NATIVE_MODE;
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return 0;
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}
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@ -12646,7 +12674,8 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
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/* Check if rotation or scaling is enabled on DCN401 */
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if ((drm_plane_mask(crtc->cursor) & new_crtc_state->plane_mask) &&
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amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1)) {
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(amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 2, 0) ||
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amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1))) {
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new_cursor_state = drm_atomic_get_new_plane_state(state, crtc->cursor);
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is_rotated = new_cursor_state &&
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: MIT
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/*
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* Copyright 2022 Advanced Micro Devices, Inc.
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* Copyright 2022-2026 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@ -759,6 +759,7 @@ static int amdgpu_dm_plane_get_plane_modifiers(struct amdgpu_device *adev, unsig
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case AMDGPU_FAMILY_GC_11_0_0:
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case AMDGPU_FAMILY_GC_11_0_1:
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case AMDGPU_FAMILY_GC_11_5_0:
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case AMDGPU_FAMILY_GC_11_5_4:
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amdgpu_dm_plane_add_gfx11_modifiers(adev, mods, &size, &capacity);
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break;
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case AMDGPU_FAMILY_GC_12_0_0:
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