github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-09-23 13:14:02 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

drm/amd/display: Allocate DCN32/1 dmub memory to GTT

Browse Source 
[Why]
On DCN32/321  sometimes DMCUB takes a long time to flush.
This adds a delay before the data is available on the driver side even
after driver receives notification from DMCUB via inbox

[How]
Allocating DMUB memory to GTT gives much better latency. Limit this to
DCN32/1 for now; it will be made general to all other dGPUs later.

Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: Sun peng (Leo) Li <sunpeng.li@amd.com>
Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Fangzhi Zuo 2026-06-18 15:02:13 -04:00 committed by Alex Deucher
parent 1d8327353d
commit a637a140ab
1 changed files with 9 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c
View File

@ -506,6 +506,7 @@ int dm_dmub_sw_init(struct amdgpu_device *adev)
DMUB_WINDOW_MEMORY_TYPE_FB, /* DMUB_WINDOW_CURSOR_OFFLOAD */
};
int r;
int mem_domain = AMDGPU_GEM_DOMAIN_GTT;
switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
case IP_VERSION(2, 1, 0):
@ -639,13 +640,19 @@ int dm_dmub_sw_init(struct amdgpu_device *adev)
return -EINVAL;
}
/* Limit to allocate dmub to GTT on DCN32/1
* TODO: Other asics with GDDR7 may have worse latency
*/
if (dmub_asic != DMUB_ASIC_DCN32 &&
dmub_asic != DMUB_ASIC_DCN321)
mem_domain |= AMDGPU_GEM_DOMAIN_VRAM;
/*
* Allocate a framebuffer based on the total size of all the regions.
* TODO: Move this into GART.
*/
r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM |
AMDGPU_GEM_DOMAIN_GTT,
mem_domain,
&adev->dm.dmub_bo,
&adev->dm.dmub_bo_gpu_addr,
&adev->dm.dmub_bo_cpu_addr);