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wifi: iwlwifi: add support for SNPS DPHYIP region type
Add the required logic for parsing and dumping this new region. Signed-off-by: Daniel Gabay <daniel.gabay@intel.com> Signed-off-by: Gregory Greenman <gregory.greenman@intel.com> Link: https://lore.kernel.org/r/20231017115047.c859539194e7.I965482de2871e28b09f4572f1aa87ae4e3b366be@changeid Signed-off-by: Johannes Berg <johannes.berg@intel.com>
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@ -159,6 +159,7 @@ struct iwl_fw_ini_region_internal_buffer {
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* &IWL_FW_INI_REGION_PAGING, &IWL_FW_INI_REGION_CSR,
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* &IWL_FW_INI_REGION_DRAM_IMR and &IWL_FW_INI_REGION_PCI_IOSF_CONFIG
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* &IWL_FW_INI_REGION_DBGI_SRAM, &FW_TLV_DEBUG_REGION_TYPE_DBGI_SRAM,
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* &IWL_FW_INI_REGION_PERIPHERY_SNPS_DPHYIP,
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* @dev_addr_range: device address range configuration. Used by
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* &IWL_FW_INI_REGION_PERIPHERY_MAC_RANGE and
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* &IWL_FW_INI_REGION_PERIPHERY_PHY_RANGE
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@ -392,6 +393,7 @@ enum iwl_fw_ini_buffer_location {
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* @IWL_FW_INI_REGION_DBGI_SRAM: periphery registers of DBGI SRAM
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* @IWL_FW_INI_REGION_PERIPHERY_MAC_RANGE: a range of periphery registers of MAC
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* @IWL_FW_INI_REGION_PERIPHERY_PHY_RANGE: a range of periphery registers of PHY
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* @IWL_FW_INI_REGION_PERIPHERY_SNPS_DPHYIP: periphery registers of SNPS DPHYIP
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* @IWL_FW_INI_REGION_NUM: number of region types
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*/
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enum iwl_fw_ini_region_type {
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@ -416,6 +418,7 @@ enum iwl_fw_ini_region_type {
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IWL_FW_INI_REGION_DBGI_SRAM,
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IWL_FW_INI_REGION_PERIPHERY_MAC_RANGE,
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IWL_FW_INI_REGION_PERIPHERY_PHY_RANGE,
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IWL_FW_INI_REGION_PERIPHERY_SNPS_DPHYIP,
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IWL_FW_INI_REGION_NUM
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}; /* FW_TLV_DEBUG_REGION_TYPE_API_E */
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@ -1416,6 +1416,53 @@ static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime *fwrt,
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return sizeof(*range) + le32_to_cpu(range->range_data_size);
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}
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static int
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iwl_dump_ini_prph_snps_dphyip_iter(struct iwl_fw_runtime *fwrt,
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struct iwl_dump_ini_region_data *reg_data,
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void *range_ptr, u32 range_len, int idx)
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{
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struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
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struct iwl_fw_ini_error_dump_range *range = range_ptr;
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__le32 *val = range->data;
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__le32 offset = reg->dev_addr.offset;
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u32 indirect_rd_wr_addr = DPHYIP_INDIRECT;
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u32 addr = le32_to_cpu(reg->addrs[idx]);
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u32 dphy_state, dphy_addr, prph_val;
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int i;
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range->internal_base_addr = cpu_to_le32(addr);
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range->range_data_size = reg->dev_addr.size;
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if (!iwl_trans_grab_nic_access(fwrt->trans))
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return -EBUSY;
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indirect_rd_wr_addr += le32_to_cpu(offset);
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dphy_addr = offset ? WFPM_LMAC2_PS_CTL_RW : WFPM_LMAC1_PS_CTL_RW;
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dphy_state = iwl_read_umac_prph_no_grab(fwrt->trans, dphy_addr);
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for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) {
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if (dphy_state == HBUS_TIMEOUT ||
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(dphy_state & WFPM_PS_CTL_RW_PHYRF_PD_FSM_CURSTATE_MSK) !=
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WFPM_PHYRF_STATE_ON) {
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*val++ = cpu_to_le32(WFPM_DPHY_OFF);
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continue;
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}
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iwl_write_prph_no_grab(fwrt->trans, indirect_rd_wr_addr,
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addr + i);
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/* wait a bit for value to be ready in register */
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udelay(1);
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prph_val = iwl_read_prph_no_grab(fwrt->trans,
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indirect_rd_wr_addr);
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*val++ = cpu_to_le32((prph_val & DPHYIP_INDIRECT_RD_MSK) >>
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DPHYIP_INDIRECT_RD_SHIFT);
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}
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iwl_trans_release_nic_access(fwrt->trans);
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return sizeof(*range) + le32_to_cpu(range->range_data_size);
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}
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struct iwl_ini_rxf_data {
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u32 fifo_num;
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u32 size;
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@ -2537,6 +2584,12 @@ static const struct iwl_dump_ini_mem_ops iwl_dump_ini_region_ops[] = {
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.fill_mem_hdr = iwl_dump_ini_mon_dbgi_fill_header,
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.fill_range = iwl_dump_ini_dbgi_sram_iter,
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},
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[IWL_FW_INI_REGION_PERIPHERY_SNPS_DPHYIP] = {
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.get_num_of_ranges = iwl_dump_ini_mem_ranges,
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.get_size = iwl_dump_ini_mem_get_size,
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.fill_mem_hdr = iwl_dump_ini_mem_fill_header,
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.fill_range = iwl_dump_ini_prph_snps_dphyip_iter,
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},
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};
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static u32 iwl_dump_ini_trigger(struct iwl_fw_runtime *fwrt,
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@ -2580,7 +2633,8 @@ static u32 iwl_dump_ini_trigger(struct iwl_fw_runtime *fwrt,
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continue;
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if ((reg_type == IWL_FW_INI_REGION_PERIPHERY_PHY ||
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reg_type == IWL_FW_INI_REGION_PERIPHERY_PHY_RANGE) &&
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reg_type == IWL_FW_INI_REGION_PERIPHERY_PHY_RANGE ||
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reg_type == IWL_FW_INI_REGION_PERIPHERY_SNPS_DPHYIP) &&
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tp_id != IWL_FW_INI_TIME_POINT_FW_ASSERT) {
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IWL_WARN(fwrt,
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"WRT: trying to collect phy prph at time point: %d, skipping\n",
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@ -516,4 +516,8 @@ enum {
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#define WFPM_LMAC2_PD_NOTIFICATION 0xA033CC
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#define WFPM_LMAC2_PD_RE_READ BIT(31)
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#define DPHYIP_INDIRECT 0xA2D800
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#define DPHYIP_INDIRECT_RD_MSK 0xFF000000
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#define DPHYIP_INDIRECT_RD_SHIFT 24
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#endif /* __iwl_prph_h__ */
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