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drm/amd/display: Revert "init dispclk from bootup clock for DCN315"
[Why&How] This reverts commit14bb17cc37. Due to the change, the display shows garbage on startup. We have an alternative solution for the original issue:d24203bb62("drm/amd/display: Re-check seamless boot can be enabled or not") Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Wang, Sung-huai <Danny.Wang@amd.com> Signed-off-by: Matthew Stewart <matthew.stewart2@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Wang, Sung-huai
Alex Deucher
parent
bdc26342c4
commit
a625dc4989
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@ -40,7 +40,7 @@
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#include "dm_helpers.h"
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#include "dc_dmub_srv.h"
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#include "reg_helper.h"
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#include "logger_types.h"
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#undef DC_LOGGER
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#define DC_LOGGER \
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@ -48,43 +48,9 @@
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#include "link_service.h"
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#define MAX_INSTANCE 7
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#define MAX_SEGMENT 8
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struct IP_BASE_INSTANCE {
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unsigned int segment[MAX_SEGMENT];
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};
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struct IP_BASE {
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struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
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};
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static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0, 0, 0 } },
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{ { 0x00016E00, 0x02401C00, 0, 0, 0, 0, 0, 0 } },
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{ { 0x00017000, 0x02402000, 0, 0, 0, 0, 0, 0 } },
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{ { 0x00017200, 0x02402400, 0, 0, 0, 0, 0, 0 } },
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{ { 0x0001B000, 0x0242D800, 0, 0, 0, 0, 0, 0 } },
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{ { 0x0001B200, 0x0242DC00, 0, 0, 0, 0, 0, 0 } } } };
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#define regCLK1_CLK0_CURRENT_CNT 0x0314
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#define regCLK1_CLK0_CURRENT_CNT_BASE_IDX 0
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#define regCLK1_CLK1_CURRENT_CNT 0x0315
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#define regCLK1_CLK1_CURRENT_CNT_BASE_IDX 0
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#define regCLK1_CLK2_CURRENT_CNT 0x0316
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#define regCLK1_CLK2_CURRENT_CNT_BASE_IDX 0
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#define regCLK1_CLK3_CURRENT_CNT 0x0317
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#define regCLK1_CLK3_CURRENT_CNT_BASE_IDX 0
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#define regCLK1_CLK4_CURRENT_CNT 0x0318
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#define regCLK1_CLK4_CURRENT_CNT_BASE_IDX 0
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#define regCLK1_CLK5_CURRENT_CNT 0x0319
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#define regCLK1_CLK5_CURRENT_CNT_BASE_IDX 0
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#define TO_CLK_MGR_DCN315(clk_mgr)\
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container_of(clk_mgr, struct clk_mgr_dcn315, base)
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#define REG(reg_name) \
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(CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
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#define UNSUPPORTED_DCFCLK 10000000
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#define MIN_DPP_DISP_CLK 100000
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@ -172,7 +138,7 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base,
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if (dc->work_arounds.skip_clock_update)
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return;
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clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
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display_count = dcn315_get_active_display_cnt_wa(dc, context);
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/*
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* if it is safe to lower, but we are already in the lower state, we don't have to do anything
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* also if safe to lower is false, we just go in the higher state
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@ -185,7 +151,6 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base,
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}
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/* check that we're not already in lower */
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if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
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display_count = dcn315_get_active_display_cnt_wa(dc, context);
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/* if we can go lower, go lower */
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if (display_count == 0) {
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union display_idle_optimization_u idle_info = { 0 };
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@ -279,38 +244,9 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base,
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dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
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}
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static void dcn315_dump_clk_registers_internal(struct dcn35_clk_internal *internal, struct clk_mgr *clk_mgr_base)
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{
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struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
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// read dtbclk
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internal->CLK1_CLK4_CURRENT_CNT = REG_READ(CLK1_CLK4_CURRENT_CNT);
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// read dcfclk
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internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_CLK3_CURRENT_CNT);
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// read dppclk
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internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_CLK1_CURRENT_CNT);
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// read dprefclk
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internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_CLK2_CURRENT_CNT);
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// read dispclk
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internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_CLK0_CURRENT_CNT);
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}
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static void dcn315_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
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struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
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{
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struct dcn35_clk_internal internal = {0};
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dcn315_dump_clk_registers_internal(&internal, clk_mgr_base);
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regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10;
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regs_and_bypass->dprefclk = internal.CLK1_CLK2_CURRENT_CNT / 10;
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regs_and_bypass->dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10;
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regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10;
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regs_and_bypass->dtbclk = internal.CLK1_CLK4_CURRENT_CNT / 10;
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return;
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}
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@ -657,32 +593,13 @@ static struct clk_mgr_funcs dcn315_funcs = {
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.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
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.get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
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.update_clocks = dcn315_update_clocks,
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.init_clocks = dcn315_init_clocks,
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.init_clocks = dcn31_init_clocks,
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.enable_pme_wa = dcn315_enable_pme_wa,
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.are_clock_states_equal = dcn31_are_clock_states_equal,
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.notify_wm_ranges = dcn315_notify_wm_ranges
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};
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extern struct clk_mgr_funcs dcn3_fpga_funcs;
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void dcn315_init_clocks(struct clk_mgr *clk_mgr)
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{
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struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);
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uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz;
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struct clk_mgr_dcn315 *clk_mgr_dcn315 = TO_CLK_MGR_DCN315(clk_mgr_int);
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struct clk_log_info log_info = {0};
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memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
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// Assumption is that boot state always supports pstate
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clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk; // restore ref_dtbclk
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clk_mgr->clks.p_state_change_support = true;
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clk_mgr->clks.prev_p_state_change_support = true;
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clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
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clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN;
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dcn315_dump_clk_registers(&clk_mgr->boot_snapshot, &clk_mgr_dcn315->base.base, &log_info);
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clk_mgr->clks.dispclk_khz = clk_mgr->boot_snapshot.dispclk * 1000;
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}
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void dcn315_clk_mgr_construct(
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struct dc_context *ctx,
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struct clk_mgr_dcn315 *clk_mgr,
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@ -743,7 +660,6 @@ void dcn315_clk_mgr_construct(
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/* Saved clocks configured at boot for debug purposes */
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dcn315_dump_clk_registers(&clk_mgr->base.base.boot_snapshot,
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&clk_mgr->base.base, &log_info);
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clk_mgr->base.base.clks.dispclk_khz = clk_mgr->base.base.boot_snapshot.dispclk * 1000;
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clk_mgr->base.base.dprefclk_khz = 600000;
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clk_mgr->base.base.dprefclk_khz = dcn315_smu_get_dpref_clk(&clk_mgr->base);
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@ -44,7 +44,6 @@ void dcn315_clk_mgr_construct(struct dc_context *ctx,
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struct pp_smu_funcs *pp_smu,
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struct dccg *dccg);
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void dcn315_init_clocks(struct clk_mgr *clk_mgr);
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void dcn315_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int);
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#endif //__DCN315_CLK_MGR_H__
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