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- amd64_edac: Shorten the ErrorInformation field read from the MCA_SYND MSR to

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only two bits. It is perfectly fine to do so because no system ever
   supported more than 2 bits of information (the Chip Selects used were only
   4 maximum) and newer hardware will use only 2 bits anyway
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Merge tag 'edac_urgent_for_v7.3_rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras

Pull EDAC fix from Borislav Petkov:

 - amd64_edac: Shorten the ErrorInformation field read from the MCA_SYND
   MSR to only two bits. It is perfectly fine to do so because no system
   ever supported more than 2 bits of information (the Chip Selects used
   were only 4 maximum) and newer hardware will use only 2 bits anyway

* tag 'edac_urgent_for_v7.3_rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras:
  EDAC/amd64: Mask UMC chip select to the four implemented selects
This commit is contained in:
Linus Torvalds 2026-10-10 16:57:30 -07:00
commit a5ebb76233
1 changed files with 2 additions and 2 deletions
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4
drivers/edac/amd64_edac.c
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@ -2796,13 +2796,13 @@ static inline void decode_bus_error(int node_id, struct mce *m)
* the instance_id. For example, instance_id=0xYXXXXX where Y is the channel
* number.
*
* For DRAM ECC errors, the Chip Select number is given in bits [2:0] of
* For DRAM ECC errors, the Chip Select number is given in bits [1:0] of
* the MCA_SYND[ErrorInformation] field.
*/
static void umc_get_err_info(struct mce *m, struct err_info *err)
{
err->channel = (m->ipid & GENMASK(31, 0)) >> 20;
err->csrow = m->synd & 0x7;
err->csrow = m->synd & 0x3;
}
static void decode_umc_error(int node_id, struct mce *m)