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drm/amd/amdgpu/include : update mes api header v11/v12

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Update the parameter in SET_HW_RESOURCES API 1. Align with the setting
of enable_lr_compute_wa 2. Add enable_compute_pipe_reset to enable
pipe reset when compute queue reset failes

v2: add driver flags to track when we enable it

Signed-off-by: Shaoyun Liu <shaoyun.liu@amd.com>
Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Shaoyun Liu 2026-04-20 10:45:50 -04:00 committed by Alex Deucher
parent 7f95690063
commit a5b9f68d38
3 changed files with 9 additions and 4 deletions
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3
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
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@ -168,6 +168,9 @@ struct amdgpu_mes {
int master_xcc_ids[AMDGPU_MAX_MES_INST_PIPES];
struct amdgpu_bo *shared_cmd_buf_obj[AMDGPU_MAX_MES_INST_PIPES];
uint64_t shared_cmd_buf_gpu_addr[AMDGPU_MAX_MES_INST_PIPES];
bool compute_pipe_reset_enabled;
bool gfx_pipe_reset_enabled;
};
struct amdgpu_mes_hung_queue_hqd_info {

5
drivers/gpu/drm/amd/include/mes_v11_api_def.h
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@ -238,8 +238,9 @@ union MESAPI_SET_HW_RESOURCES {
uint32_t enable_mes_sch_stb_log : 1;
uint32_t limit_single_process : 1;
uint32_t is_strix_tmz_wa_enabled :1;
uint32_t enable_lr_compute_wa : 1;
uint32_t reserved : 12;
uint32_t enable_lr_compute_wa : 2;
uint32_t enable_compute_pipe_reset : 1;
uint32_t reserved : 10;
};
uint32_t uint32_t_all;
};

5
drivers/gpu/drm/amd/include/mes_v12_api_def.h
View File

@ -294,8 +294,9 @@ union MESAPI_SET_HW_RESOURCES {
uint32_t limit_single_process : 1;
uint32_t unmapped_doorbell_handling: 2;
uint32_t enable_mes_fence_int: 1;
uint32_t enable_lr_compute_wa : 1;
uint32_t reserved : 9;
uint32_t enable_lr_compute_wa : 2;
uint32_t enable_compute_pipe_reset : 1;
uint32_t reserved : 7;
};
uint32_t uint32_all;
};