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i.MX arm device tree change for 5.17:

Browse Source 
- New board support: TQ-Systems MBa6x, Y Soft IOTA Crux/Crux+ board,
   JOZ Access Point, Phytec PEB-WLBT-05 support, BSH SMM-M2 IMX6ULZ
   SystemMaster.
 - Update SPBA bus node name to match binding schema.
 - A series from Christoph Niedermaier to update imx6qdl-dhcom board
   around Ethernet and USB support.
 - A series from Giulio Benetti to clean up undocumented/unused fixed
   clock compatibles.
 - A series from Laurent Pinchart to update i.MX7 MIPI_CSI support.
 - A couple of changes from Russell to update phy-mode for
   vf610-zii-dev-rev-b board.
 - Add Wacom digitizer support for imx7d-remarkable2 device.
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Merge tag 'imx-dt-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt

i.MX arm device tree change for 5.17:

- New board support: TQ-Systems MBa6x, Y Soft IOTA Crux/Crux+ board,
  JOZ Access Point, Phytec PEB-WLBT-05 support, BSH SMM-M2 IMX6ULZ
  SystemMaster.
- Update SPBA bus node name to match binding schema.
- A series from Christoph Niedermaier to update imx6qdl-dhcom board
  around Ethernet and USB support.
- A series from Giulio Benetti to clean up undocumented/unused fixed
  clock compatibles.
- A series from Laurent Pinchart to update i.MX7 MIPI_CSI support.
- A couple of changes from Russell to update phy-mode for
  vf610-zii-dev-rev-b board.
- Add Wacom digitizer support for imx7d-remarkable2 device.

* tag 'imx-dt-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (36 commits)
  ARM: dts: imx6: phytec: Add PEB-WLBT-05 support
  ARM: dts: imx6qdl: phytec: Add support for optional PEB-AV-02 LCD adapter
  ARM: dts: imx6qdl: phytec: Add support for optional PEB-EVAL-01 board
  ARM: dts: imx6qdl-dhcom: Add USB overcurrent pin on SoM layer
  ARM: dts: imx7d-remarkable2: add wacom digitizer device
  ARM: dts: imx6ulz-bsh-smm-m2: Add BSH SMM-M2 IMX6ULZ SystemMaster
  ARM: dts: imx6qdl-dhcom: Identify the PHY by ethernet-phy-id0007.c0f0
  ARM: dts: imx6qdl-dhcom: Align PHY reset timing with other DHCOM SoMs
  ARM: dts: imx6qdl: drop "fsl,imx-ckih1"
  ARM: dts: imx6qdl: drop "fsl,imx-ckil"
  ARM: dts: imx6qdl: drop "fsl,imx-osc"
  ARM: dts: imx53: drop "fsl,imx-ckih2"
  ARM: dts: imx53: drop "fsl,imx-ckih1"
  ARM: dts: imx53: drop "fsl,imx-ckil"
  ARM: dts: imx53: drop "fsl,imx-osc"
  ARM: dts: imx51: drop "fsl,imx-ckih2"
  ARM: dts: imx51: drop "fsl,imx-ckih1"
  ARM: dts: imx51: drop "fsl,imx-ckil"
  ARM: dts: imx51: drop "fsl,imx-osc"
  ARM: dts: imx50: drop "fsl,imx-ckih2"
  ...

Link: https://lore.kernel.org/r/20211218071427.26745-4-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2021-12-20 16:04:56 +01:00
commit a5a44f4d50
44 changed files with 2043 additions and 52 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
arch/arm/boot/dts/Makefile
View File

@ -486,6 +486,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-icore-rqs.dtb \
imx6dl-lanmcu.dtb \
imx6dl-mamoj.dtb \
imx6dl-mba6a.dtb \
imx6dl-mba6b.dtb \
imx6dl-nit6xlite.dtb \
imx6dl-nitrogen6x.dtb \
imx6dl-phytec-mira-rdk-nand.dtb \
@ -587,6 +589,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-kp-tpc.dtb \
imx6q-logicpd.dtb \
imx6q-marsboard.dtb \
imx6q-mba6a.dtb \
imx6q-mba6b.dtb \
imx6q-mccmon6.dtb \
imx6q-nitrogen6x.dtb \
imx6q-nitrogen6_max.dtb \
@ -631,7 +635,9 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-wandboard.dtb \
imx6q-wandboard-revb1.dtb \
imx6q-wandboard-revd1.dtb \
imx6q-yapp4-crux.dtb \
imx6q-zii-rdu2.dtb \
imx6qp-mba6b.dtb \
imx6qp-nitrogen6_max.dtb \
imx6qp-nitrogen6_som2.dtb \
imx6qp-phytec-mira-rdk-nand.dtb \
@ -644,6 +650,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6qp-tx6qp-8137-mb7.dtb \
imx6qp-vicutp.dtb \
imx6qp-wandboard-revd1.dtb \
imx6qp-yapp4-crux-plus.dtb \
imx6qp-zii-rdu2.dtb \
imx6s-dhcom-drc02.dtb
dtb-$(CONFIG_SOC_IMX6SL) += \
@ -691,12 +698,14 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ull-colibri-emmc-eval-v3.dtb \
imx6ull-colibri-eval-v3.dtb \
imx6ull-colibri-wifi-eval-v3.dtb \
imx6ull-jozacp.dtb \
imx6ull-myir-mys-6ulx-eval.dtb \
imx6ull-opos6uldev.dtb \
imx6ull-phytec-segin-ff-rdk-nand.dtb \
imx6ull-phytec-segin-ff-rdk-emmc.dtb \
imx6ull-phytec-segin-lc-rdk-nand.dtb \
imx6ulz-14x14-evk.dtb
imx6ulz-14x14-evk.dtb \
imx6ulz-bsh-smm-m2.dtb
dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-cl-som-imx7.dtb \
imx7d-colibri-aster.dtb \

6
arch/arm/boot/dts/imx1-pinfunc.h
View File

@ -26,9 +26,9 @@
* 2 - 0
* 3 - 1
*
* 'pin' is an integer between 0 and 0xbf. i.MX1 has 4 ports with 32 configurable
* configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is the pin
* number on the specific port (between 0 and 31).
* 'pin' is an integer between 0 and 0xbf. i.MX1 has 4 ports with 32
* configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is
* the pin number on the specific port (between 0 and 31).
*/
#define MX1_PAD_A24__A24 0x00 0x004

2
arch/arm/boot/dts/imx1.dtsi
View File

@ -55,7 +55,7 @@ cpu@0 {
clocks {
clk32 {
compatible = "fsl,imx-clk32", "fixed-clock";
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32000>;
};

4
arch/arm/boot/dts/imx25.dtsi
View File

@ -62,7 +62,7 @@ asic: asic-interrupt-controller@68000000 {
clocks {
osc {
compatible = "fsl,imx-osc", "fixed-clock";
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
@ -200,7 +200,7 @@ audmux: audmux@43fb0000 {
};
};
spba@50000000 {
spba-bus@50000000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;

6
arch/arm/boot/dts/imx27-pinfunc.h
View File

@ -26,9 +26,9 @@
* 2 - 0
* 3 - 1
*
* 'pin' is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable
* configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is the pin
* number on the specific port (between 0 and 31).
* 'pin' is an integer between 0 and 0xbf. imx27 has 6 ports with 32
* configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is
* the pin number on the specific port (between 0 and 31).
*/
#define MX27_PAD_USBH2_CLK__USBH2_CLK 0x00 0x000

2
arch/arm/boot/dts/imx31.dtsi
View File

@ -166,7 +166,7 @@ uart5: serial@43fb4000 {
};
};
spba@50000000 {
spba-bus@50000000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;

10
arch/arm/boot/dts/imx50.dtsi
View File

@ -62,25 +62,25 @@ tzic: tz-interrupt-controller@fffc000 {
clocks {
ckil {
compatible = "fsl,imx-ckil", "fixed-clock";
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
ckih1 {
compatible = "fsl,imx-ckih1", "fixed-clock";
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <22579200>;
};
ckih2 {
compatible = "fsl,imx-ckih2", "fixed-clock";
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
osc {
compatible = "fsl,imx-osc", "fixed-clock";
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
@ -108,7 +108,7 @@ bus@50000000 { /* AIPS1 */
reg = <0x50000000 0x10000000>;
ranges;
spba@50000000 {
spba-bus@50000000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;

10
arch/arm/boot/dts/imx51.dtsi
View File

@ -48,25 +48,25 @@ tzic: tz-interrupt-controller@e0000000 {
clocks {
ckil {
compatible = "fsl,imx-ckil", "fixed-clock";
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
ckih1 {
compatible = "fsl,imx-ckih1", "fixed-clock";
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
ckih2 {
compatible = "fsl,imx-ckih2", "fixed-clock";
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
osc {
compatible = "fsl,imx-osc", "fixed-clock";
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
@ -178,7 +178,7 @@ bus@70000000 { /* AIPS1 */
reg = <0x70000000 0x10000000>;
ranges;
spba@70000000 {
spba-bus@70000000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;

10
arch/arm/boot/dts/imx53.dtsi
View File

@ -86,25 +86,25 @@ tzic: tz-interrupt-controller@fffc000 {
clocks {
ckil {
compatible = "fsl,imx-ckil", "fixed-clock";
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
ckih1 {
compatible = "fsl,imx-ckih1", "fixed-clock";
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <22579200>;
};
ckih2 {
compatible = "fsl,imx-ckih2", "fixed-clock";
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
osc {
compatible = "fsl,imx-osc", "fixed-clock";
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
@ -229,7 +229,7 @@ bus@50000000 { /* AIPS1 */
reg = <0x50000000 0x10000000>;
ranges;
spba@50000000 {
spba-bus@50000000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;

22
arch/arm/boot/dts/imx6dl-mba6.dtsi Normal file
View File

@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2013 Sascha Hauer, Pengutronix
*
* Copyright 2013-2021 TQ-Systems GmbH
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
*/
&ethphy {
rxdv-skew-ps = <180>;
txen-skew-ps = <0>;
rxd3-skew-ps = <180>;
rxd2-skew-ps = <180>;
rxd1-skew-ps = <180>;
rxd0-skew-ps = <180>;
txd3-skew-ps = <120>;
txd2-skew-ps = <0>;
txd1-skew-ps = <300>;
txd0-skew-ps = <120>;
txc-skew-ps = <1860>;
rxc-skew-ps = <1860>;
};

21
arch/arm/boot/dts/imx6dl-mba6a.dts Normal file
View File

@ -0,0 +1,21 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2013 Sascha Hauer, Pengutronix
*
* Copyright 2013-2021 TQ-Systems GmbH
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "imx6dl-tqma6a.dtsi"
#include "imx6qdl-mba6.dtsi"
#include "imx6qdl-mba6a.dtsi"
#include "imx6dl-mba6.dtsi"
/ {
model = "TQ TQMa6S/DL on MBa6x";
compatible = "tq,imx6dl-mba6x-a", "tq,mba6a",
"tq,imx6dl-tqma6dl-a", "fsl,imx6dl";
};

21
arch/arm/boot/dts/imx6dl-mba6b.dts Normal file
View File

@ -0,0 +1,21 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2013 Sascha Hauer, Pengutronix
*
* Copyright 2013-2021 TQ-Systems GmbH
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "imx6dl-tqma6b.dtsi"
#include "imx6qdl-mba6.dtsi"
#include "imx6qdl-mba6b.dtsi"
#include "imx6dl-mba6.dtsi"
/ {
model = "TQ TQMa6S/DL on MBa6x";
compatible = "tq,imx6dl-mba6x-b", "tq,mba6b",
"tq,imx6dl-tqma6dl-b", "fsl,imx6dl";
};

3
arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts
View File

@ -8,6 +8,9 @@
#include "imx6dl.dtsi"
#include "imx6qdl-phytec-phycore-som.dtsi"
#include "imx6qdl-phytec-mira.dtsi"
#include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
#include "imx6qdl-phytec-mira-peb-av-02.dtsi"
#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi"
/ {
model = "PHYTEC phyBOARD-Mira DualLite/Solo Carrier-Board with NAND";

44
arch/arm/boot/dts/imx6q-mba6.dtsi Normal file
View File

@ -0,0 +1,44 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2013 Sascha Hauer, Pengutronix
*
* Copyright 2013-2021 TQ-Systems GmbH
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
*/
&ecspi5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi5_mba6x>;
cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
};
&ethphy {
rxdv-skew-ps = <180>;
txen-skew-ps = <120>;
rxd3-skew-ps = <180>;
rxd2-skew-ps = <180>;
rxd1-skew-ps = <180>;
rxd0-skew-ps = <180>;
txd3-skew-ps = <120>;
txd2-skew-ps = <0>;
txd1-skew-ps = <180>;
txd0-skew-ps = <360>;
txc-skew-ps = <1860>;
rxc-skew-ps = <1860>;
};
&sata {
status = "okay";
};
&iomuxc {
pinctrl_ecspi5_mba6x: ecspi5grp-mba6x {
fsl,pins = <
/* HYS, SPEED = MED, 100k up, DSE = 011, SRE_FAST */
MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x1b099
MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0xb099
MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0xb099
MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0xb099 /* eCSPI5 SS0 */
>;
};
};

20
arch/arm/boot/dts/imx6q-mba6a.dts Normal file
View File

@ -0,0 +1,20 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2013 Sascha Hauer, Pengutronix
*
* Copyright 2013-2021 TQ-Systems GmbH
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
*/
/dts-v1/;
#include "imx6q-tqma6a.dtsi"
#include "imx6qdl-mba6.dtsi"
#include "imx6qdl-mba6a.dtsi"
#include "imx6q-mba6.dtsi"
/ {
model = "TQ TQMa6Q on MBa6x";
compatible = "tq,imx6q-mba6x-a", "tq,mba6a",
"tq,imx6q-tqma6q-a", "fsl,imx6q";
};

20
arch/arm/boot/dts/imx6q-mba6b.dts Normal file
View File

@ -0,0 +1,20 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2013 Sascha Hauer, Pengutronix
*
* Copyright 2013-2021 TQ-Systems GmbH
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
*/
/dts-v1/;
#include "imx6q-tqma6b.dtsi"
#include "imx6qdl-mba6.dtsi"
#include "imx6qdl-mba6b.dtsi"
#include "imx6q-mba6.dtsi"
/ {
model = "TQ TQMa6Q on MBa6x";
compatible = "tq,imx6q-mba6x-b", "tq,mba6b",
"tq,imx6q-tqma6q-b", "fsl,imx6q";
};

3
arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts
View File

@ -8,6 +8,9 @@
#include "imx6q.dtsi"
#include "imx6qdl-phytec-phycore-som.dtsi"
#include "imx6qdl-phytec-mira.dtsi"
#include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
#include "imx6qdl-phytec-mira-peb-av-02.dtsi"
#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi"
/ {
model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with eMMC";

3
arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts
View File

@ -8,6 +8,9 @@
#include "imx6q.dtsi"
#include "imx6qdl-phytec-phycore-som.dtsi"
#include "imx6qdl-phytec-mira.dtsi"
#include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
#include "imx6qdl-phytec-mira-peb-av-02.dtsi"
#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi"
/ {
model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with NAND";

54
arch/arm/boot/dts/imx6q-yapp4-crux.dts Normal file
View File

@ -0,0 +1,54 @@
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2021 Y Soft Corporation, a.s.
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6dl-yapp4-common.dtsi"
/ {
model = "Y Soft IOTA Crux i.MX6Quad board";
compatible = "ysoft,imx6q-yapp4-crux", "fsl,imx6q";
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0xf0000000>;
};
};
&gpio_oled {
status = "okay";
};
&leds {
status = "okay";
};
&oled_1305 {
status = "okay";
};
&oled_1309 {
status = "okay";
};
&reg_usb_h1_vbus {
status = "okay";
};
&touchkeys {
status = "okay";
};
&uart2 {
status = "disabled";
};
&usbh1 {
status = "okay";
};
&usbphy2 {
status = "okay";
};

4
arch/arm/boot/dts/imx6qdl-dhcom-drc02.dtsi
View File

@ -95,6 +95,10 @@ &uart5 {
rts-gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>; /* GPIO P */
};
&usbh1 {
disable-over-current;
};
&usdhc2 { /* SD card */
status = "okay";
};

4
arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi
View File

@ -260,6 +260,10 @@ &ssi1 {
status = "okay";
};
&usbh1 {
disable-over-current;
};
&usdhc2 { /* SD card */
status = "okay";
};

8
arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi
View File

@ -132,14 +132,15 @@ mdio {
#size-cells = <0>;
ethphy0: ethernet-phy@0 { /* SMSC LAN8710Ai */
compatible = "ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-id0007.c0f0",
"ethernet-phy-ieee802.3-c22";
interrupt-parent = <&gpio4>;
interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&pinctrl_ethphy0>;
pinctrl-names = "default";
reg = <0>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
reset-assert-us = <500>;
reset-deassert-us = <500>;
reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
smsc,disable-energy-detect; /* Make plugin detection reliable */
};
@ -728,6 +729,7 @@ MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x4001b0b1
pinctrl_usbh1: usbh1-grp {
fsl,pins = <
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x120b0
MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b0b1
>;
};

526
arch/arm/boot/dts/imx6qdl-mba6.dtsi Normal file
View File

@ -0,0 +1,526 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2013 Sascha Hauer, Pengutronix
*
* Copyright 2013-2021 TQ-Systems GmbH
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
*/
#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/sound/fsl-imx-audmux.h>
/ {
aliases {
mmc0 = &usdhc3;
mmc1 = &usdhc2;
/delete-property/ mmc2;
/delete-property/ mmc3;
};
chosen {
stdout-path = &uart2;
};
beeper: gpio-beeper {
compatible = "gpio-beeper";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpiobeeper>;
gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
};
gpio_buttons: gpio-buttons {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpiobuttons>;
button1 {
label = "s6";
linux,code = <KEY_F6>;
gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
};
button2 {
label = "s7";
linux,code = <KEY_F7>;
gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
};
button3 {
label = "s8";
linux,code = <KEY_F8>;
gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
};
};
gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpioled>;
led1 {
label = "led1";
gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
};
led2 {
label = "led2";
gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
reg_mba6_3p3v: regulator-mba6-3p3v {
compatible = "regulator-fixed";
regulator-name = "supply-mba6-3p3v";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_pcie: regulator-pcie {
compatible = "regulator-fixed";
regulator-name = "supply-pcie";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
/* PCIE.PWR_EN */
gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
vin-supply = <&reg_mba6_3p3v>;
};
reg_vcc3v3_audio: regulator-vcc3v3-audio {
compatible = "regulator-fixed";
regulator-name = "vcc3v3-audio";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&reg_mba6_3p3v>;
};
sound {
compatible = "fsl,imx-audio-tlv320aic32x4";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
model = "imx-audio-tlv320aic32x4";
ssi-controller = <&ssi1>;
audio-codec = <&tlv320aic32x4>;
audio-asrc = <&asrc>;
audio-routing =
"IN3_L", "Mic Jack",
"Mic Jack", "Mic Bias",
"IN1_L", "Line In Jack",
"IN1_R", "Line In Jack",
"Line Out Jack", "LOL",
"Line Out Jack", "LOR";
mux-int-port = <1>;
mux-ext-port = <3>;
};
};
&audmux {
status = "okay";
ssi0 {
fsl,audmux-port = <MX31_AUDMUX_PORT1_SSI0>;
fsl,port-config = <
(IMX_AUDMUX_V2_PTCR_SYN |
IMX_AUDMUX_V2_PTCR_TFSDIR |
IMX_AUDMUX_V2_PTCR_TFSEL(MX31_AUDMUX_PORT3_SSI_PINS_3) |
IMX_AUDMUX_V2_PTCR_TCLKDIR |
IMX_AUDMUX_V2_PTCR_TCSEL(MX31_AUDMUX_PORT3_SSI_PINS_3))
IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT3_SSI_PINS_3)
>;
};
aud3 {
fsl,audmux-port = <MX31_AUDMUX_PORT3_SSI_PINS_3>;
fsl,port-config = <
IMX_AUDMUX_V2_PTCR_SYN
IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT1_SSI0)
>;
};
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1>;
status = "okay";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can2>;
status = "okay";
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_mba6>;
cs-gpios = <&gpio3 19 0>, <&gpio3 24 0>;
};
&fec {
phy-mode = "rgmii-id";
phy-handle = <&ethphy>;
mac-address = [00 00 00 00 00 00];
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
interrupt-parent = <&gpio1>;
interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
reset-assert-us = <1000>;
reset-deassert-us = <100000>;
micrel,force-master;
max-speed = <1000>;
};
};
};
&i2c1 {
tlv320aic32x4: audio-codec@18 {
compatible = "ti,tlv320aic32x4";
reg = <0x18>;
clocks = <&clks IMX6QDL_CLK_CKO>;
clock-names = "mclk";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_codec>;
ldoin-supply = <&reg_vcc3v3_audio>;
iov-supply = <&reg_mba6_3p3v>;
};
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio6 7 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
&snvs_poweroff {
status = "okay";
};
&ssi1 {
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
uart-has-rtscts;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
uart-has-rtscts;
linux,rs485-enabled-at-boot-time;
rs485-rts-active-low;
rs485-rx-during-tx;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
uart-has-rtscts;
status = "okay";
};
&usbh1 {
disable-over-current;
status = "okay";
};
&usbotg {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
power-active-high;
over-current-active-low;
srp-disable;
hnp-disable;
adp-disable;
dr_mode = "otg";
status = "okay";
};
/* SD card slot */
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
vmmc-supply = <&reg_mba6_3p3v>;
bus-width = <4>;
no-1-8-v;
no-mmc;
no-sdio;
cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog1>;
/* does not work on unmodified starter kit */
/* fsl,ext-reset-output; */
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0
>;
};
pinctrl_can1: can1grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0xb099
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0xb099
>;
};
pinctrl_can2: can2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0xb099
MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0xb099
>;
};
pinctrl_codec: codecgrp {
fsl,pins = <
MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0xb0 /* CLK */
>;
};
pinctrl_ecspi1_mba6: ecspimba6grp {
fsl,pins = <
MX6QDL_PAD_EIM_D24__GPIO3_IO24 0xb099 /* eCSPI1 SS2 */
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
/* FEC phy IRQ */
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x00011008
/* FEC phy reset */
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b099
/* DSE = 100, 100k up, SPEED = MED */
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0xb0a0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0xb0a0
/* DSE = 111, pull 100k up */
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0xb038
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0xb038
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0xb038
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0xb038
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0xb038
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0xb038
/* DSE = 111, pull external */
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x0038
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x0038
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x0038
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x0038
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x0038
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x0038
/* HYS = 1, DSE = 111, 100k up, SPEED = HIGH */
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0f0
>;
};
pinctrl_gpiobeeper: gpiobeepergrp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0xb099
>;
};
pinctrl_gpiobuttons: gpiobuttongrp {
fsl,pins = <
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0001b099
MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b099
MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b099
>;
};
pinctrl_gpioled: gpioledgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0xb099 /* LED V15 */
MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb099 /* LED V16 */
>;
};
pinctrl_hog: hoggrp {
fsl,pins = <
/* LCD.CONTRAST -> Rev 0100 only, not used on Rev.0200*/
MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0001b099
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b099
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b099
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x0001b099
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001b099
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0001b099
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0001b099
MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0001b099
MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0001b099
MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0001b099
MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x0001b099
MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0001b099
MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x0001b099
MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x0001b099
MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0001b099
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0001b099
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b099
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b099
MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0001b099
MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x0001b099
MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x0001b099
MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x0001b099
MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x0001b099
MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0001b099
MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x0001b099
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
/* HYS = 1, DSE = 110, 100k up, SPEED = HIGH (11)*/
MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x001b0f0 /* #PCIE.WAKE */
MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x001b0f0 /* #PCIE.RST */
MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x001b0f0 /* #PCIE.DIS */
/* HYS = 1, DSE = 110, PUE+PKE, SPEED = HIGH (11)*/
MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00130f0 /* PCIE.PWR_EN */
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
/* 100 k PD, DSE 120 OHM, SPPEED LO */
MX6QDL_PAD_GPIO_9__PWM1_OUT 0x00003050
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
/* 100 k PD, DSE 120 OHM, SPPEED LO */
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x00003050
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
/* 100 k PD, DSE 120 OHM, SPPEED LO */
MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x00003050
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b099
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b099
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1
MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x1b0b1
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
/* CLK: 47k Pup SPD_LOW DSE 40Ohm SRE_FAST HYS */
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x00017071
/* SD2: 47k Pup SPD_LOW DSE 80Ohm SRE_FAST HYS */
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x00017059
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017059
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b099 /* usdhc2 CD */
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0001b099 /* usdhc2 WP */
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x0001b0b0
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x00017059
MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x0001b099
>;
};
pinctrl_wdog1: wdog1grp {
fsl,pins = <
/* Watchdog out */
MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x0000b099
>;
};
};

36
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@ -0,0 +1,36 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2013 Sascha Hauer, Pengutronix
*
* Copyright 2013-2021 TQ-Systems GmbH
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
*/
/ {
aliases {
rtc0 = &rtc0;
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>, <&pinctrl_enet_fix>;
};
&i2c1 {
lm75: temperature-sensor@49 {
compatible = "national,lm75";
reg = <0x49>;
};
m24c64_57: eeprom@57 {
compatible = "atmel,24c64";
reg = <0x57>;
pagesize = <32>;
};
rtc0: rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
};
};

52
arch/arm/boot/dts/imx6qdl-mba6b.dtsi Normal file
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@ -0,0 +1,52 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2013 Sascha Hauer, Pengutronix
*
* Copyright 2013-2021 TQ-Systems GmbH
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
*/
/ {
aliases {
rtc0 = &rtc0;
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
};
&i2c3 {
lm75: temperature-sensor@49 {
compatible = "national,lm75";
reg = <0x49>;
};
m24c64_57: eeprom@57 {
compatible = "atmel,24c64";
reg = <0x57>;
pagesize = <32>;
};
rtc0: rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
};
};
&iomuxc {
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b899
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b899
>;
};
};

119
arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi Normal file
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@ -0,0 +1,119 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2018 PHYTEC Messtechnik
* Author: Christian Hemp <c.hemp@phytec.de>
*/
/ {
display: display0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx-parallel-display";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_disp0>;
interface-pix-fmt = "rgb24";
status = "disabled";
port@0 {
reg = <0>;
display0_in: endpoint {
remote-endpoint = <&ipu1_di0_disp0>;
};
};
port@1 {
reg = <1>;
display0_out: endpoint {
remote-endpoint = <&peb_panel_lcd_in>;
};
};
};
panel-lcd {
compatible = "edt,etm0700g0edh6";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_disp0_pwr>;
power-supply = <&reg_display>;
enable-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
backlight = <&backlight>;
status = "disabled";
port {
peb_panel_lcd_in: endpoint {
remote-endpoint = <&display0_out>;
};
};
};
reg_display: regulator-peb-display {
compatible = "regulator-fixed";
regulator-name = "peb-display";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&i2c1 {
edt_ft5x06: touchscreen@38 {
compatible = "edt,edt-ft5406";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_edt_ft5x06>;
reg = <0x38>;
interrupt-parent = <&gpio3>;
interrupts = <2 IRQ_TYPE_NONE>;
status = "disabled";
};
};
&ipu1_di0_disp0 {
remote-endpoint = <&display0_in>;
};
&iomuxc {
pinctrl_disp0: disp0grp {
fsl,pins = <
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x1b080
MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
>;
};
pinctrl_disp0_pwr: disp0pwrgrp {
fsl,pins = <
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
>;
};
pinctrl_edt_ft5x06: edtft5x06grp {
fsl,pins = <
MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0xb0b1
>;
};
};

71
arch/arm/boot/dts/imx6qdl-phytec-mira-peb-eval-01.dtsi Normal file
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@ -0,0 +1,71 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2018 PHYTEC Messtechnik
* Author: Christian Hemp <c.hemp@phytec.de>
*/
#include <dt-bindings/input/input.h>
/ {
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
status = "disabled";
power {
label = "Power Button";
gpios = <&gpio5 28 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WAKEUP>;
wakeup-source;
};
sleep {
label = "Sleep Button";
gpios = <&gpio6 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_SLEEP>;
};
};
user_leds: user-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_user_leds>;
status = "disabled";
user-led1 {
gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "gpio";
default-state = "on";
};
user-led2 {
gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "gpio";
default-state = "on";
};
user-led3 {
gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "gpio";
default-state = "on";
};
};
};
&iomuxc {
pinctrl_gpio_keys: gpiokeysgrp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0
MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x1b0b0
>;
};
pinctrl_user_leds: userledsgrp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0
MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x1b0b0
>;
};
};

85
arch/arm/boot/dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi Normal file
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@ -0,0 +1,85 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2021 PHYTEC Messtechnik GmbH
* Author: Yunus Bas <y.bas@phytec.de>
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
reg_wl_en: regulator-wl-en {
compatible = "regulator-fixed";
regulator-name = "wlan_en";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wl>;
gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <100>;
status = "disabled";
};
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3_bt>;
uart-has-rtscts;
bluetooth {
compatible = "brcm,bcm43438-bt";
shutdown-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
device-wakeup-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
};
&usdhc3 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3_wl>;
vmmc-supply = <&reg_wl_en>;
bus-width = <4>;
non-removable;
no-1-8-v;
status = "disabled";
brmcf: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
};
};
&iomuxc {
pinctrl_uart3_bt: uart3grp-bt {
fsl,pins = <
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0xb0b1 /* BT ENABLE */
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0xb0b1 /* DEV WAKEUP */
MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0xb0b1 /* HOST WAKEUP */
>;
};
pinctrl_usdhc3_wl: usdhc3grp-wl {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
>;
};
pinctrl_wl: wlgrp {
fsl,pins = <
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0xb0b1 /* WLAN ENABLE */
>;
};
};

20
arch/arm/boot/dts/imx6qdl-tqma6a.dtsi
View File

@ -4,6 +4,12 @@
* Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com>
*/
&fec {
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
fsl,err006687-workaround-present;
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
@ -26,3 +32,17 @@ eeprom@50 {
pagesize = <32>;
};
};
&iomuxc {
/*
* This pinmuxing is required for the ERR006687 workaround. Board
* DTS files that enable the FEC controller with
* fsl,err006687-workaround-present must include this group.
*/
pinctrl_enet_fix: enetfixgrp {
fsl,pins = <
/* ENET ping patch */
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
};
};

8
arch/arm/boot/dts/imx6qdl.dtsi
View File

@ -55,19 +55,19 @@ aliases {
clocks {
ckil {
compatible = "fsl,imx-ckil", "fixed-clock";
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
ckih1 {
compatible = "fsl,imx-ckih1", "fixed-clock";
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
osc {
compatible = "fsl,imx-osc", "fixed-clock";
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
@ -481,7 +481,7 @@ asrc: asrc@2034000 {
status = "okay";
};
spba@203c000 {
spba-bus@203c000 {
reg = <0x0203c000 0x4000>;
};
};

18
arch/arm/boot/dts/imx6qp-mba6b.dts Normal file
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@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2015-2021 TQ-Systems GmbH
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "imx6qp-tqma6b.dtsi"
#include "imx6qdl-mba6.dtsi"
#include "imx6qdl-mba6b.dtsi"
#include "imx6q-mba6.dtsi"
/ {
model = "TQ TQMa6QP on MBa6x";
compatible = "tq,imx6qp-mba6x-b", "tq,mba6b",
"tq,imx6qp-tqma6qp-b", "fsl,imx6qp";
};

3
arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts
View File

@ -8,6 +8,9 @@
#include "imx6qp.dtsi"
#include "imx6qdl-phytec-phycore-som.dtsi"
#include "imx6qdl-phytec-mira.dtsi"
#include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
#include "imx6qdl-phytec-mira-peb-av-02.dtsi"
#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi"
/ {
model = "PHYTEC phyBOARD-Mira QuadPlus Carrier-Board with NAND";

54
arch/arm/boot/dts/imx6qp-yapp4-crux-plus.dts Normal file
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@ -0,0 +1,54 @@
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2021 Y Soft Corporation, a.s.
/dts-v1/;
#include "imx6qp.dtsi"
#include "imx6dl-yapp4-common.dtsi"
/ {
model = "Y Soft IOTA Crux+ i.MX6QuadPlus board";
compatible = "ysoft,imx6qp-yapp4-crux-plus", "fsl,imx6qp";
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0xf0000000>;
};
};
&gpio_oled {
status = "okay";
};
&leds {
status = "okay";
};
&oled_1305 {
status = "okay";
};
&oled_1309 {
status = "okay";
};
&reg_usb_h1_vbus {
status = "okay";
};
&touchkeys {
status = "okay";
};
&uart2 {
status = "disabled";
};
&usbh1 {
status = "okay";
};
&usbphy2 {
status = "okay";
};

1
arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
View File

@ -10,6 +10,7 @@
#include "imx6ul-phytec-segin.dtsi"
#include "imx6ul-phytec-segin-peb-eval-01.dtsi"
#include "imx6ul-phytec-segin-peb-av-02.dtsi"
#include "imx6ul-phytec-segin-peb-wlbt-05.dtsi"
/ {
model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with NAND";

90
arch/arm/boot/dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi Normal file
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@ -0,0 +1,90 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2021 PHYTEC Messtechnik GmbH
* Author: Yunus Bas <y.bas@phytec.de>
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
reg_wl_en: regulator-wl-en {
compatible = "regulator-fixed";
regulator-name = "wlan_en";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wl>;
gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <100>;
status = "disabled";
};
};
&iomuxc {
pinctrl_bt: btgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x3031 /* BT ENABLE */
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x3031 /* HOST WAKEUP */
MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x3031 /* DEV WAKEUP */
>;
};
pinctrl_uart2_bt: uart2grp-bt {
fsl,pins = <
MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x17059
MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x17059
MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x17059
MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x17059
>;
};
pinctrl_usdhc2_wl: usdhc2grp-wl {
fsl,pins = <
MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x10051
MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x10061
MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x10051
MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x10051
MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x10051
MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x10051
>;
};
pinctrl_wl: wlgrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x3031 /* WLAN ENABLE */
>;
};
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_bt &pinctrl_bt>;
uart-has-rtscts;
status = "disabled";
bluetooth {
compatible = "brcm,bcm43438-bt";
shutdown-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
device-wakeup-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
};
};
&usdhc2 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2_wl>;
vmmc-supply = <&reg_wl_en>;
bus-width = <4>;
non-removable;
no-1-8-v;
status = "disabled";
brmcf: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
};
};

456
arch/arm/boot/dts/imx6ull-jozacp.dts Normal file
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@ -0,0 +1,456 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2020 Protonic Holland
* Copyright (c) 2020 Oleksij Rempel <kernel@pengutronix.de>, Pengutronix
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include "imx6ull.dtsi"
/ {
model = "JOZ Access Point";
compatible = "joz,jozacp", "fsl,imx6ull";
chosen {
stdout-path = &uart1;
};
/* On board name LED_RGB1 */
led-controller-1 {
compatible = "pwm-leds";
led-0 {
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <0>;
pwms = <&pwm1 0 10000000 0>;
max-brightness = <255>;
};
led-1 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <1>;
pwms = <&pwm3 0 10000000 0>;
max-brightness = <255>;
};
led-2 {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <2>;
pwms = <&pwm5 0 10000000 0>;
max-brightness = <255>;
linux,default-trigger = "heartbeat";
};
};
/* On board name LED_RGB2 */
led-controller-2 {
compatible = "pwm-leds";
led-3 {
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <3>;
pwms = <&pwm2 0 10000000 0>;
max-brightness = <255>;
};
led-4 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <4>;
pwms = <&pwm4 0 10000000 0>;
max-brightness = <255>;
};
led-5 {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <5>;
pwms = <&pwm6 0 10000000 0>;
max-brightness = <255>;
};
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&reg_5v0>;
};
reg_5v0: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_vbus: regulator-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_vbus>;
regulator-name = "vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&reg_5v0>;
gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
usdhc2_wifi_pwrseq: usdhc2-wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wifi_npd>;
reset-gpios = <&gpio4 25 GPIO_ACTIVE_LOW>;
};
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1>;
status = "okay";
};
&cpu0 {
clock-frequency = <792000000>;
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "rmii";
phy-handle = <&ethphy0>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
reg = <0>;
clocks = <&clks IMX6UL_CLK_ENET_REF>;
clock-names = "rmii-ref";
interrupts-extended = <&gpio1 29 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <300>;
};
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clock-frequency = <100000>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clock-frequency = <100000>;
status = "okay";
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
&pwm5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm5>;
status = "okay";
};
&pwm6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm6>;
status = "okay";
};
&snvs_rtc {
status = "disabled";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
dtr-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
uart-has-rtscts;
status = "okay";
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1>;
vbus-supply = <&reg_vbus>;
dr_mode = "host";
over-current-active-low;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
vmmc-supply = <&reg_3v3>;
bus-width = <8>;
no-1-8-v;
non-removable;
cap-mmc-hw-reset;
no-sd;
no-sdio;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
mmc-pwrseq = <&usdhc2_wifi_pwrseq>;
bus-width = <4>;
no-1-8-v;
no-mmc;
no-sd;
non-removable;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_can1: can1grp {
fsl,pins = <
MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b0b0
MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b0b0
>;
};
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x038b0
MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x170b0
>;
};
pinctrl_hog: hoggrp {
fsl,pins = <
/* HW Revision */
MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x1b0b0
MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x1b0b0
/* HW ID */
MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x1b0b0
MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x1b0b0
MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x1b0b0
MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0
/* Digital inputs */
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x11000
MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x11000
MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x11000
MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x11000
MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x11000
/* Isolated outputs */
MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x01020
MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x01020
MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0x01020
MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x01020
MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x01020
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001f8b1
MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001f8b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001f8b1
MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001f8b1
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x01010
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA01__PWM2_OUT 0x01010
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA02__PWM3_OUT 0x01010
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA03__PWM4_OUT 0x01010
>;
};
pinctrl_pwm5: pwm5grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA18__PWM5_OUT 0x01010
>;
};
pinctrl_pwm6: pwm6grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA19__PWM6_OUT 0x01010
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x1b0b0
MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b0
MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS 0x1b0b0
MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS 0x1b0b0
MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x1b0b0
>;
};
pinctrl_usbotg1: usbotg1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x1b0b0
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_NAND_WP_B__USDHC1_RESET_B 0x17099
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x1f099
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10099
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17099
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17099
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17099
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17099
MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17099
MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17099
MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17099
MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17099
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x100b9
MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x170b9
MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x170b9
MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x170b9
MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x170b9
MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x170b9
>;
};
pinctrl_vbus: vbus0grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x030b0
>;
};
pinctrl_wifi_npd: wifigrp {
fsl,pins = <
/* WL_REG_ON */
MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x03020
>;
};
};
&iomuxc_snvs {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_snvs_hog>;
pinctrl_snvs_hog: snvs-hog-grp {
fsl,pins = <
/* Digital outputs */
MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x00020
MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x00020
MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x00020
MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x00020
MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x00020
/* Digital outputs fault feedback */
MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17000
MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17000
MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x17000
MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x17000
MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x17000
>;
};
};

1
arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts
View File

@ -10,6 +10,7 @@
#include "imx6ull-phytec-segin.dtsi"
#include "imx6ull-phytec-segin-peb-eval-01.dtsi"
#include "imx6ull-phytec-segin-peb-av-02.dtsi"
#include "imx6ull-phytec-segin-peb-wlbt-05.dtsi"
/ {
model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with NAND";

1
arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts
View File

@ -9,6 +9,7 @@
#include "imx6ull-phytec-phycore-som.dtsi"
#include "imx6ull-phytec-segin.dtsi"
#include "imx6ull-phytec-segin-peb-eval-01.dtsi"
#include "imx6ull-phytec-segin-peb-wlbt-05.dtsi"
/ {
model = "PHYTEC phyBOARD-Segin i.MX6 ULL Low Cost with NAND";

19
arch/arm/boot/dts/imx6ull-phytec-segin-peb-wlbt-05.dtsi Normal file
View File

@ -0,0 +1,19 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2021 PHYTEC Messtechnik GmbH
* Author: Yunus Bas <y.bas@phytec.de>
*/
#include "imx6ul-phytec-segin-peb-wlbt-05.dtsi"
&iomuxc {
/delete-node/ wlgrp;
};
&iomuxc_snvs {
pinctrl_wl: wlgrp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x3031
>;
};
};

146
arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts Normal file
View File

@ -0,0 +1,146 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2021 BSH Hausgeraete GmbH
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "imx6ulz.dtsi"
/ {
model = "BSH SMM M2";
compatible = "bsh,imx6ulz-bsh-smm-m2", "fsl,imx6ull", "fsl,imx6ulz";
chosen {
stdout-path = &uart4;
};
usdhc2_pwrseq: usdhc2-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>;
};
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "brcm,bcm4330-bt";
max-speed = <3000000>;
shutdown-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
device-wakeup-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
};
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&usbotg1 {
dr_mode = "peripheral";
srp-disable;
hnp-disable;
adp-disable;
status = "okay";
};
&usbphy1 {
fsl,tx-d-cal = <106>;
};
&usdhc2 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wlan>;
bus-width = <4>;
no-1-8-v;
non-removable;
cap-power-off-card;
keep-power-in-suspend;
cap-sdio-irq;
mmc-pwrseq = <&usdhc2_pwrseq>;
status = "okay";
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&gpio1>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake";
};
};
&wdog1 {
status = "okay";
};
&iomuxc {
pinctrl_gpmi_nand: gpmi-nand {
fsl,pins = <
MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b099
MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1
MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b099
MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x79 /* BT_REG_ON */
MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x100b1 /* BT_DEV_WAKE out */
MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x1b0b0 /* BT_HOST_WAKE in */
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1
MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1
>;
};
pinctrl_wlan: wlangrp {
fsl,pins = <
MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059
MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10059
MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059
MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059
MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059
MX6UL_PAD_SD1_DATA3__GPIO2_IO21 0x79 /* WL_REG_ON */
MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x100b1 /* WL_DEV_WAKE - WiFi_GPIO_4 - WiFi FW UART */
MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b1 /* WL_HOST_WAKE - WIFI_GPIO_0 - OOB IRQ */
MX6UL_PAD_ENET1_RX_EN__OSC32K_32K_OUT 0x4001b031 /* OSC 32Khz wifi clk in */
>;
};
};

59
arch/arm/boot/dts/imx7d-remarkable2.dts
View File

@ -34,6 +34,19 @@ reg_brcm: regulator-brcm {
startup-delay-us = <150>;
};
reg_digitizer: regulator-digitizer {
compatible = "regulator-fixed";
regulator-name = "VDD_3V3_DIGITIZER";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_digitizer_reg>;
pinctrl-1 = <&pinctrl_digitizer_reg>;
gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <100000>; /* 100 ms */
};
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
@ -51,6 +64,26 @@ &clks {
assigned-clock-rates = <0>, <32768>;
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
wacom_digitizer: digitizer@9 {
compatible = "hid-over-i2c";
reg = <0x09>;
hid-descr-addr = <0x01>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wacom>;
interrupt-parent = <&gpio1>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
touchscreen-inverted-x;
touchscreen-inverted-y;
vdd-supply = <&reg_digitizer>;
};
};
&snvs_pwrkey {
status = "okay";
};
@ -117,6 +150,25 @@ &wdog1 {
fsl,ext-reset-output;
};
&iomuxc_lpsr {
pinctrl_digitizer_reg: digitizerreggrp {
fsl,pins = <
/* DIGITIZER_PWR_EN */
MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x14
>;
};
pinctrl_wacom: wacomgrp {
fsl,pins = <
/*MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x00000014 FWE */
MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x00000074 /* PDCTB */
MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x00000034 /* WACOM INT */
/*MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x00000014 WACOM PWR ENABLE */
/*MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x00000074 WACOM RESET */
>;
};
};
&iomuxc {
pinctrl_brcm_reg: brcmreggrp {
fsl,pins = <
@ -125,6 +177,13 @@ MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x14
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79

14
arch/arm/boot/dts/imx7s-warp.dts
View File

@ -248,17 +248,17 @@ mpl3115@60 {
&mipi_csi {
clock-frequency = <166000000>;
fsl,csis-hs-settle = <3>;
status = "okay";
port@0 {
reg = <0>;
ports {
port@0 {
reg = <0>;
mipi_from_sensor: endpoint {
remote-endpoint = <&ov2680_to_mipi>;
data-lanes = <1>;
mipi_from_sensor: endpoint {
remote-endpoint = <&ov2680_to_mipi>;
data-lanes = <1>;
};
};
};
};

22
arch/arm/boot/dts/imx7s.dtsi
View File

@ -809,8 +809,6 @@ lcdif: lcdif@30730000 {
mipi_csi: mipi-csi@30750000 {
compatible = "fsl,imx7-mipi-csi2";
reg = <0x30750000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_IPG_ROOT_CLK>,
<&clks IMX7D_MIPI_CSI_ROOT_CLK>,
@ -819,18 +817,22 @@ mipi_csi: mipi-csi@30750000 {
power-domains = <&pgc_mipi_phy>;
phy-supply = <&reg_1p0d>;
resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
reset-names = "mrst";
status = "disabled";
port@0 {
reg = <0>;
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
port@0 {
reg = <0>;
};
mipi_vc0_to_csi_mux: endpoint {
remote-endpoint = <&csi_mux_from_mipi_vc0>;
port@1 {
reg = <1>;
mipi_vc0_to_csi_mux: endpoint {
remote-endpoint = <&csi_mux_from_mipi_vc0>;
};
};
};
};

6
arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
View File

@ -149,7 +149,7 @@ switch1port5: port@5 {
reg = <5>;
label = "dsa";
link = <&switch2port9>;
phy-mode = "rgmii-txid";
phy-mode = "1000base-x";
fixed-link {
speed = <1000>;
@ -211,12 +211,14 @@ port@0 {
reg = <0>;
label = "lan6";
phy-handle = <&switch2phy0>;
phy-mode = "sgmii";
};
port@1 {
reg = <1>;
label = "lan7";
phy-handle = <&switch2phy1>;
phy-mode = "sgmii";
};
port@2 {
@ -252,7 +254,7 @@ fixed-link {
switch2port9: port@9 {
reg = <9>;
label = "dsa";
phy-mode = "rgmii-txid";
phy-mode = "1000base-x";
link = <&switch1port5
&switch0port5>;