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dt-bindings: riscv: Add xsfvfnrclipxfqf ISA extension description

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Add "xsfvfnrclipxfqf" ISA extension which is provided by SiFive for
FP32-to-int8 ranged clip instructions support.

Signed-off-by: Cyan Yang <cyan.yang@sifive.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250418053239.4351-6-cyan.yang@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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Cyan Yang 2025-04-18 13:32:32 +08:00 committed by Palmer Dabbelt
parent 1a6274f035
commit a5a15e07cb
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1 changed files with 6 additions and 0 deletions
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6
Documentation/devicetree/bindings/riscv/extensions.yaml
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@ -675,6 +675,12 @@ properties:
See more details in
https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification
- const: xsfvfnrclipxfqf
description:
SiFive FP32-to-int8 Ranged Clip Instructions Extensions Specification.
See more details in
https://www.sifive.com/document-file/fp32-to-int8-ranged-clip-instructions
# T-HEAD
- const: xtheadvector
description: