From a42ea603594c1d236a9770c5334edb0defeeada5 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 13 Apr 2014 13:41:02 +0200 Subject: [PATCH 01/38] ARM: sun6i: dt: Fixup prcm node name The prcm lives at address 0x01f01400 as the reg entry in its node already correctly indicates, rename the node to match this. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index d45efa74827c..bc46814d2ff0 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -479,14 +479,14 @@ gic: interrupt-controller@01c81000 { interrupts = <1 9 0xf04>; }; + prcm@01f01400 { + compatible = "allwinner,sun6i-a31-prcm"; + reg = <0x01f01400 0x200>; + }; + cpucfg@01f01c00 { compatible = "allwinner,sun6i-a31-cpuconfig"; reg = <0x01f01c00 0x300>; }; - - prcm@01f01c00 { - compatible = "allwinner,sun6i-a31-prcm"; - reg = <0x01f01400 0x200>; - }; }; }; From 60bbe31649ed65643f0b2b910a2d3191d10e7d4e Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 13 Apr 2014 13:41:03 +0200 Subject: [PATCH 02/38] ARM: sun4i: dt: Add address- and size-cells info to i2c controller nodes Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 9174724571e2..fe845ebc27be 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -647,6 +647,8 @@ i2c0: i2c@01c2ac00 { clocks = <&apb1_gates 0>; clock-frequency = <100000>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; i2c1: i2c@01c2b000 { @@ -656,6 +658,8 @@ i2c1: i2c@01c2b000 { clocks = <&apb1_gates 1>; clock-frequency = <100000>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; i2c2: i2c@01c2b400 { @@ -665,6 +669,8 @@ i2c2: i2c@01c2b400 { clocks = <&apb1_gates 2>; clock-frequency = <100000>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; }; }; From a470342e645400e4d05eb52e4488b9d2ca48b19c Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 13 Apr 2014 13:41:04 +0200 Subject: [PATCH 03/38] ARM: sun5i: dt: Add address- and size-cells info to i2c controller nodes Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-a13.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index f01c315bdc4b..d0836d43c28d 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -467,6 +467,8 @@ i2c0: i2c@01c2ac00 { clocks = <&apb1_gates 0>; clock-frequency = <100000>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; i2c1: i2c@01c2b000 { @@ -476,6 +478,8 @@ i2c1: i2c@01c2b000 { clocks = <&apb1_gates 1>; clock-frequency = <100000>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; i2c2: i2c@01c2b400 { @@ -485,6 +489,8 @@ i2c2: i2c@01c2b400 { clocks = <&apb1_gates 2>; clock-frequency = <100000>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; timer@01c60000 { From d1412aed95ad80758a3dc532b368890dd846d39d Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 13 Apr 2014 13:41:05 +0200 Subject: [PATCH 04/38] ARM: sun7i: dt: Add address- and size-cells info to i2c controller nodes Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 32efc105df83..88171f419e35 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -776,6 +776,8 @@ i2c0: i2c@01c2ac00 { clocks = <&apb1_gates 0>; clock-frequency = <100000>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; i2c1: i2c@01c2b000 { @@ -785,6 +787,8 @@ i2c1: i2c@01c2b000 { clocks = <&apb1_gates 1>; clock-frequency = <100000>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; i2c2: i2c@01c2b400 { @@ -794,6 +798,8 @@ i2c2: i2c@01c2b400 { clocks = <&apb1_gates 2>; clock-frequency = <100000>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; i2c3: i2c@01c2b800 { @@ -803,6 +809,8 @@ i2c3: i2c@01c2b800 { clocks = <&apb1_gates 3>; clock-frequency = <100000>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; i2c4: i2c@01c2bc00 { @@ -812,6 +820,8 @@ i2c4: i2c@01c2bc00 { clocks = <&apb1_gates 15>; clock-frequency = <100000>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; gmac: ethernet@01c50000 { From 28240d27d6c6ab1e3c20ec038a7e29a80f6ed614 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 17 Apr 2014 10:29:35 +0200 Subject: [PATCH 05/38] ARM: sun6i: Sort the NMI node by physical address The DT are supposed to be ordered by physical address. Move the NMI node where it belongs. Signed-off-by: Maxime Ripard Acked-by: Arnd Bergmann --- arch/arm/boot/dts/sun6i-a31.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index bc46814d2ff0..5ebf963464b9 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -237,14 +237,6 @@ soc@01c00000 { #size-cells = <1>; ranges; - nmi_intc: interrupt-controller@01f00c0c { - compatible = "allwinner,sun6i-a31-sc-nmi"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x01f00c0c 0x38>; - interrupts = <0 32 4>; - }; - pio: pinctrl@01c20800 { compatible = "allwinner,sun6i-a31-pinctrl"; reg = <0x01c20800 0x400>; @@ -479,6 +471,14 @@ gic: interrupt-controller@01c81000 { interrupts = <1 9 0xf04>; }; + nmi_intc: interrupt-controller@01f00c0c { + compatible = "allwinner,sun6i-a31-sc-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01f00c0c 0x38>; + interrupts = <0 32 4>; + }; + prcm@01f01400 { compatible = "allwinner,sun6i-a31-prcm"; reg = <0x01f01400 0x200>; From d2d878c45371b57a55ac7d51c19a1a4b05ddd40e Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 30 Jan 2014 15:41:23 +0100 Subject: [PATCH 06/38] ARM: sun6i: dt: Add A31 DMA controller to DTSI Now that we have a DMA driver, we can add the DMA bindings in the DTSI for the controller and the devices supported that can use DMA. Signed-off-by: Maxime Ripard Acked-by: Arnd Bergmann --- arch/arm/boot/dts/sun6i-a31.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 5ebf963464b9..b28a55fdf3ce 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -237,6 +237,15 @@ soc@01c00000 { #size-cells = <1>; ranges; + dma: dma-controller@01c02000 { + compatible = "allwinner,sun6i-a31-dma"; + reg = <0x01c02000 0x1000>; + interrupts = <0 50 4>; + clocks = <&ahb1_gates 6>; + resets = <&ahb1_rst 6>; + #dma-cells = <1>; + }; + pio: pinctrl@01c20800 { compatible = "allwinner,sun6i-a31-pinctrl"; reg = <0x01c20800 0x400>; @@ -322,6 +331,8 @@ uart0: serial@01c28000 { reg-io-width = <4>; clocks = <&apb2_gates 16>; resets = <&apb2_rst 16>; + dmas = <&dma 6>, <&dma 6>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -333,6 +344,8 @@ uart1: serial@01c28400 { reg-io-width = <4>; clocks = <&apb2_gates 17>; resets = <&apb2_rst 17>; + dmas = <&dma 7>, <&dma 7>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -344,6 +357,8 @@ uart2: serial@01c28800 { reg-io-width = <4>; clocks = <&apb2_gates 18>; resets = <&apb2_rst 18>; + dmas = <&dma 8>, <&dma 8>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -355,6 +370,8 @@ uart3: serial@01c28c00 { reg-io-width = <4>; clocks = <&apb2_gates 19>; resets = <&apb2_rst 19>; + dmas = <&dma 9>, <&dma 9>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -366,6 +383,8 @@ uart4: serial@01c29000 { reg-io-width = <4>; clocks = <&apb2_gates 20>; resets = <&apb2_rst 20>; + dmas = <&dma 10>, <&dma 10>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -377,6 +396,8 @@ uart5: serial@01c29400 { reg-io-width = <4>; clocks = <&apb2_gates 21>; resets = <&apb2_rst 21>; + dmas = <&dma 22>, <&dma 22>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -426,6 +447,8 @@ spi0: spi@01c68000 { interrupts = <0 65 4>; clocks = <&ahb1_gates 20>, <&spi0_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 23>, <&dma 23>; + dma-names = "rx", "tx"; resets = <&ahb1_rst 20>; status = "disabled"; }; @@ -436,6 +459,8 @@ spi1: spi@01c69000 { interrupts = <0 66 4>; clocks = <&ahb1_gates 21>, <&spi1_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 24>, <&dma 24>; + dma-names = "rx", "tx"; resets = <&ahb1_rst 21>; status = "disabled"; }; @@ -446,6 +471,8 @@ spi2: spi@01c6a000 { interrupts = <0 67 4>; clocks = <&ahb1_gates 22>, <&spi2_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 25>, <&dma 25>; + dma-names = "rx", "tx"; resets = <&ahb1_rst 22>; status = "disabled"; }; @@ -456,6 +483,8 @@ spi3: spi@01c6b000 { interrupts = <0 68 4>; clocks = <&ahb1_gates 23>, <&spi3_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 26>, <&dma 26>; + dma-names = "rx", "tx"; resets = <&ahb1_rst 23>; status = "disabled"; }; From e29ea4d3b2a4c3ae77cffe0658e70cd58de5dc46 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 17 Apr 2014 21:54:41 +0200 Subject: [PATCH 07/38] ARM: sun7i: Add ARM PMU in A20 DTSI Enable the performance monitoring unit found in the A20 SoCs. Signed-off-by: Maxime Ripard Reviewed-by: Hans de Goede --- arch/arm/boot/dts/sun7i-a20.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 88171f419e35..fe626ec579f2 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -57,6 +57,12 @@ timer { <1 10 0xf08>; }; + pmu { + compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; + interrupts = <0 120 4>, + <0 121 4>; + }; + clocks { #address-cells = <1>; #size-cells = <1>; From b5a10b769962072eecf638fda94906fe656036d3 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 17 Apr 2014 21:54:41 +0200 Subject: [PATCH 08/38] ARM: sun6i: Add ARM PMU in A31 DTSI Enable the performance monitoring unit found in the A31 SoCs. Signed-off-by: Maxime Ripard Reviewed-by: Hans de Goede --- arch/arm/boot/dts/sun6i-a31.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index b28a55fdf3ce..22f63e01166e 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -59,6 +59,14 @@ memory { reg = <0x40000000 0x80000000>; }; + pmu { + compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; + interrupts = <0 120 4>, + <0 121 4>, + <0 122 4>, + <0 123 4>; + }; + clocks { #address-cells = <1>; #size-cells = <1>; From 1d5726e9df9c377e65c6c01ee663bea813043c53 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Mon, 28 Apr 2014 18:17:10 +0200 Subject: [PATCH 09/38] ARM: sun4i: dt: add pinmux configuration for the PWM Add the pinctrl descriptions for both PWM channels of the Allwinner A10. Signed-off-by: Alexandre Belloni Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index fe845ebc27be..8810ce459c0f 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -477,6 +477,20 @@ pio: pinctrl@01c20800 { #size-cells = <0>; #gpio-cells = <3>; + pwm0_pins_a: pwm0@0 { + allwinner,pins = "PB2"; + allwinner,function = "pwm"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + pwm1_pins_a: pwm1@0 { + allwinner,pins = "PI3"; + allwinner,function = "pwm"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + uart0_pins_a: uart0@0 { allwinner,pins = "PB22", "PB23"; allwinner,function = "uart0"; From fd7898a2b06a270d97fef0d5dc7bb46be0c3c971 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Mon, 28 Apr 2014 18:17:12 +0200 Subject: [PATCH 10/38] ARM: sun7i: dt: add pinmux configuration for the PWM Add the pinctrl descriptions for both PWM channels of the Allwinner A20. Signed-off-by: Alexandre Belloni Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index fe626ec579f2..3ac8926bde27 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -546,6 +546,20 @@ pio: pinctrl@01c20800 { #size-cells = <0>; #gpio-cells = <3>; + pwm0_pins_a: pwm0@0 { + allwinner,pins = "PB2"; + allwinner,function = "pwm"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + pwm1_pins_a: pwm1@0 { + allwinner,pins = "PI3"; + allwinner,function = "pwm"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + uart0_pins_a: uart0@0 { allwinner,pins = "PB22", "PB23"; allwinner,function = "uart0"; From 4b57a3959cd2b9f7dab949504651cca33c1c35f3 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Mon, 28 Apr 2014 18:17:11 +0200 Subject: [PATCH 11/38] ARM: sun4i: dt: add PWM support Add the PWM bindings for the Allwinner A10. Signed-off-by: Alexandre Belloni Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 8810ce459c0f..4dc376170dd0 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -563,6 +563,14 @@ rtc: rtc@01c20d00 { interrupts = <24>; }; + pwm: pwm@01c20e00 { + compatible = "allwinner,sun4i-a10-pwm"; + reg = <0x01c20e00 0xc>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + sid: eeprom@01c23800 { compatible = "allwinner,sun4i-a10-sid"; reg = <0x01c23800 0x10>; From 8ec40c25139d45e9df385b60b50e5cd36c732464 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Mon, 28 Apr 2014 18:17:13 +0200 Subject: [PATCH 12/38] ARM: sun7i: dt: add PWM support Add the PWM bindings for the Allwinner A20. Signed-off-by: Alexandre Belloni Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 3ac8926bde27..ea62839a5e2f 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -698,6 +698,14 @@ rtc: rtc@01c20d00 { interrupts = <0 24 4>; }; + pwm: pwm@01c20e00 { + compatible = "allwinner,sun7i-a20-pwm"; + reg = <0x01c20e00 0xc>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + sid: eeprom@01c23800 { compatible = "allwinner,sun7i-a20-sid"; reg = <0x01c23800 0x200>; From 96ac3b343d40957b253bbbf8fc81efbdbed9f25d Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Mon, 28 Apr 2014 18:17:14 +0200 Subject: [PATCH 13/38] ARM: sunxi: dt: add PWM support for the cubietruck Enable the PWM for both PWM channels on the cubietruck. They can be found on connector CN8. Signed-off-by: Alexandre Belloni Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index cb25d3c8da58..0c3bd127a5fd 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -63,6 +63,12 @@ led_pins_cubietruck: led_pins@0 { }; }; + pwm: pwm@01c20e00 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins_a>, <&pwm1_pins_a>; + status = "okay"; + }; + uart0: serial@01c28000 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; From 6da50f13a7153c4d55ee8e3ab9d5f7248ff8e3fc Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 26 Apr 2014 12:16:12 +0200 Subject: [PATCH 14/38] ARM: dts: sun5i: Add pin-muxing info for the mmc controllers This adds pin-muxing info for the mmc controller / port combinations which are known to be used on actual boards. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-a10s.dtsi | 14 ++++++++++++++ arch/arm/boot/dts/sun5i-a13.dtsi | 7 +++++++ 2 files changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index 79989ed5658d..9493b2129886 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -451,6 +451,20 @@ i2c2_pins_a: i2c2@0 { allwinner,drive = <0>; allwinner,pull = <0>; }; + + mmc0_pins_a: mmc0@0 { + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; + allwinner,function = "mmc0"; + allwinner,drive = <2>; + allwinner,pull = <0>; + }; + + mmc1_pins_a: mmc1@0 { + allwinner,pins = "PG3","PG4","PG5","PG6","PG7","PG8"; + allwinner,function = "mmc1"; + allwinner,drive = <2>; + allwinner,pull = <0>; + }; }; timer@01c20c00 { diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index d0836d43c28d..dda9df69e033 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -415,6 +415,13 @@ i2c2_pins_a: i2c2@0 { allwinner,drive = <0>; allwinner,pull = <0>; }; + + mmc0_pins_a: mmc0@0 { + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; + allwinner,function = "mmc0"; + allwinner,drive = <2>; + allwinner,pull = <0>; + }; }; timer@01c20c00 { From 9797eb83c85d553dbc062b2953597fb1086649e9 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 26 Apr 2014 12:16:16 +0200 Subject: [PATCH 15/38] ARM: dts: sun6i: Add pin-muxing info for the mmc controllers This adds pin-muxing info for the mmc controller / port combinations which are known to be used on actual boards. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 22f63e01166e..30138cd935d4 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -295,6 +295,13 @@ i2c2_pins_a: i2c2@0 { allwinner,drive = <0>; allwinner,pull = <0>; }; + + mmc0_pins_a: mmc0@0 { + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; + allwinner,function = "mmc0"; + allwinner,drive = <2>; + allwinner,pull = <0>; + }; }; ahb1_rst: reset@01c202c0 { From b258b369e8ec4b6f544265aea52bb74476185b12 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?David=20Lanzend=C3=B6rfer?= Date: Fri, 2 May 2014 17:57:18 +0200 Subject: [PATCH 16/38] ARM: dts: sun4i: Add mmc controller nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add nodes for the 4 mmc controllers found on A10 SoCs to arch/arm/boot/dts/sun4i-a10.dtsi. Signed-off-by: David Lanzendörfer Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 36 ++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 4dc376170dd0..aa7fcedb84aa 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -377,6 +377,42 @@ mdio@01c0b080 { #size-cells = <0>; }; + mmc0: mmc@01c0f000 { + compatible = "allwinner,sun4i-a10-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ahb_gates 8>, <&mmc0_clk>; + clock-names = "ahb", "mmc"; + interrupts = <32>; + status = "disabled"; + }; + + mmc1: mmc@01c10000 { + compatible = "allwinner,sun4i-a10-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ahb_gates 9>, <&mmc1_clk>; + clock-names = "ahb", "mmc"; + interrupts = <33>; + status = "disabled"; + }; + + mmc2: mmc@01c11000 { + compatible = "allwinner,sun4i-a10-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ahb_gates 10>, <&mmc2_clk>; + clock-names = "ahb", "mmc"; + interrupts = <34>; + status = "disabled"; + }; + + mmc3: mmc@01c12000 { + compatible = "allwinner,sun4i-a10-mmc"; + reg = <0x01c12000 0x1000>; + clocks = <&ahb_gates 11>, <&mmc3_clk>; + clock-names = "ahb", "mmc"; + interrupts = <35>; + status = "disabled"; + }; + usbphy: phy@01c13400 { #phy-cells = <1>; compatible = "allwinner,sun4i-a10-usb-phy"; From b5f86a3a719d2defb6b4144f75bfd92342f01aaa Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 2 May 2014 17:57:19 +0200 Subject: [PATCH 17/38] ARM: dts: sun4i: Add pin-muxing info for the mmc0 controller mmc0 is the only controller actually being used on boards, so limit the pin-muxing options to that. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index aa7fcedb84aa..c7b794ed337d 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -579,6 +579,20 @@ emac_pins_a: emac0@0 { allwinner,drive = <0>; allwinner,pull = <0>; }; + + mmc0_pins_a: mmc0@0 { + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; + allwinner,function = "mmc0"; + allwinner,drive = <2>; + allwinner,pull = <0>; + }; + + mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { + allwinner,pins = "PH1"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; }; timer@01c20c00 { From c0955a86f4af4fef7965bfcd41a9642a3f67486b Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 2 May 2014 17:57:20 +0200 Subject: [PATCH 18/38] ARM: dts: sun4i: Enable mmc controller on various A10 boards Tested on a subset of these boards, for the others boards the settings match the ones of the tested boards according to the original firmware fex files. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10-a1000.dts | 9 +++++++++ arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 9 +++++++++ arch/arm/boot/dts/sun4i-a10-hackberry.dts | 9 +++++++++ arch/arm/boot/dts/sun4i-a10-inet97fv2.dts | 9 +++++++++ arch/arm/boot/dts/sun4i-a10-mini-xplus.dts | 9 +++++++++ arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts | 9 +++++++++ arch/arm/boot/dts/sun4i-a10-pcduino.dts | 9 +++++++++ 7 files changed, 63 insertions(+) diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts index fa746aea5e66..93af30699895 100644 --- a/arch/arm/boot/dts/sun4i-a10-a1000.dts +++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts @@ -36,6 +36,15 @@ phy1: ethernet-phy@1 { }; }; + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts index 4684cbe6843b..8581385d277e 100644 --- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts +++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts @@ -34,6 +34,15 @@ phy1: ethernet-phy@1 { }; }; + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts index d7c17e46ce23..9dc7b1c1dd9e 100644 --- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts +++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts @@ -36,6 +36,15 @@ phy0: ethernet-phy@0 { }; }; + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts index fe9272ee55c3..297b8f6b39a3 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts @@ -24,6 +24,15 @@ aliases { }; soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + uart0: serial@01c28000 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts index dd84a9e313b3..b7a4218ef2a4 100644 --- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts +++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts @@ -20,6 +20,15 @@ / { compatible = "pineriver,mini-xplus", "allwinner,sun4i-a10"; soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts index 66cf0c7cf5b7..4b7fd04ea488 100644 --- a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts +++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts @@ -33,6 +33,15 @@ phy1: ethernet-phy@1 { }; }; + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts index 255b47e7019c..4d9c3cdddced 100644 --- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts +++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts @@ -34,6 +34,15 @@ phy1: ethernet-phy@1 { }; }; + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; From d3aed1dfbd2e66ff2eca14897fa141a989a36fb0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?David=20Lanzend=C3=B6rfer?= Date: Fri, 2 May 2014 17:57:21 +0200 Subject: [PATCH 19/38] ARM: dts: sun5i: Add mmc controller nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add nodes for the 3 mmc controllers found on A10s SoCs and for the 2 mmc controllers found on A13 SoCs. Signed-off-by: David Lanzendörfer Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-a10s.dtsi | 27 +++++++++++++++++++++++++++ arch/arm/boot/dts/sun5i-a13.dtsi | 18 ++++++++++++++++++ 2 files changed, 45 insertions(+) diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index 9493b2129886..aa1dd59dc34a 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -338,6 +338,33 @@ mdio@01c0b080 { #size-cells = <0>; }; + mmc0: mmc@01c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ahb_gates 8>, <&mmc0_clk>; + clock-names = "ahb", "mmc"; + interrupts = <32>; + status = "disabled"; + }; + + mmc1: mmc@01c10000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ahb_gates 9>, <&mmc1_clk>; + clock-names = "ahb", "mmc"; + interrupts = <33>; + status = "disabled"; + }; + + mmc2: mmc@01c11000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ahb_gates 10>, <&mmc2_clk>; + clock-names = "ahb", "mmc"; + interrupts = <34>; + status = "disabled"; + }; + usbphy: phy@01c13400 { #phy-cells = <1>; compatible = "allwinner,sun5i-a13-usb-phy"; diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index dda9df69e033..c9fdb7b3ecd9 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -320,6 +320,24 @@ spi1: spi@01c06000 { #size-cells = <0>; }; + mmc0: mmc@01c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ahb_gates 8>, <&mmc0_clk>; + clock-names = "ahb", "mmc"; + interrupts = <32>; + status = "disabled"; + }; + + mmc2: mmc@01c11000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ahb_gates 10>, <&mmc2_clk>; + clock-names = "ahb", "mmc"; + interrupts = <34>; + status = "disabled"; + }; + usbphy: phy@01c13400 { #phy-cells = <1>; compatible = "allwinner,sun5i-a13-usb-phy"; From 31064bbd6dc3d49fe18f97d81e6ef2cb0358c9c8 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 2 May 2014 17:57:22 +0200 Subject: [PATCH 20/38] ARM: dts: sun5i: Enable mmc controller on various A10s and A13 boards The cd pin settings have been taken from the original firmware fex files, and have been confirmed to work on the actual boards. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- .../boot/dts/sun5i-a10s-olinuxino-micro.dts | 32 +++++++++++++++++++ .../boot/dts/sun5i-a13-olinuxino-micro.dts | 16 ++++++++++ arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 16 ++++++++++ 3 files changed, 64 insertions(+) diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts index 23611b71d3aa..de9130848704 100644 --- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts @@ -35,6 +35,24 @@ phy1: ethernet-phy@1 { }; }; + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino_micro>; + bus-width = <4>; + cd-gpios = <&pio 6 1 0>; /* PG1 */ + cd-inverted; + status = "okay"; + }; + + mmc1: mmc@01c10000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>, <&mmc1_cd_pin_olinuxino_micro>; + bus-width = <4>; + cd-gpios = <&pio 6 13 0>; /* PG13 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; @@ -49,6 +67,20 @@ ohci0: usb@01c14400 { }; pinctrl@01c20800 { + mmc0_cd_pin_olinuxino_micro: mmc0_cd_pin@0 { + allwinner,pins = "PG1"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + + mmc1_cd_pin_olinuxino_micro: mmc1_cd_pin@0 { + allwinner,pins = "PG13"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + led_pins_olinuxino: led_pins@0 { allwinner,pins = "PE3"; allwinner,function = "gpio_out"; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts index 11169d5b5b86..8515f19477d2 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts @@ -21,6 +21,15 @@ / { compatible = "olimex,a13-olinuxino-micro", "allwinner,sun5i-a13"; soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxinom>; + bus-width = <4>; + cd-gpios = <&pio 6 0 0>; /* PG0 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; @@ -35,6 +44,13 @@ ohci0: usb@01c14400 { }; pinctrl@01c20800 { + mmc0_cd_pin_olinuxinom: mmc0_cd_pin@0 { + allwinner,pins = "PG0"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + led_pins_olinuxinom: led_pins@0 { allwinner,pins = "PG9"; allwinner,function = "gpio_out"; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts index 7a9187bbeb28..51a943837cb2 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts @@ -20,6 +20,15 @@ / { compatible = "olimex,a13-olinuxino", "allwinner,sun5i-a13"; soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino>; + bus-width = <4>; + cd-gpios = <&pio 6 0 0>; /* PG0 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; @@ -34,6 +43,13 @@ ohci0: usb@01c14400 { }; pinctrl@01c20800 { + mmc0_cd_pin_olinuxino: mmc0_cd_pin@0 { + allwinner,pins = "PG0"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + led_pins_olinuxino: led_pins@0 { allwinner,pins = "PG9"; allwinner,function = "gpio_out"; From adc54c858499436f049cc7252de617314e7bacf2 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 2 May 2014 17:57:23 +0200 Subject: [PATCH 21/38] ARM: dts: sun6i: Add mmc clocks Add clk-nodes for the mmc clocks. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 30138cd935d4..0cbb5404ff13 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -206,6 +206,38 @@ apb2_gates: clk@01c2006c { "apb2_uart4", "apb2_uart5"; }; + mmc0_clk: clk@01c20088 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20088 0x4>; + clocks = <&osc24M>, <&pll6>; + clock-output-names = "mmc0"; + }; + + mmc1_clk: clk@01c2008c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c2008c 0x4>; + clocks = <&osc24M>, <&pll6>; + clock-output-names = "mmc1"; + }; + + mmc2_clk: clk@01c20090 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20090 0x4>; + clocks = <&osc24M>, <&pll6>; + clock-output-names = "mmc2"; + }; + + mmc3_clk: clk@01c20094 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20094 0x4>; + clocks = <&osc24M>, <&pll6>; + clock-output-names = "mmc3"; + }; + spi0_clk: clk@01c200a0 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; From 5b753f0e27da2b0a29142be0833784475bc29366 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 2 May 2014 17:57:24 +0200 Subject: [PATCH 22/38] ARM: dts: sun6i: Add mmc controller nodes Add nodes for the 4 mmc controllers found on A31 SoCs to arch/arm/boot/dts/sun6i-a31.dtsi. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 44 ++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 0cbb5404ff13..eec1afa257a5 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -286,6 +286,50 @@ dma: dma-controller@01c02000 { #dma-cells = <1>; }; + mmc0: mmc@01c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ahb1_gates 8>, <&mmc0_clk>; + clock-names = "ahb", "mmc"; + resets = <&ahb1_rst 8>; + reset-names = "ahb"; + interrupts = <0 60 4>; + status = "disabled"; + }; + + mmc1: mmc@01c10000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ahb1_gates 9>, <&mmc1_clk>; + clock-names = "ahb", "mmc"; + resets = <&ahb1_rst 9>; + reset-names = "ahb"; + interrupts = <0 61 4>; + status = "disabled"; + }; + + mmc2: mmc@01c11000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ahb1_gates 10>, <&mmc2_clk>; + clock-names = "ahb", "mmc"; + resets = <&ahb1_rst 10>; + reset-names = "ahb"; + interrupts = <0 62 4>; + status = "disabled"; + }; + + mmc3: mmc@01c12000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c12000 0x1000>; + clocks = <&ahb1_gates 11>, <&mmc3_clk>; + clock-names = "ahb", "mmc"; + resets = <&ahb1_rst 11>; + reset-names = "ahb"; + interrupts = <0 63 4>; + status = "disabled"; + }; + pio: pinctrl@01c20800 { compatible = "allwinner,sun6i-a31-pinctrl"; reg = <0x01c20800 0x400>; From 0ff1ffd3fe86840c80458ea45c2379014c86b660 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 2 May 2014 17:57:25 +0200 Subject: [PATCH 23/38] ARM: dts: sun6i: Add new sun6i-a31-m9 dts file for Mele M9 Add a new sun6i-a31-m9 dts file for the Mele M9 / Mele A1000G Quad. These HTPCs use the same board in a different case, for more details see: http://linux-sunxi.org/Mele_M9 Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/sun6i-a31-m9.dts | 48 ++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) create mode 100644 arch/arm/boot/dts/sun6i-a31-m9.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 35c146f31e46..1cd137dc69e5 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -351,6 +351,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \ sun5i-a13-olinuxino.dtb \ sun5i-a13-olinuxino-micro.dtb \ sun6i-a31-colombus.dtb \ + sun6i-a31-m9.dtb \ sun7i-a20-cubieboard2.dtb \ sun7i-a20-cubietruck.dtb \ sun7i-a20-olinuxino-micro.dtb diff --git a/arch/arm/boot/dts/sun6i-a31-m9.dts b/arch/arm/boot/dts/sun6i-a31-m9.dts new file mode 100644 index 000000000000..22eacf83997a --- /dev/null +++ b/arch/arm/boot/dts/sun6i-a31-m9.dts @@ -0,0 +1,48 @@ +/* + * Copyright 2014 Hans de Goede + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "sun6i-a31.dtsi" + +/ { + model = "Mele M9 / A1000G Quad top set box"; + compatible = "mele,m9", "allwinner,sun6i-a31"; + + chosen { + bootargs = "earlyprintk console=ttyS0,115200"; + }; + + soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_m9>; + bus-width = <4>; + cd-gpios = <&pio 7 22 0>; /* PH22 */ + cd-inverted; + status = "okay"; + }; + + pio: pinctrl@01c20800 { + mmc0_cd_pin_m9: mmc0_cd_pin@0 { + allwinner,pins = "PH22"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + }; + + uart0: serial@01c28000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; + }; + }; +}; From dd29ce53b2a48bbb29eaa4a0c86a7a5f36c3d9c0 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 2 May 2014 17:57:26 +0200 Subject: [PATCH 24/38] ARM: dts: sun7i: Add mmc controller nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add nodes for the 4 mmc controllers found on A20 SoCs to arch/arm/boot/dts/sun7i-a20.dtsi. Signed-off-by: David Lanzendörfer Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 36 ++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index ea62839a5e2f..e64aa4dd4f39 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -453,6 +453,42 @@ mdio@01c0b080 { #size-cells = <0>; }; + mmc0: mmc@01c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ahb_gates 8>, <&mmc0_clk>; + clock-names = "ahb", "mmc"; + interrupts = <0 32 4>; + status = "disabled"; + }; + + mmc1: mmc@01c10000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ahb_gates 9>, <&mmc1_clk>; + clock-names = "ahb", "mmc"; + interrupts = <0 33 4>; + status = "disabled"; + }; + + mmc2: mmc@01c11000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ahb_gates 10>, <&mmc2_clk>; + clock-names = "ahb", "mmc"; + interrupts = <0 34 4>; + status = "disabled"; + }; + + mmc3: mmc@01c12000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c12000 0x1000>; + clocks = <&ahb_gates 11>, <&mmc3_clk>; + clock-names = "ahb", "mmc"; + interrupts = <0 35 4>; + status = "disabled"; + }; + usbphy: phy@01c13400 { #phy-cells = <1>; compatible = "allwinner,sun7i-a20-usb-phy"; From 11fbedf4dd960db39b40aa59253bb7375df54241 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 2 May 2014 17:57:27 +0200 Subject: [PATCH 25/38] ARM: dts: sun7i: Add pin-muxing info for the mmc controllers This adds pin-muxing info for the mmc controller / port combinations which are known to be used on actual boards. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index e64aa4dd4f39..56df970ffe25 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -709,6 +709,27 @@ spi2_pins_a: spi2@0 { allwinner,drive = <0>; allwinner,pull = <0>; }; + + mmc0_pins_a: mmc0@0 { + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; + allwinner,function = "mmc0"; + allwinner,drive = <2>; + allwinner,pull = <0>; + }; + + mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { + allwinner,pins = "PH1"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + + mmc3_pins_a: mmc3@0 { + allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9"; + allwinner,function = "mmc3"; + allwinner,drive = <2>; + allwinner,pull = <0>; + }; }; timer@01c20c00 { From c621183c203affa526c15e46432c24f31afed997 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 2 May 2014 17:57:28 +0200 Subject: [PATCH 26/38] ARM: dts: sun7i: Enable mmc controller on various A20 boards The cd pin settings have been taken from the original firmware fex files, and have been confirmed to work on the actual boards. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 9 +++++++ arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 9 +++++++ .../boot/dts/sun7i-a20-olinuxino-micro.dts | 25 +++++++++++++++++++ 3 files changed, 43 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts index 68de89ffbdfa..3918e2f6e8ca 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts @@ -20,6 +20,15 @@ / { compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20"; soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index 0c3bd127a5fd..a39f08970b64 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -20,6 +20,15 @@ / { compatible = "cubietech,cubietruck", "allwinner,sun7i-a20"; soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts index eeadf76362fa..1bfef12cf9d1 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts @@ -31,6 +31,24 @@ spi1: spi@01c06000 { status = "okay"; }; + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + + mmc3: mmc@01c12000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_olinuxinom>; + bus-width = <4>; + cd-gpios = <&pio 7 11 0>; /* PH11 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; @@ -65,6 +83,13 @@ ohci1: usb@01c1c400 { }; pinctrl@01c20800 { + mmc3_cd_pin_olinuxinom: mmc3_cd_pin@0 { + allwinner,pins = "PH11"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + led_pins_olinuxino: led_pins@0 { allwinner,pins = "PH2"; allwinner,function = "gpio_out"; From 3906c0a688587408fa37a411d5e79778039e9dc3 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 2 May 2014 17:57:29 +0200 Subject: [PATCH 27/38] ARM: dts: sun7i: Add basic support for the Cubietruck WiFi module The CubieTruck has an AMPAK AP6210 WiFi+Bluetooth module. The WiFi part is a BCM43362 IC connected to MMC3 in the A20 SoC via SDIO. The IC also takes a power enable signal via GPIO. The WiFi module supports out-of-band interrupt signaling via GPIO, but this is not supported in this patch. Signed-off-by: Chen-Yu Tsai Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index a39f08970b64..9dbb763c8e27 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -29,6 +29,14 @@ mmc0: mmc@01c0f000 { status = "okay"; }; + mmc3: mmc@01c12000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins_a>; + vmmc-supply = <®_vmmc3>; + non-removable; + status = "okay"; + }; + usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; @@ -57,6 +65,18 @@ ohci1: usb@01c1c400 { }; pinctrl@01c20800 { + mmc3_pins_a: mmc3@0 { + /* AP6210 requires pull-up */ + allwinner,pull = <1>; + }; + + vmmc3_pin_cubietruck: vmmc3_pin@0 { + allwinner,pins = "PH9"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + ahci_pwr_pin_cubietruck: ahci_pwr_pin@1 { allwinner,pins = "PH12"; allwinner,function = "gpio_out"; @@ -154,4 +174,15 @@ reg_usb1_vbus: usb1-vbus { reg_usb2_vbus: usb2-vbus { status = "okay"; }; + + reg_vmmc3: vmmc3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&vmmc3_pin_cubietruck>; + regulator-name = "vmmc3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pio 7 9 0>; + }; }; From e509e4044b1c2d44abead8ccd152c956890bf5dd Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 11 May 2014 09:46:53 +0200 Subject: [PATCH 28/38] ARM: dts: sunxi: Add reg_vcc3v3 supply to sunxi-common-regulators.dtsi Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sunxi-common-regulators.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/sunxi-common-regulators.dtsi b/arch/arm/boot/dts/sunxi-common-regulators.dtsi index 18eeac0670b9..026bd83f078f 100644 --- a/arch/arm/boot/dts/sunxi-common-regulators.dtsi +++ b/arch/arm/boot/dts/sunxi-common-regulators.dtsi @@ -72,4 +72,11 @@ reg_usb2_vbus: usb2-vbus { gpio = <&pio 7 3 0>; status = "disabled"; }; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; }; From a4da476b6c712bce10beddd342111d346a526caa Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 11 May 2014 09:46:54 +0200 Subject: [PATCH 29/38] ARM: dts: sun4i: Add reg_vcc3v3 to sun4i board mmc nodes Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10-a1000.dts | 1 + arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 1 + arch/arm/boot/dts/sun4i-a10-hackberry.dts | 1 + arch/arm/boot/dts/sun4i-a10-inet97fv2.dts | 1 + arch/arm/boot/dts/sun4i-a10-mini-xplus.dts | 1 + arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts | 1 + arch/arm/boot/dts/sun4i-a10-pcduino.dts | 1 + 7 files changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts index 93af30699895..0b97c071dd56 100644 --- a/arch/arm/boot/dts/sun4i-a10-a1000.dts +++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts @@ -39,6 +39,7 @@ phy1: ethernet-phy@1 { mmc0: mmc@01c0f000 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 0>; /* PH1 */ cd-inverted; diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts index 8581385d277e..c200eacc66e8 100644 --- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts +++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts @@ -37,6 +37,7 @@ phy1: ethernet-phy@1 { mmc0: mmc@01c0f000 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 0>; /* PH1 */ cd-inverted; diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts index 9dc7b1c1dd9e..547fadcb984b 100644 --- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts +++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts @@ -39,6 +39,7 @@ phy0: ethernet-phy@0 { mmc0: mmc@01c0f000 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 0>; /* PH1 */ cd-inverted; diff --git a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts index 297b8f6b39a3..f13723e18b86 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts @@ -27,6 +27,7 @@ soc@01c00000 { mmc0: mmc@01c0f000 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 0>; /* PH1 */ cd-inverted; diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts index b7a4218ef2a4..c01cea50cf0c 100644 --- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts +++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts @@ -23,6 +23,7 @@ soc@01c00000 { mmc0: mmc@01c0f000 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 0>; /* PH1 */ cd-inverted; diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts index 4b7fd04ea488..d46a7dbecef5 100644 --- a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts +++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts @@ -36,6 +36,7 @@ phy1: ethernet-phy@1 { mmc0: mmc@01c0f000 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 0>; /* PH1 */ cd-inverted; diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts index 4d9c3cdddced..fb03bccb78d2 100644 --- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts +++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts @@ -37,6 +37,7 @@ phy1: ethernet-phy@1 { mmc0: mmc@01c0f000 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 0>; /* PH1 */ cd-inverted; From b4d6c77e3c64c1d1c097db1baa9c12126a4f583d Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 11 May 2014 09:46:55 +0200 Subject: [PATCH 30/38] ARM: dts: sun5i: Add reg_vcc3v3 to sun5i board mmc nodes Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 2 ++ arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts | 1 + arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 1 + 3 files changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts index de9130848704..ea9519da5764 100644 --- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts @@ -38,6 +38,7 @@ phy1: ethernet-phy@1 { mmc0: mmc@01c0f000 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino_micro>; + vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 1 0>; /* PG1 */ cd-inverted; @@ -47,6 +48,7 @@ mmc0: mmc@01c0f000 { mmc1: mmc@01c10000 { pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins_a>, <&mmc1_cd_pin_olinuxino_micro>; + vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 13 0>; /* PG13 */ cd-inverted; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts index 8515f19477d2..fa44b026483b 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts @@ -24,6 +24,7 @@ soc@01c00000 { mmc0: mmc@01c0f000 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxinom>; + vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 0 0>; /* PG0 */ cd-inverted; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts index 51a943837cb2..429994e1943e 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts @@ -23,6 +23,7 @@ soc@01c00000 { mmc0: mmc@01c0f000 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino>; + vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 0 0>; /* PG0 */ cd-inverted; From e6879d190d0ccd02d60b24ff9e49c0e105d135a6 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 11 May 2014 09:46:56 +0200 Subject: [PATCH 31/38] ARM: dts: sun6i: Add reg_vcc3v3 to sun6i board mmc nodes Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31-m9.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/sun6i-a31-m9.dts b/arch/arm/boot/dts/sun6i-a31-m9.dts index 22eacf83997a..bc6115da5ae1 100644 --- a/arch/arm/boot/dts/sun6i-a31-m9.dts +++ b/arch/arm/boot/dts/sun6i-a31-m9.dts @@ -11,6 +11,7 @@ /dts-v1/; /include/ "sun6i-a31.dtsi" +/include/ "sunxi-common-regulators.dtsi" / { model = "Mele M9 / A1000G Quad top set box"; @@ -24,6 +25,7 @@ soc@01c00000 { mmc0: mmc@01c0f000 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_m9>; + vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 22 0>; /* PH22 */ cd-inverted; From 0ed9eab3030a337d803a0eaefd70fc254a1ae1c8 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 11 May 2014 09:46:57 +0200 Subject: [PATCH 32/38] ARM: dts: sun7i: Add reg_vcc3v3 to sun7i board mmc nodes Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 1 + arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 1 + arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 2 ++ 3 files changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts index 3918e2f6e8ca..a5ad945197e8 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts @@ -23,6 +23,7 @@ soc@01c00000 { mmc0: mmc@01c0f000 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 0>; /* PH1 */ cd-inverted; diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index 9dbb763c8e27..b7e79d0bf4a7 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -23,6 +23,7 @@ soc@01c00000 { mmc0: mmc@01c0f000 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 0>; /* PH1 */ cd-inverted; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts index 1bfef12cf9d1..b759630bc9a9 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts @@ -34,6 +34,7 @@ spi1: spi@01c06000 { mmc0: mmc@01c0f000 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 0>; /* PH1 */ cd-inverted; @@ -43,6 +44,7 @@ mmc0: mmc@01c0f000 { mmc3: mmc@01c12000 { pinctrl-names = "default"; pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_olinuxinom>; + vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 11 0>; /* PH11 */ cd-inverted; From de806b390f67783791567bb45ea2e57d1b72541e Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 12 May 2014 14:11:06 +0200 Subject: [PATCH 33/38] ARM: dts: sun5i: Add new A10s r7 hdmi tv dongle board The R7 tv-dongle is an A10s based hdmi tv dongle, with 1G RAM, 4G nand flash, and rtl8189es sdio wifi. It has a standard male hdmi connector, an USB host port using an USB-A receptacle and a micro-usb receptacle for both power and USB OTG. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts | 100 ++++++++++++++++++ 2 files changed, 101 insertions(+) create mode 100644 arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 1cd137dc69e5..d44a724c602e 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -348,6 +348,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \ sun4i-a10-olinuxino-lime.dtb \ sun4i-a10-pcduino.dtb \ sun5i-a10s-olinuxino-micro.dtb \ + sun5i-a10s-r7-tv-dongle.dtb \ sun5i-a13-olinuxino.dtb \ sun5i-a13-olinuxino-micro.dtb \ sun6i-a31-colombus.dtb \ diff --git a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts new file mode 100644 index 000000000000..43a93762d4f2 --- /dev/null +++ b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts @@ -0,0 +1,100 @@ +/* + * Copyright 2014 Hans de Goede + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "sun5i-a10s.dtsi" +/include/ "sunxi-common-regulators.dtsi" + +/ { + model = "R7 A10s hdmi tv-stick"; + compatible = "allwinner,r7-tv-dongle", "allwinner,sun5i-a10s"; + + soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_r7>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 6 1 0>; /* PG1 */ + cd-inverted; + status = "okay"; + }; + + mmc1: mmc@01c10000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + status = "okay"; + }; + + usbphy: phy@01c13400 { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; + }; + + ehci0: usb@01c14000 { + status = "okay"; + }; + + ohci0: usb@01c14400 { + status = "okay"; + }; + + pinctrl@01c20800 { + mmc0_cd_pin_r7: mmc0_cd_pin@0 { + allwinner,pins = "PG1"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + + led_pins_r7: led_pins@0 { + allwinner,pins = "PB2"; + allwinner,function = "gpio_out"; + allwinner,drive = <1>; + allwinner,pull = <0>; + }; + + usb1_vbus_pin_r7: usb1_vbus_pin@0 { + allwinner,pins = "PG13"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + }; + + uart0: serial@01c28000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_r7>; + + green { + label = "r7-tv-dongle:green:usr"; + gpios = <&pio 1 2 0>; + default-state = "on"; + }; + }; + + reg_usb1_vbus: usb1-vbus { + pinctrl-0 = <&usb1_vbus_pin_r7>; + gpio = <&pio 6 13 0>; + status = "okay"; + }; +}; From 94a1cd14bf4e361d81fd75714a8a8f2fe48cff9c Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 13 May 2014 17:44:16 +0200 Subject: [PATCH 34/38] ARM: sun6i: Add the USB clocks to the DTSI The USB clocks of the A31 seems to be parented to the 24MHz oscillator, and handle the clocks for the USB phys and OHCI devices. Signed-off-by: Maxime Ripard Reviewed-by: Hans de Goede --- arch/arm/boot/dts/sun6i-a31.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index eec1afa257a5..13aa56ed5858 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -269,6 +269,17 @@ spi3_clk: clk@01c200ac { clocks = <&osc24M>, <&pll6>; clock-output-names = "spi3"; }; + + usb_clk: clk@01c200cc { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-usb-clk"; + reg = <0x01c200cc 0x4>; + clocks = <&osc24M>; + clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2", + "usb_ohci0", "usb_ohci1", + "usb_ohci2"; + }; }; soc@01c00000 { From ef964085e0c96281601c36c2d34d88a16afe217c Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 13 May 2014 17:44:21 +0200 Subject: [PATCH 35/38] ARM: sun6i: dt: Add support for the USB controllers The A31 has two ECHI/OHCI controllers, and one OHCI-only phy-less controller. Signed-off-by: Maxime Ripard Reviewed-by: Hans de Goede --- arch/arm/boot/dts/sun6i-a31.dtsi | 77 ++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 13aa56ed5858..5e9f01af6d99 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -341,6 +341,83 @@ mmc3: mmc@01c12000 { status = "disabled"; }; + usbphy: phy@01c19400 { + compatible = "allwinner,sun6i-a31-usb-phy"; + reg = <0x01c19400 0x10>, + <0x01c1a800 0x4>, + <0x01c1b800 0x4>; + reg-names = "phy_ctrl", + "pmu1", + "pmu2"; + clocks = <&usb_clk 8>, + <&usb_clk 9>, + <&usb_clk 10>; + clock-names = "usb0_phy", + "usb1_phy", + "usb2_phy"; + resets = <&usb_clk 0>, + <&usb_clk 1>, + <&usb_clk 2>; + reset-names = "usb0_reset", + "usb1_reset", + "usb2_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + + ehci0: usb@01c1a000 { + compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; + reg = <0x01c1a000 0x100>; + interrupts = <0 72 4>; + clocks = <&ahb1_gates 26>; + resets = <&ahb1_rst 26>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb@01c1a400 { + compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; + reg = <0x01c1a400 0x100>; + interrupts = <0 73 4>; + clocks = <&ahb1_gates 29>, <&usb_clk 16>; + resets = <&ahb1_rst 29>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci1: usb@01c1b000 { + compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; + reg = <0x01c1b000 0x100>; + interrupts = <0 74 4>; + clocks = <&ahb1_gates 27>; + resets = <&ahb1_rst 27>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci1: usb@01c1b400 { + compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; + reg = <0x01c1b400 0x100>; + interrupts = <0 75 4>; + clocks = <&ahb1_gates 30>, <&usb_clk 17>; + resets = <&ahb1_rst 30>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci2: usb@01c1c000 { + compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; + reg = <0x01c1c400 0x100>; + interrupts = <0 77 4>; + clocks = <&ahb1_gates 31>, <&usb_clk 18>; + resets = <&ahb1_rst 31>; + status = "disabled"; + }; + pio: pinctrl@01c20800 { compatible = "allwinner,sun6i-a31-pinctrl"; reg = <0x01c20800 0x400>; From 8b2b956297c3b27de0ebb8d084afcb30f602eb9f Mon Sep 17 00:00:00 2001 From: Boris BREZILLON Date: Tue, 13 May 2014 17:44:22 +0200 Subject: [PATCH 36/38] ARM: sunxi: dt: add APP4-EVB1 board support The APP4 EVB1 development boards embeds an A31, together with some NAND, one SD card slot, and one SDIO + UART WiFi and Bluetooth chip, a few I2C buses, USB, and a LCD display. Signed-off-by: Boris BREZILLON Signed-off-by: Maxime Ripard Reviewed-by: Hans de Goede --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/sun6i-a31-app4-evb1.dts | 57 +++++++++++++++++++++++ 2 files changed, 58 insertions(+) create mode 100644 arch/arm/boot/dts/sun6i-a31-app4-evb1.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d44a724c602e..efc8cfc0faa1 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -351,6 +351,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \ sun5i-a10s-r7-tv-dongle.dtb \ sun5i-a13-olinuxino.dtb \ sun5i-a13-olinuxino-micro.dtb \ + sun6i-a31-app4-evb1.dtb \ sun6i-a31-colombus.dtb \ sun6i-a31-m9.dtb \ sun7i-a20-cubieboard2.dtb \ diff --git a/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts b/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts new file mode 100644 index 000000000000..2bbf8867362b --- /dev/null +++ b/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts @@ -0,0 +1,57 @@ +/* + * Copyright 2014 Boris Brezillon + * + * Boris Brezillon + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "sun6i-a31.dtsi" +/include/ "sunxi-common-regulators.dtsi" + +/ { + model = "Allwinner A31 APP4 EVB1 Evaluation Board"; + compatible = "allwinner,app4-evb1", "allwinner,sun6i-a31"; + + chosen { + bootargs = "earlyprintk console=ttyS0,115200"; + }; + + soc@01c00000 { + pio: pinctrl@01c20800 { + usb1_vbus_pin_a: usb1_vbus_pin@0 { + allwinner,pins = "PH27"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + }; + + usbphy: phy@01c19400 { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; + }; + + ehci0: usb@01c1a000 { + status = "okay"; + }; + + uart0: serial@01c28000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; + }; + }; + + reg_usb1_vbus: usb1-vbus { + pinctrl-0 = <&usb1_vbus_pin_a>; + gpio = <&pio 7 27 0>; + status = "okay"; + }; +}; From cc08f5e9c10fba240687561590c7c5286679a052 Mon Sep 17 00:00:00 2001 From: Boris BREZILLON Date: Wed, 14 May 2014 14:38:21 +0200 Subject: [PATCH 37/38] ARM: sunxi: dt: add PRCM clk and reset controller subdevices Add DT definitions for PRCM (Power/Reset/Clock Management) clock and reset controller subdevices. Signed-off-by: Boris BREZILLON Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 38 ++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 5e9f01af6d99..90398fa1d0e5 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -690,6 +690,44 @@ nmi_intc: interrupt-controller@01f00c0c { prcm@01f01400 { compatible = "allwinner,sun6i-a31-prcm"; reg = <0x01f01400 0x200>; + + ar100: ar100_clk { + compatible = "allwinner,sun6i-a31-ar100-clk"; + #clock-cells = <0>; + clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; + clock-output-names = "ar100"; + }; + + ahb0: ahb0_clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clocks = <&ar100>; + clock-output-names = "ahb0"; + }; + + apb0: apb0_clk { + compatible = "allwinner,sun6i-a31-apb0-clk"; + #clock-cells = <0>; + clocks = <&ahb0>; + clock-output-names = "apb0"; + }; + + apb0_gates: apb0_gates_clk { + compatible = "allwinner,sun6i-a31-apb0-gates-clk"; + #clock-cells = <1>; + clocks = <&apb0>; + clock-output-names = "apb0_pio", "apb0_ir", + "apb0_timer", "apb0_p2wi", + "apb0_uart", "apb0_1wire", + "apb0_i2c"; + }; + + apb0_rst: apb0_rst { + compatible = "allwinner,sun6i-a31-clock-reset"; + #reset-cells = <1>; + }; }; cpucfg@01f01c00 { From 209394aed532c5de9bf549f4beac92bf1b80f887 Mon Sep 17 00:00:00 2001 From: Boris BREZILLON Date: Tue, 13 May 2014 16:03:03 +0200 Subject: [PATCH 38/38] ARM: sunxi: dt: declare the r_pio pin controller for A31 SoC The A31 SoC has a different pin controller for PL and PM banks. Define this new controller in the device tree. Signed-off-by: Boris BREZILLON Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 90398fa1d0e5..2ad880c0821d 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -734,5 +734,19 @@ cpucfg@01f01c00 { compatible = "allwinner,sun6i-a31-cpuconfig"; reg = <0x01f01c00 0x300>; }; + + r_pio: pinctrl@01f02c00 { + compatible = "allwinner,sun6i-a31-r-pinctrl"; + reg = <0x01f02c00 0x400>; + interrupts = <0 45 4>, + <0 46 4>; + clocks = <&apb0_gates 0>; + resets = <&apb0_rst 0>; + gpio-controller; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + #gpio-cells = <3>; + }; }; };