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drm: renesas: rz-du: mipi_dsi: Add feature flag for 16BPP support

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Introduce the `RZ_MIPI_DSI_FEATURE_16BPP` flag in `rzg2l_mipi_dsi_hw_info`
to indicate support for 16BPP pixel formats. The RZ/V2H(P) SoC supports
16BPP, whereas this feature is missing on the RZ/G2L SoC.

Update the `mipi_dsi_host_attach()` function to check this flag before
allowing 16BPP formats. If the SoC does not support 16BPP, return an error
to prevent incorrect format selection.

This change enables finer-grained format support control for different
SoC variants.

Co-developed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20250609225630.502888-8-prabhakar.mahadev-lad.rj@bp.renesas.com
This commit is contained in:
Lad Prabhakar 2025-06-09 23:56:28 +01:00 committed by Biju Das
parent 7c3fecdd12
commit a56a6b81d8
1 changed files with 11 additions and 0 deletions
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11
drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
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@ -34,6 +34,8 @@
#define RZG2L_DCS_BUF_SIZE 128 /* Maximum DCS buffer size in external memory. */
#define RZ_MIPI_DSI_FEATURE_16BPP BIT(0)
struct rzg2l_mipi_dsi;
struct rzg2l_mipi_dsi_hw_info {
@ -43,6 +45,7 @@ struct rzg2l_mipi_dsi_hw_info {
u32 link_reg_offset;
unsigned long min_dclk;
unsigned long max_dclk;
u8 features;
};
struct rzg2l_mipi_dsi {
@ -672,8 +675,16 @@ static int rzg2l_mipi_dsi_host_attach(struct mipi_dsi_host *host,
switch (mipi_dsi_pixel_format_to_bpp(device->format)) {
case 24:
break;
case 18:
break;
case 16:
if (!(dsi->info->features & RZ_MIPI_DSI_FEATURE_16BPP)) {
dev_err(dsi->dev, "Unsupported format 0x%04x\n",
device->format);
return -EINVAL;
}
break;
default:
dev_err(dsi->dev, "Unsupported format 0x%04x\n", device->format);
return -EINVAL;