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drm/amd/display: Move ntuple to insert entry

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Move get_optimal_ntuple to the FPU code and call it inside
insert_entry_into_table_sorted.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rodrigo Siqueira 2022-07-08 11:55:39 -04:00 committed by Alex Deucher
parent 5b4ee98713
commit a4f8f294fe
2 changed files with 25 additions and 28 deletions
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28
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
View File

@ -1955,29 +1955,6 @@ void dcn32_calculate_wm_and_dlg(struct dc *dc, struct dc_state *context,
DC_FP_END();
}
static void get_optimal_ntuple(struct _vcs_dpi_voltage_scaling_st *entry)
{
if (entry->dcfclk_mhz > 0) {
float bw_on_sdp = entry->dcfclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100);
entry->fabricclk_mhz = bw_on_sdp / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100));
entry->dram_speed_mts = bw_on_sdp / (dcn3_2_soc.num_chans *
dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100));
} else if (entry->fabricclk_mhz > 0) {
float bw_on_fabric = entry->fabricclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100);
entry->dcfclk_mhz = bw_on_fabric / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100));
entry->dram_speed_mts = bw_on_fabric / (dcn3_2_soc.num_chans *
dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100));
} else if (entry->dram_speed_mts > 0) {
float bw_on_dram = entry->dram_speed_mts * dcn3_2_soc.num_chans *
dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100);
entry->fabricclk_mhz = bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100));
entry->dcfclk_mhz = bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100));
}
}
static void remove_entry_from_table_at_index(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries,
unsigned int index)
{
@ -2061,7 +2038,6 @@ static int build_synthetic_soc_states(struct clk_bw_params *bw_params,
entry.fabricclk_mhz = 0;
entry.dram_speed_mts = 0;
get_optimal_ntuple(&entry);
DC_FP_START();
insert_entry_into_table_sorted(table, num_entries, &entry);
DC_FP_END();
@ -2072,7 +2048,6 @@ static int build_synthetic_soc_states(struct clk_bw_params *bw_params,
entry.fabricclk_mhz = 0;
entry.dram_speed_mts = 0;
get_optimal_ntuple(&entry);
DC_FP_START();
insert_entry_into_table_sorted(table, num_entries, &entry);
DC_FP_END();
@ -2083,7 +2058,6 @@ static int build_synthetic_soc_states(struct clk_bw_params *bw_params,
entry.fabricclk_mhz = 0;
entry.dram_speed_mts = bw_params->clk_table.entries[i].memclk_mhz * 16;
get_optimal_ntuple(&entry);
DC_FP_START();
insert_entry_into_table_sorted(table, num_entries, &entry);
DC_FP_END();
@ -2096,7 +2070,6 @@ static int build_synthetic_soc_states(struct clk_bw_params *bw_params,
entry.fabricclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
entry.dram_speed_mts = 0;
get_optimal_ntuple(&entry);
DC_FP_START();
insert_entry_into_table_sorted(table, num_entries, &entry);
DC_FP_END();
@ -2108,7 +2081,6 @@ static int build_synthetic_soc_states(struct clk_bw_params *bw_params,
entry.fabricclk_mhz = max_fclk_mhz;
entry.dram_speed_mts = 0;
get_optimal_ntuple(&entry);
DC_FP_START();
insert_entry_into_table_sorted(table, num_entries, &entry);
DC_FP_END();

25
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
View File

@ -353,6 +353,29 @@ static float calculate_net_bw_in_kbytes_sec(struct _vcs_dpi_voltage_scaling_st *
return limiting_bw_kbytes_sec;
}
static void get_optimal_ntuple(struct _vcs_dpi_voltage_scaling_st *entry)
{
if (entry->dcfclk_mhz > 0) {
float bw_on_sdp = entry->dcfclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100);
entry->fabricclk_mhz = bw_on_sdp / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100));
entry->dram_speed_mts = bw_on_sdp / (dcn3_2_soc.num_chans *
dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100));
} else if (entry->fabricclk_mhz > 0) {
float bw_on_fabric = entry->fabricclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100);
entry->dcfclk_mhz = bw_on_fabric / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100));
entry->dram_speed_mts = bw_on_fabric / (dcn3_2_soc.num_chans *
dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100));
} else if (entry->dram_speed_mts > 0) {
float bw_on_dram = entry->dram_speed_mts * dcn3_2_soc.num_chans *
dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100);
entry->fabricclk_mhz = bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100));
entry->dcfclk_mhz = bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100));
}
}
void insert_entry_into_table_sorted(struct _vcs_dpi_voltage_scaling_st *table,
unsigned int *num_entries,
struct _vcs_dpi_voltage_scaling_st *entry)
@ -363,6 +386,8 @@ void insert_entry_into_table_sorted(struct _vcs_dpi_voltage_scaling_st *table,
dc_assert_fp_enabled();
get_optimal_ntuple(entry);
if (*num_entries == 0) {
table[0] = *entry;
(*num_entries)++;