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phy/rockchip: inno-dsidphy: add LVDS/TTL support
Change-Id: I9ae338ebd3afcd56a1dc4ed9e15347b48507c5e1 Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
This commit is contained in:
Guochun Huang
Tao Huang
parent
022001e45d
commit
a4bbfc35fd
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@ -94,6 +94,13 @@
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#define SAMPLE_CLOCK_DIRECTION_MASK BIT(4)
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#define SAMPLE_CLOCK_DIRECTION_REVERSE BIT(4)
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#define SAMPLE_CLOCK_DIRECTION_FORWARD 0
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#define LOWFRE_EN_MASK BIT(5)
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#define PLL_OUTPUT_FREQUENCY_DIV_BY_1 0
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#define PLL_OUTPUT_FREQUENCY_DIV_BY_2 1
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/* Analog Register Part: reg1e */
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#define PLL_MODE_SEL_MASK GENMASK(6, 5)
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#define PLL_MODE_SEL_LVDS_MODE 0
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#define PLL_MODE_SEL_MIPI_MODE BIT(5)
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/* Analog Register Part: reg0b */
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#define CLOCK_LANE_VOD_RANGE_SET_MASK GENMASK(3, 0)
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#define CLOCK_LANE_VOD_RANGE_SET(x) UPDATE(x, 3, 0)
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@ -211,7 +218,6 @@ struct inno_dsidphy {
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void __iomem *phy_base;
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void __iomem *host_base;
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struct reset_control *rst;
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enum phy_mode mode;
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struct phy_configure_opts_mipi_dphy dphy_cfg;
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unsigned int lanes;
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const struct inno_dsidphy_plat_data *pdata;
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@ -297,6 +303,17 @@ static void phy_update_bits(struct inno_dsidphy *inno,
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writel(tmp, inno->phy_base + reg);
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}
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static void host_update_bits(struct inno_dsidphy *inno,
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u32 reg, u32 mask, u32 val)
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{
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unsigned int tmp, orig;
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orig = readl(inno->host_base + reg);
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tmp = orig & ~mask;
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tmp |= val & mask;
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writel(tmp, inno->host_base + reg);
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}
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static unsigned long inno_dsidphy_pll_calc_rate(struct inno_dsidphy *inno,
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unsigned long rate)
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{
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@ -602,8 +619,9 @@ static void inno_dsidphy_lvds_mode_enable(struct inno_dsidphy *inno)
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/* Sample clock reverse direction */
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phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08,
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SAMPLE_CLOCK_DIRECTION_MASK,
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SAMPLE_CLOCK_DIRECTION_REVERSE);
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SAMPLE_CLOCK_DIRECTION_MASK | LOWFRE_EN_MASK,
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SAMPLE_CLOCK_DIRECTION_REVERSE |
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PLL_OUTPUT_FREQUENCY_DIV_BY_1);
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/* Select LVDS mode */
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phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
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@ -623,6 +641,10 @@ static void inno_dsidphy_lvds_mode_enable(struct inno_dsidphy *inno)
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msleep(20);
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/* Select PLL mode */
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phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1e,
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PLL_MODE_SEL_MASK, PLL_MODE_SEL_LVDS_MODE);
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/* Reset LVDS digital logic */
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phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
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LVDS_DIGITAL_INTERNAL_RESET_MASK,
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@ -642,9 +664,36 @@ static void inno_dsidphy_lvds_mode_enable(struct inno_dsidphy *inno)
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LVDS_DATA_LANE2_EN | LVDS_DATA_LANE3_EN);
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}
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static void inno_dsidphy_phy_ttl_mode_enable(struct inno_dsidphy *inno)
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{
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/* Select TTL mode */
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phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
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MODE_ENABLE_MASK, TTL_MODE_ENABLE);
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/* Reset digital logic */
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phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
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LVDS_DIGITAL_INTERNAL_RESET_MASK,
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LVDS_DIGITAL_INTERNAL_RESET_ENABLE);
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udelay(1);
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phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
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LVDS_DIGITAL_INTERNAL_RESET_MASK,
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LVDS_DIGITAL_INTERNAL_RESET_DISABLE);
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/* Enable digital logic */
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phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
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LVDS_DIGITAL_INTERNAL_ENABLE_MASK,
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LVDS_DIGITAL_INTERNAL_ENABLE);
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/* Enable analog driver */
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phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
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LVDS_LANE_EN_MASK, LVDS_CLK_LANE_EN |
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LVDS_DATA_LANE0_EN | LVDS_DATA_LANE1_EN |
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LVDS_DATA_LANE2_EN | LVDS_DATA_LANE3_EN);
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/* Enable for clk lane in TTL mode */
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host_update_bits(inno, DSI_PHY_RSTZ, PHY_ENABLECLK, PHY_ENABLECLK);
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}
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static int inno_dsidphy_power_on(struct phy *phy)
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{
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struct inno_dsidphy *inno = phy_get_drvdata(phy);
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enum phy_mode mode = phy_get_mode(phy);
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clk_prepare_enable(inno->pclk_phy);
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clk_prepare_enable(inno->ref_clk);
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@ -657,7 +706,7 @@ static int inno_dsidphy_power_on(struct phy *phy)
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phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
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POWER_WORK_MASK, POWER_WORK_ENABLE);
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switch (inno->mode) {
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switch (mode) {
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case PHY_MODE_MIPI_DPHY:
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inno_dsidphy_mipi_mode_enable(inno);
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break;
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@ -665,7 +714,7 @@ static int inno_dsidphy_power_on(struct phy *phy)
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inno_dsidphy_lvds_mode_enable(inno);
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break;
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default:
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return -EINVAL;
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inno_dsidphy_phy_ttl_mode_enable(inno);
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}
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return 0;
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@ -702,17 +751,6 @@ static int inno_dsidphy_power_off(struct phy *phy)
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static int inno_dsidphy_set_mode(struct phy *phy, enum phy_mode mode,
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int submode)
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{
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struct inno_dsidphy *inno = phy_get_drvdata(phy);
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switch (mode) {
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case PHY_MODE_MIPI_DPHY:
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case PHY_MODE_LVDS:
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inno->mode = mode;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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@ -721,9 +759,10 @@ static int inno_dsidphy_configure(struct phy *phy,
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{
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struct inno_dsidphy *inno = phy_get_drvdata(phy);
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struct phy_configure_opts_mipi_dphy *cfg = &inno->dphy_cfg;
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enum phy_mode mode = phy_get_mode(phy);
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int ret;
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if (inno->mode != PHY_MODE_MIPI_DPHY)
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if (mode != PHY_MODE_MIPI_DPHY)
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return -EINVAL;
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ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy);
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@ -753,6 +792,7 @@ static int inno_dsidphy_probe(struct platform_device *pdev)
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struct inno_dsidphy *inno;
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struct phy_provider *phy_provider;
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struct phy *phy;
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struct resource *res;
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int ret;
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inno = devm_kzalloc(dev, sizeof(*inno), GFP_KERNEL);
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@ -763,10 +803,20 @@ static int inno_dsidphy_probe(struct platform_device *pdev)
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inno->pdata = of_device_get_match_data(inno->dev);
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platform_set_drvdata(pdev, inno);
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inno->phy_base = devm_platform_ioremap_resource(pdev, 0);
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inno->phy_base = devm_platform_ioremap_resource_byname(pdev, "phy");
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if (IS_ERR(inno->phy_base))
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return PTR_ERR(inno->phy_base);
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "host");
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if (!res) {
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dev_err(dev, "invalid host resource\n");
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return -EINVAL;
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}
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inno->host_base = devm_ioremap(dev, res->start, resource_size(res));
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if (IS_ERR(inno->host_base))
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return PTR_ERR(inno->host_base);
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inno->ref_clk = devm_clk_get(dev, "ref");
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if (IS_ERR(inno->ref_clk)) {
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ret = PTR_ERR(inno->ref_clk);
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@ -781,6 +831,13 @@ static int inno_dsidphy_probe(struct platform_device *pdev)
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return ret;
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}
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inno->pclk_host = devm_clk_get(dev, "pclk_host");
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if (IS_ERR(inno->pclk_host)) {
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ret = PTR_ERR(inno->pclk_host);
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dev_err(dev, "failed to get host pclk: %d\n", ret);
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return ret;
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}
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inno->rst = devm_reset_control_get(dev, "apb");
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if (IS_ERR(inno->rst)) {
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ret = PTR_ERR(inno->rst);
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