From a49c84d6fd58c416a5b4bcc363e915b3eddc7750 Mon Sep 17 00:00:00 2001 From: Ce Sun Date: Fri, 23 Jan 2026 14:53:39 +0800 Subject: [PATCH] drm/amdgpu: retire mmhub v1.8 ACA support retire mmhub v1.8 ACA support Reviewed-by: Hawking Zhang Signed-off-by: Ce Sun Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c | 92 ------------------------- 1 file changed, 92 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c index cc688ae79e84..2a6a5ac4f374 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c @@ -772,100 +772,8 @@ static const struct amdgpu_ras_block_hw_ops mmhub_v1_8_ras_hw_ops = { .reset_ras_error_count = mmhub_v1_8_reset_ras_error_count, }; -static int mmhub_v1_8_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, - enum aca_smu_type type, void *data) -{ - struct aca_bank_info info; - u64 misc0; - int ret; - - ret = aca_bank_info_decode(bank, &info); - if (ret) - return ret; - - misc0 = bank->regs[ACA_REG_IDX_MISC0]; - switch (type) { - case ACA_SMU_TYPE_UE: - bank->aca_err_type = ACA_ERROR_TYPE_UE; - ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_UE, - 1ULL); - break; - case ACA_SMU_TYPE_CE: - bank->aca_err_type = ACA_ERROR_TYPE_CE; - ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, - ACA_REG__MISC0__ERRCNT(misc0)); - break; - default: - return -EINVAL; - } - - return ret; -} - -/* reference to smu driver if header file */ -static int mmhub_v1_8_err_codes[] = { - 0, 1, 2, 3, 4, /* CODE_DAGB0 - 4 */ - 5, 6, 7, 8, 9, /* CODE_EA0 - 4 */ - 10, /* CODE_UTCL2_ROUTER */ - 11, /* CODE_VML2 */ - 12, /* CODE_VML2_WALKER */ - 13, /* CODE_MMCANE */ -}; - -static bool mmhub_v1_8_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, - enum aca_smu_type type, void *data) -{ - u32 instlo; - - instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); - instlo &= GENMASK(31, 1); - - if (instlo != mmSMNAID_AID0_MCA_SMU) - return false; - - if (aca_bank_check_error_codes(handle->adev, bank, - mmhub_v1_8_err_codes, - ARRAY_SIZE(mmhub_v1_8_err_codes))) - return false; - - return true; -} - -static const struct aca_bank_ops mmhub_v1_8_aca_bank_ops = { - .aca_bank_parser = mmhub_v1_8_aca_bank_parser, - .aca_bank_is_valid = mmhub_v1_8_aca_bank_is_valid, -}; - -static const struct aca_info mmhub_v1_8_aca_info = { - .hwip = ACA_HWIP_TYPE_SMU, - .mask = ACA_ERROR_UE_MASK, - .bank_ops = &mmhub_v1_8_aca_bank_ops, -}; - -static int mmhub_v1_8_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) -{ - int r; - - r = amdgpu_ras_block_late_init(adev, ras_block); - if (r) - return r; - - r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__MMHUB, - &mmhub_v1_8_aca_info, NULL); - if (r) - goto late_fini; - - return 0; - -late_fini: - amdgpu_ras_block_late_fini(adev, ras_block); - - return r; -} - struct amdgpu_mmhub_ras mmhub_v1_8_ras = { .ras_block = { .hw_ops = &mmhub_v1_8_ras_hw_ops, - .ras_late_init = mmhub_v1_8_ras_late_init, }, };