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Subject: [PATCH v6 0/7] ASoC: qcom and pinctrl: add LPASS LPR voting and Hawi LPASS LPI support

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Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com> says:

This series adds support for LPASS low-power resource (LPR) voting
through PRM and introduces LPASS LPI TLMM pinctrl support for newer
platforms such as Hawi.

On such platforms, LPASS requires LPR resource voting via PRM to keep
the subsystem active. This is handled by adding a new clock ID and
support for PARAM_ID_RSC_CPU_LPR in q6prm.

Additionally, a new LPASS LPI TLMM block is introduced, requiring a
dedicated DT binding and pinctrl driver.

Link: https://patch.msgid.link/20260724141708.2212057-1-prasad.kumpatla@oss.qualcomm.com
This commit is contained in:
Mark Brown 2026-08-01 00:07:31 +01:00
commit a452f59ed4
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GPG Key ID: 24D68B725D5487D0
5 changed files with 18 additions and 4 deletions
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1
include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h
View File

@ -236,6 +236,7 @@
#define LPASS_HW_AVTIMER_VOTE 101
#define LPASS_HW_MACRO_VOTE 102
#define LPASS_HW_DCODEC_VOTE 103
#define LPASS_HW_LPR_VOTE 104
#define LPASS_CLK_ATTRIBUTE_INVALID 0x0
#define LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1

2
sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.c
View File

@ -12,7 +12,7 @@
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
#include "q6dsp-lpass-clocks.h"
#define Q6DSP_MAX_CLK_ID 104
#define Q6DSP_MAX_CLK_ID 105
#define Q6DSP_LPASS_CLK_ROOT_DEFAULT 0

2
sound/soc/qcom/qdsp6/q6prm-clocks.c
View File

@ -63,6 +63,8 @@ static const struct q6dsp_clk_init q6prm_clks[] = {
"LPASS_HW_MACRO"),
Q6DSP_VOTE_CLK(LPASS_HW_DCODEC_VOTE, Q6PRM_HW_CORE_ID_DCODEC,
"LPASS_HW_DCODEC"),
Q6DSP_VOTE_CLK(LPASS_HW_LPR_VOTE, Q6PRM_HW_LPR_VOTE,
"LPASS_HW_LPR_VOTE"),
};
static const struct q6dsp_clk_desc q6dsp_clk_q6prm __maybe_unused = {

16
sound/soc/qcom/qdsp6/q6prm.c
View File

@ -31,10 +31,16 @@ struct q6prm {
#define PARAM_ID_RSC_HW_CORE 0x08001032
#define PARAM_ID_RSC_LPASS_CORE 0x0800102B
#define PARAM_ID_RSC_AUDIO_HW_CLK 0x0800102C
#define PARAM_ID_RSC_CPU_LPR 0x08001A6E
#define LPR_CPU_SS_SLEEP_DISABLE 0x1
struct prm_cmd_request_hw_core {
struct apm_module_param_data param_data;
uint32_t hw_clk_id;
union {
u32 hw_clk_id;
u32 lpr_state;
};
} __packed;
struct prm_cmd_request_rsc {
@ -62,6 +68,7 @@ static int q6prm_set_hw_core_req(struct device *dev, uint32_t hw_block_id, bool
struct prm_cmd_request_hw_core *req;
gpr_device_t *gdev = prm->gdev;
uint32_t opcode, rsp_opcode;
bool lpr_req = (hw_block_id == Q6PRM_HW_LPR_VOTE);
if (enable) {
opcode = PRM_CMD_REQUEST_HW_RSC;
@ -82,10 +89,13 @@ static int q6prm_set_hw_core_req(struct device *dev, uint32_t hw_block_id, bool
param_data->module_instance_id = GPR_PRM_MODULE_IID;
param_data->error_code = 0;
param_data->param_id = PARAM_ID_RSC_HW_CORE;
param_data->param_id = lpr_req ? PARAM_ID_RSC_CPU_LPR : PARAM_ID_RSC_HW_CORE;
param_data->param_size = sizeof(*req) - APM_MODULE_PARAM_DATA_SIZE;
req->hw_clk_id = hw_block_id;
if (lpr_req)
req->lpr_state = LPR_CPU_SS_SLEEP_DISABLE;
else
req->hw_clk_id = hw_block_id;
return q6prm_send_cmd_sync(prm, pkt, rsp_opcode);
}

1
sound/soc/qcom/qdsp6/q6prm.h
View File

@ -90,6 +90,7 @@
#define Q6PRM_LPASS_CLK_ROOT_DEFAULT 0
#define Q6PRM_HW_CORE_ID_LPASS 1
#define Q6PRM_HW_CORE_ID_DCODEC 2
#define Q6PRM_HW_LPR_VOTE 3
int q6prm_set_lpass_clock(struct device *dev, int clk_id, int clk_attr,
int clk_root, unsigned int freq);