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Qualcomm Arm64 DeviceTree updates for v6.18

Browse Source 
Add support for Lenovo Thinkbook 16, Dell Inspiron 7441, Dell Latitude
 7455, Samsung Galaxy S20, Billion Capture+, the Monaco EVK and the
 Lemans EVK.
 
 The SDM845 Cheza development boards are removed, as they are not longer
 in use.
 
 For IPQ5018 crypto, tsens, rng, SPI NAND support is dded, the two MDIO
 buses are added and the internal GE PHY.
 
 IPQ5424 gets CPU frequency scaling and a missing UART.
 
 The SA8775P SoC is remaned Lemans, to reduce confusion about the chip
 name. The IoT memory map introduced and made the default, GDSP FastRPC
 and GPR nodes are added.
 
 Touch keys are enabled on the BQ Aquaris X5 Plus.
 
 On QCM2290 the video accelerator is enabled, so is HS timing modes for
 eMMC.
 
 The QCS615 platform is renamed SM6150. CPU frequency scaling and the WiFi
 PCIe controller is introduced.
 
 On Monaco (QCS8300) scaling of L3 and DDR bandwidth is introduced. So is
 eMMC support and generic packer router (GPR).
 
 On the Monaco Ride board, the eMMC controller is enabled.
 
 On QRB220 RB1, the venus video accelerator is enabled.
 
 For SC7280 the first PCIe controller and PHY is introduced. SoundWire,
 LPASS, and USB offload support is added, the codecs and sound card is
 then described on the QCM6490 IDP. The MDSS core reset is introduced, to
 clear bootloader configuration on SC7280-based devices.
 On Fairphone5, USB audio offload is added.
 
 AudioReach support on SC7280 (QCS6490) is introduced and used to
 enable sound on the RB3Gen2 board.
 
 The video clock controller is added to SC8180X.
 
 On SC8280XP the GPI DMA controllers are described and enabled.
 
 Display and GPU is enabled for the Fairphone 3 and charging is enabled
 on the Google Pixel 3a.
 
 The routing for the second USB connector on the Lenovo Yoga C630 is
 described.
 
 On SM6150 ADSP and CDSP FastRPC is introduced, as is the video
 encoder/decoder (venus).
 
 On SM6350 RPMh statistics is enabled, the USB audio offload DAI is
 introduced and on Fairphone4 the USB audio offload support is enabled.
 
 On SM8450 QRD the PMIC GLINK is described, to add USB Type-C and battery
 functionality.
 
 On SM8650 ACD levels are added for the GPU.
 
 Camera and video clock controllers power-domains are updated on SM8450,
 SM8550, and SM8650, now that support for multiple power-domains is
 accepted.
 
 SM8750 gains bwmon support for dynamic bus scaling, and PCIe nodes.
 
 The DWC3 glue and core nodes are flattened on a number of platforms.
 
 USB Type-C DisplayPort support is extended to 4 lanes (from 2) on a
 variety of platforms, now that the QMP PHY driver supports this.
 
 Platform specific RPMh PD constants are replaced with generic constants
 wherever possible.
 
 On X Elite the PM8010 is disabled by default, removing boot splats
 on a variety of boards without this PMIC, the video clock controller is
 added.
 
 For the X Elite and X Plus CRDs, and the Lenovo Thinkpad T14s, HBR3 is
 marked as valid for the external DisplayPorts. The fingerprint reader
 found on the CRDs are enabled. The PCIe x8 slot on the QCP is enabled.
 The two Microsoft Surface Laptop 7 gains WiFi and Bluetooth support.
 
 GPU support is added for the X Plus SoC.
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Merge tag 'qcom-arm64-for-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt

Qualcomm Arm64 DeviceTree updates for v6.18

Add support for Lenovo Thinkbook 16, Dell Inspiron 7441, Dell Latitude
7455, Samsung Galaxy S20, Billion Capture+, the Monaco EVK and the
Lemans EVK.

The SDM845 Cheza development boards are removed, as they are not longer
in use.

For IPQ5018 crypto, tsens, rng, SPI NAND support is dded, the two MDIO
buses are added and the internal GE PHY.

IPQ5424 gets CPU frequency scaling and a missing UART.

The SA8775P SoC is remaned Lemans, to reduce confusion about the chip
name. The IoT memory map introduced and made the default, GDSP FastRPC
and GPR nodes are added.

Touch keys are enabled on the BQ Aquaris X5 Plus.

On QCM2290 the video accelerator is enabled, so is HS timing modes for
eMMC.

The QCS615 platform is renamed SM6150. CPU frequency scaling and the WiFi
PCIe controller is introduced.

On Monaco (QCS8300) scaling of L3 and DDR bandwidth is introduced. So is
eMMC support and generic packer router (GPR).

On the Monaco Ride board, the eMMC controller is enabled.

On QRB220 RB1, the venus video accelerator is enabled.

For SC7280 the first PCIe controller and PHY is introduced. SoundWire,
LPASS, and USB offload support is added, the codecs and sound card is
then described on the QCM6490 IDP. The MDSS core reset is introduced, to
clear bootloader configuration on SC7280-based devices.
On Fairphone5, USB audio offload is added.

AudioReach support on SC7280 (QCS6490) is introduced and used to
enable sound on the RB3Gen2 board.

The video clock controller is added to SC8180X.

On SC8280XP the GPI DMA controllers are described and enabled.

Display and GPU is enabled for the Fairphone 3 and charging is enabled
on the Google Pixel 3a.

The routing for the second USB connector on the Lenovo Yoga C630 is
described.

On SM6150 ADSP and CDSP FastRPC is introduced, as is the video
encoder/decoder (venus).

On SM6350 RPMh statistics is enabled, the USB audio offload DAI is
introduced and on Fairphone4 the USB audio offload support is enabled.

On SM8450 QRD the PMIC GLINK is described, to add USB Type-C and battery
functionality.

On SM8650 ACD levels are added for the GPU.

Camera and video clock controllers power-domains are updated on SM8450,
SM8550, and SM8650, now that support for multiple power-domains is
accepted.

SM8750 gains bwmon support for dynamic bus scaling, and PCIe nodes.

The DWC3 glue and core nodes are flattened on a number of platforms.

USB Type-C DisplayPort support is extended to 4 lanes (from 2) on a
variety of platforms, now that the QMP PHY driver supports this.

Platform specific RPMh PD constants are replaced with generic constants
wherever possible.

On X Elite the PM8010 is disabled by default, removing boot splats
on a variety of boards without this PMIC, the video clock controller is
added.

For the X Elite and X Plus CRDs, and the Lenovo Thinkpad T14s, HBR3 is
marked as valid for the external DisplayPorts. The fingerprint reader
found on the CRDs are enabled. The PCIe x8 slot on the QCP is enabled.
The two Microsoft Surface Laptop 7 gains WiFi and Bluetooth support.

GPU support is added for the X Plus SoC.

* tag 'qcom-arm64-for-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (208 commits)
  arm64: dts: qcom: x1e80100: Update GPU OPP table
  arm64: dts: qcom: sm8650: Drop redundant status from PMK8550 RTC
  arm64: dts: qcom: add initial support for Samsung Galaxy S20
  dt-bindings: arm: qcom: document x1q board binding
  arm64: dts: qcom: sm8250-samsung-r8q: Move common parts to dtsi
  arm64: dts: qcom: lemans-evk: Add sound card
  arm64: dts: qcom: lemans: Add gpr node
  arm64: dts: qcom: x1e78100-t14s-oled: Add eDP panel
  arm64: dts: qcom: qcs615-ride: enable venus node to initialize video codec
  arm64: dts: qcom: sm6150: add venus node to devicetree
  arm64: dts: qcom: x1e80100-romulus: Add WCN7850 Wi-Fi/BT
  arm64: dts: qcom: qrb2210-rb1: Enable Venus
  arm64: dts: qcom: qcm2290: Add Venus video node
  arm64: dts: qcom: monaco-evk: Add sound card
  arm64: dts: qcom: qcs8300: Add gpr node
  arm64: dts: qcom: qcs8300: Add Monaco EVK board
  dt-bindings: arm: qcom: Add Monaco EVK support
  arm64: dts: qcom: qcm6490-idp: Add sound card
  arm64: dts: qcom: qcm6490-idp: Add WSA8830 speakers and WCD9370 headset codec
  arm64: dts: qcom: qcs6490-rb3gen2: Add sound card
  ...

Link: https://lore.kernel.org/r/20250911233600.3033675-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2025-09-15 15:25:50 +02:00
commit a3ef7cad8b
139 changed files with 11081 additions and 3959 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
Documentation/devicetree/bindings/arm/qcom-soc.yaml
View File

@ -23,7 +23,9 @@ description: |
select:
properties:
compatible:
pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sar|sc|sd[amx]|sm|x1[ep])[0-9]+.*$"
oneOf:
- pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sar|sc|sd[amx]|sm|x1[ep])[0-9]+.*$"
- pattern: "^qcom,.*(glymur|milos).*$"
required:
- compatible
@ -34,6 +36,7 @@ properties:
- pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+(pro)?-.*$"
- pattern: "^qcom,sar[0-9]+[a-z]?-.*$"
- pattern: "^qcom,(sa|sc)8[0-9]+[a-z][a-z]?-.*$"
- pattern: "^qcom,(glymur|milos)-.*$"
# Legacy namings - variations of existing patterns/compatibles are OK,
# but do not add completely new entries to these:

107
Documentation/devicetree/bindings/arm/qcom.yaml
View File

@ -10,100 +10,6 @@ maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
description: |
For devices using the Qualcomm SoC the "compatible" properties consists of
one or several "manufacturer,model" strings, describing the device itself,
followed by one or several "qcom,<SoC>" strings, describing the SoC used in
the device.
The 'SoC' element must be one of the following strings:
apq8016
apq8026
apq8064
apq8074
apq8084
apq8094
apq8096
ipq4018
ipq4019
ipq5018
ipq5332
ipq5424
ipq6018
ipq8064
ipq8074
ipq9574
mdm9615
msm8226
msm8660
msm8916
msm8917
msm8926
msm8929
msm8939
msm8953
msm8956
msm8960
msm8974
msm8974pro
msm8976
msm8992
msm8994
msm8996
msm8996pro
msm8998
qcs404
qcs615
qcs8300
qcs8550
qcm2290
qcm6490
qcs9100
qdu1000
qrb2210
qrb4210
qru1000
sa8155p
sa8540p
sa8775p
sar2130p
sc7180
sc7280
sc8180x
sc8280xp
sda660
sdm450
sdm630
sdm632
sdm636
sdm660
sdm670
sdm845
sdx55
sdx65
sdx75
sm4250
sm4450
sm6115
sm6115p
sm6125
sm6350
sm6375
sm7125
sm7150
sm7225
sm7325
sm8150
sm8250
sm8350
sm8450
sm8550
sm8650
sm8750
x1e78100
x1e80100
x1p42100
There are many devices in the list below that run the standard ChromeOS
bootloader setup and use the open source depthcharge bootloader to boot the
OS. These devices use the bootflow explained at
@ -287,6 +193,7 @@ properties:
- items:
- enum:
- flipkart,rimob
- motorola,potter
- xiaomi,daisy
- xiaomi,mido
@ -948,6 +855,7 @@ properties:
- items:
- enum:
- qcom,monaco-evk
- qcom,qcs8300-ride
- const: qcom,qcs8300
@ -955,6 +863,7 @@ properties:
- enum:
- qcom,qcs615-ride
- const: qcom,qcs615
- const: qcom,sm6150
- items:
- enum:
@ -975,6 +884,7 @@ properties:
- items:
- enum:
- qcom,lemans-evk
- qcom,qcs9100-ride
- qcom,qcs9100-ride-r3
- const: qcom,qcs9100
@ -982,9 +892,6 @@ properties:
- items:
- enum:
- google,cheza
- google,cheza-rev1
- google,cheza-rev2
- lenovo,yoga-c630
- lg,judyln
- lg,judyp
@ -1082,6 +989,8 @@ properties:
- qcom,qrb5165-rb5
- qcom,sm8250-hdk
- qcom,sm8250-mtp
- samsung,r8q
- samsung,x1q
- sony,pdx203-generic
- sony,pdx206-generic
- xiaomi,elish
@ -1103,6 +1012,7 @@ properties:
- qcom,sm8450-qrd
- sony,pdx223
- sony,pdx224
- samsung,r0q
- const: qcom,sm8450
- items:
@ -1152,6 +1062,8 @@ properties:
- enum:
- asus,vivobook-s15
- asus,zenbook-a14-ux3407ra
- dell,inspiron-14-plus-7441
- dell,latitude-7455
- dell,xps13-9345
- hp,elitebook-ultra-g1q
- hp,omnibook-x14
@ -1165,6 +1077,7 @@ properties:
- items:
- enum:
- asus,zenbook-a14-ux3407qa
- lenovo,thinkbook-16
- qcom,x1p42100-crd
- const: qcom,x1p42100

55
Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml Normal file
View File

@ -0,0 +1,55 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,ipq5424-apss-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm APSS IPQ5424 Clock Controller
maintainers:
- Varadarajan Narayanan <quic_varada@quicinc.com>
description:
The CPU core in ipq5424 is clocked by a huayra PLL with RCG support.
The RCG and PLL have a separate register space from the GCC.
properties:
compatible:
enum:
- qcom,ipq5424-apss-clk
reg:
maxItems: 1
clocks:
items:
- description: Reference to the XO clock.
- description: Reference to the GPLL0 clock.
'#clock-cells':
const: 1
'#interconnect-cells':
const: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#interconnect-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,ipq5424-gcc.h>
apss_clk: clock-controller@fa80000 {
compatible = "qcom,ipq5424-apss-clk";
reg = <0x0fa80000 0x20000>;
clocks = <&xo_board>,
<&gcc GPLL0>;
#clock-cells = <1>;
#interconnect-cells = <1>;
};

2
Documentation/devicetree/bindings/vendor-prefixes.yaml
View File

@ -552,6 +552,8 @@ patternProperties:
description: Foxconn Industrial Internet
"^firefly,.*":
description: Firefly
"^flipkart,.*":
description: Flipkart Inc.
"^focaltech,.*":
description: FocalTech Systems Co.,Ltd
"^forlinx,.*":

1
MAINTAINERS
View File

@ -3109,7 +3109,6 @@ ARM/QUALCOMM CHROMEBOOK SUPPORT
R: cros-qcom-dts-watchers@chromium.org
F: arch/arm64/boot/dts/qcom/sc7180*
F: arch/arm64/boot/dts/qcom/sc7280*
F: arch/arm64/boot/dts/qcom/sdm845-cheza*
ARM/QUALCOMM MAILING LIST
L: linux-arm-msm@vger.kernel.org

14
arch/arm64/boot/dts/qcom/Makefile
View File

@ -29,6 +29,8 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp449.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp453.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp454.dtb
dtb-$(CONFIG_ARCH_QCOM) += lemans-evk.dtb
dtb-$(CONFIG_ARCH_QCOM) += monaco-evk.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8216-samsung-fortuna3g.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb
@ -71,6 +73,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8939-samsung-a7.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8939-sony-xperia-kanuti-tulip.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8939-wingtech-wt82918.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8939-wingtech-wt82918hd.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8953-flipkart-rimob.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8953-motorola-potter.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-daisy.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-mido.dtb
@ -231,9 +234,6 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm632-motorola-ocean.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm636-sony-xperia-ganges-mermaid.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-lavender.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm670-google-sargo.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb
sdm845-db845c-navigation-mezzanine-dtbs := sdm845-db845c.dtb sdm845-db845c-navigation-mezzanine.dtbo
@ -275,6 +275,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8150-sony-xperia-kumano-bahamut.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-sony-xperia-kumano-griffin.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8250-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8250-samsung-r8q.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8250-samsung-x1q.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx203.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx206.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8250-xiaomi-elish-boe.dtb
@ -315,6 +317,10 @@ x1e80100-asus-zenbook-a14-el2-dtbs := x1e80100-asus-zenbook-a14.dtb x1-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-asus-zenbook-a14.dtb x1e80100-asus-zenbook-a14-el2.dtb
x1e80100-crd-el2-dtbs := x1e80100-crd.dtb x1-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-crd.dtb x1e80100-crd-el2.dtb
x1e80100-dell-inspiron-14-plus-7441-el2-dtbs := x1e80100-dell-inspiron-14-plus-7441.dtb x1-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-dell-inspiron-14-plus-7441.dtb x1e80100-dell-inspiron-14-plus-7441-el2.dtb
x1e80100-dell-latitude-7455-el2-dtbs := x1e80100-dell-latitude-7455.dtb x1-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-dell-latitude-7455.dtb x1e80100-dell-latitude-7455-el2.dtb
x1e80100-dell-xps13-9345-el2-dtbs := x1e80100-dell-xps13-9345.dtb x1-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-dell-xps13-9345.dtb x1e80100-dell-xps13-9345-el2.dtb
x1e80100-hp-elitebook-ultra-g1q-el2-dtbs := x1e80100-hp-elitebook-ultra-g1q.dtb x1-el2.dtbo
@ -333,3 +339,5 @@ x1p42100-asus-zenbook-a14-el2-dtbs := x1p42100-asus-zenbook-a14.dtb x1-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += x1p42100-asus-zenbook-a14.dtb x1p42100-asus-zenbook-a14-el2.dtb
x1p42100-crd-el2-dtbs := x1p42100-crd.dtb x1-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += x1p42100-crd.dtb x1p42100-crd-el2.dtb
x1p42100-lenovo-thinkbook-16-el2-dtbs := x1p42100-lenovo-thinkbook-16.dtb x1-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += x1p42100-lenovo-thinkbook-16.dtb x1p42100-lenovo-thinkbook-16-el2.dtb

3
arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
View File

@ -120,5 +120,6 @@ &usbphy0 {
};
&xo_board_clk {
clock-frequency = <24000000>;
clock-div = <4>;
clock-mult = <1>;
};

3
arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts
View File

@ -124,5 +124,6 @@ uart_pins: uart-pins-state {
};
&xo_board_clk {
clock-frequency = <24000000>;
clock-div = <4>;
clock-mult = <1>;
};

356
arch/arm64/boot/dts/qcom/ipq5018.dtsi
View File

@ -2,13 +2,15 @@
/*
* IPQ5018 SoC device tree source
*
* Copyright (c) 2023 The Linux Foundation. All rights reserved.
* Copyright (c) 2023-2025 The Linux Foundation. All rights reserved.
*/
#include <dt-bindings/clock/qcom,apss-ipq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-ipq5018.h>
#include <dt-bindings/clock/qcom,ipq5018-cmn-pll.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/qcom,gcc-ipq5018.h>
#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&intc>;
@ -16,14 +18,41 @@ / {
#size-cells = <2>;
clocks {
gephy_rx_clk: gephy-rx-clk {
compatible = "fixed-clock";
clock-frequency = <125000000>;
#clock-cells = <0>;
};
gephy_tx_clk: gephy-tx-clk {
compatible = "fixed-clock";
clock-frequency = <125000000>;
#clock-cells = <0>;
};
ref_96mhz_clk: ref-96mhz-clk {
compatible = "fixed-factor-clock";
clocks = <&xo_clk>;
#clock-cells = <0>;
clock-div = <1>;
clock-mult = <2>;
};
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
};
xo_board_clk: xo-board-clk {
compatible = "fixed-factor-clock";
clocks = <&ref_96mhz_clk>;
#clock-cells = <0>;
};
xo_clk: xo-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
};
@ -39,6 +68,7 @@ cpu0: cpu@0 {
next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>;
};
cpu1: cpu@1 {
@ -49,6 +79,7 @@ cpu1: cpu@1 {
next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>;
};
l2_0: l2-cache {
@ -182,6 +213,201 @@ pcie0_phy: phy@86000 {
status = "disabled";
};
mdio0: mdio@88000 {
compatible = "qcom,ipq5018-mdio";
reg = <0x00088000 0x64>,
<0x019475c4 0x4>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&gcc GCC_MDIO0_AHB_CLK>;
clock-names = "gcc_mdio_ahb_clk";
status = "disabled";
ge_phy: ethernet-phy@7 {
compatible = "ethernet-phy-id004d.d0c0";
reg = <7>;
resets = <&gcc GCC_GEPHY_MISC_ARES>;
};
};
mdio1: mdio@90000 {
compatible = "qcom,ipq5018-mdio";
reg = <0x00090000 0x64>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&gcc GCC_MDIO1_AHB_CLK>;
clock-names = "gcc_mdio_ahb_clk";
status = "disabled";
};
cmn_pll: clock-controller@9b000 {
compatible = "qcom,ipq5018-cmn-pll";
reg = <0x0009b000 0x800>;
clocks = <&ref_96mhz_clk>,
<&gcc GCC_CMN_BLK_AHB_CLK>,
<&gcc GCC_CMN_BLK_SYS_CLK>;
clock-names = "ref",
"ahb",
"sys";
#clock-cells = <1>;
assigned-clocks = <&cmn_pll IPQ5018_CMN_PLL_CLK>;
assigned-clock-rates-u64 = /bits/ 64 <9600000000>;
};
qfprom: qfprom@a0000 {
compatible = "qcom,ipq5018-qfprom", "qcom,qfprom";
reg = <0x000a0000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
tsens_mode: mode@249 {
reg = <0x249 0x1>;
bits = <0 3>;
};
tsens_base1: base1@249 {
reg = <0x249 0x2>;
bits = <3 8>;
};
tsens_base2: base2@24a {
reg = <0x24a 0x2>;
bits = <3 8>;
};
tsens_s0_p1: s0-p1@24b {
reg = <0x24b 0x2>;
bits = <2 6>;
};
tsens_s0_p2: s0-p2@24c {
reg = <0x24c 0x1>;
bits = <1 6>;
};
tsens_s1_p1: s1-p1@24c {
reg = <0x24c 0x2>;
bits = <7 6>;
};
tsens_s1_p2: s1-p2@24d {
reg = <0x24d 0x2>;
bits = <5 6>;
};
tsens_s2_p1: s2-p1@24e {
reg = <0x24e 0x2>;
bits = <3 6>;
};
tsens_s2_p2: s2-p2@24f {
reg = <0x24f 0x1>;
bits = <1 6>;
};
tsens_s3_p1: s3-p1@24f {
reg = <0x24f 0x2>;
bits = <7 6>;
};
tsens_s3_p2: s3-p2@250 {
reg = <0x250 0x2>;
bits = <5 6>;
};
tsens_s4_p1: s4-p1@251 {
reg = <0x251 0x2>;
bits = <3 6>;
};
tsens_s4_p2: s4-p2@254 {
reg = <0x254 0x1>;
bits = <0 6>;
};
};
prng: rng@e3000 {
compatible = "qcom,prng-ee";
reg = <0x000e3000 0x1000>;
clocks = <&gcc GCC_PRNG_AHB_CLK>;
clock-names = "core";
status = "disabled";
};
tsens: thermal-sensor@4a9000 {
compatible = "qcom,ipq5018-tsens", "qcom,tsens-v1";
reg = <0x004a9000 0x1000>,
<0x004a8000 0x1000>;
nvmem-cells = <&tsens_mode>,
<&tsens_base1>,
<&tsens_base2>,
<&tsens_s0_p1>,
<&tsens_s0_p2>,
<&tsens_s1_p1>,
<&tsens_s1_p2>,
<&tsens_s2_p1>,
<&tsens_s2_p2>,
<&tsens_s3_p1>,
<&tsens_s3_p2>,
<&tsens_s4_p1>,
<&tsens_s4_p2>;
nvmem-cell-names = "mode",
"base1",
"base2",
"s0_p1",
"s0_p2",
"s1_p1",
"s1_p2",
"s2_p1",
"s2_p2",
"s3_p1",
"s3_p2",
"s4_p1",
"s4_p2";
interrupts = <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "uplow";
#qcom,sensors = <5>;
#thermal-sensor-cells = <1>;
};
cryptobam: dma-controller@704000 {
compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
reg = <0x00704000 0x20000>;
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <1>;
qcom,controlled-remotely;
};
crypto: crypto@73a000 {
compatible = "qcom,crypto-v5.1";
reg = <0x0073a000 0x6000>;
clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
<&gcc GCC_CRYPTO_AXI_CLK>,
<&gcc GCC_CRYPTO_CLK>;
clock-names = "iface",
"bus",
"core";
dmas = <&cryptobam 2>,
<&cryptobam 3>;
dma-names = "rx",
"tx";
};
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq5018-tlmm";
reg = <0x01000000 0x300000>;
@ -208,8 +434,8 @@ gcc: clock-controller@1800000 {
<&pcie0_phy>,
<&pcie1_phy>,
<0>,
<0>,
<0>,
<&gephy_rx_clk>,
<&gephy_tx_clk>,
<0>,
<0>;
#clock-cells = <1>;
@ -278,6 +504,44 @@ blsp1_spi1: spi@78b5000 {
status = "disabled";
};
qpic_bam: dma-controller@7984000 {
compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
reg = <0x07984000 0x1c000>;
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QPIC_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
status = "disabled";
};
qpic_nand: spi@79b0000 {
compatible = "qcom,ipq5018-snand", "qcom,ipq9574-snand";
reg = <0x079b0000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&gcc GCC_QPIC_CLK>,
<&gcc GCC_QPIC_AHB_CLK>,
<&gcc GCC_QPIC_IO_MACRO_CLK>;
clock-names = "core",
"aon",
"iom";
dmas = <&qpic_bam 0>,
<&qpic_bam 1>,
<&qpic_bam 2>;
dma-names = "tx",
"rx",
"cmd";
status = "disabled";
};
usb: usb@8af8800 {
compatible = "qcom,ipq5018-dwc3", "qcom,dwc3";
reg = <0x08af8800 0x400>;
@ -453,7 +717,7 @@ pcie1: pcie@80000000 {
max-link-speed = <2>;
phys = <&pcie1_phy>;
phy-names ="pciephy";
phy-names = "pciephy";
ranges = <0x01000000 0 0x00000000 0x80200000 0 0x00100000>,
<0x02000000 0 0x80300000 0x80300000 0 0x10000000>;
@ -481,10 +745,10 @@ pcie1: pcie@80000000 {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 142 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 0 143 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 0 144 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 0 145 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
<&gcc GCC_PCIE1_AXI_M_CLK>,
@ -554,7 +818,7 @@ pcie0: pcie@a0000000 {
max-link-speed = <2>;
phys = <&pcie0_phy>;
phy-names ="pciephy";
phy-names = "pciephy";
ranges = <0x01000000 0 0x00000000 0xa0200000 0 0x00100000>,
<0x02000000 0 0xa0300000 0xa0300000 0 0x10000000>;
@ -582,10 +846,10 @@ pcie0: pcie@a0000000 {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 75 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 0 78 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 0 79 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 0 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
<&gcc GCC_PCIE0_AXI_M_CLK>,
@ -631,6 +895,70 @@ pcie@0 {
};
};
thermal-zones {
cpu-thermal {
thermal-sensors = <&tsens 2>;
trips {
cpu-critical {
temperature = <120000>;
hysteresis = <1000>;
type = "critical";
};
cpu_alert: cpu-passive {
temperature = <100000>;
hysteresis = <1000>;
type = "passive";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
gephy-thermal {
thermal-sensors = <&tsens 4>;
trips {
gephy-critical {
temperature = <120000>;
hysteresis = <1000>;
type = "critical";
};
};
};
top-glue-thermal {
thermal-sensors = <&tsens 3>;
trips {
top-glue-critical {
temperature = <120000>;
hysteresis = <1000>;
type = "critical";
};
};
};
ubi32-thermal {
thermal-sensors = <&tsens 1>;
trips {
ubi32-critical {
temperature = <120000>;
hysteresis = <1000>;
type = "critical";
};
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

16
arch/arm64/boot/dts/qcom/ipq5332.dtsi
View File

@ -632,10 +632,10 @@ pcie1: pcie@18000000 {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 412 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 0 413 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 0 414 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 0 415 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE3X2_AXI_M_CLK>,
<&gcc GCC_PCIE3X2_AXI_S_CLK>,
@ -736,10 +736,10 @@ pcie0: pcie@20000000 {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 35 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 0 36 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 0 37 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 0 38 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE3X1_0_AXI_M_CLK>,
<&gcc GCC_PCIE3X1_0_AXI_S_CLK>,

44
arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
View File

@ -2,7 +2,7 @@
/*
* IPQ5424 RDP466 board device tree source
*
* Copyright (c) 2024 The Linux Foundation. All rights reserved.
* Copyright (c) 2024-2025 The Linux Foundation. All rights reserved.
*/
/dts-v1/;
@ -224,6 +224,13 @@ data-pins {
};
};
uart0_pins: uart0-default-state {
pins = "gpio10", "gpio11", "gpio12", "gpio13";
function = "uart0";
drive-strength = <8>;
bias-pull-down;
};
pcie2_default_state: pcie2-default-state {
pins = "gpio31";
function = "gpio";
@ -239,6 +246,17 @@ pcie3_default_state: pcie3-default-state {
};
};
&uart0 {
pinctrl-0 = <&uart0_pins>;
pinctrl-names = "default";
/*
* The required initialization for this SE is not handled by the
* bootloader. Therefore, keep the device in "reserved" state until
* linux gains support for configuring the SE.
*/
status = "reserved";
};
&uart1 {
pinctrl-0 = <&uart1_pins>;
pinctrl-names = "default";
@ -253,6 +271,26 @@ &usb3 {
status = "okay";
};
&xo_board {
clock-frequency = <24000000>;
/*
* The bootstrap pins for the board select the XO clock frequency that
* supports 48 MHZ, 96 MHZ or 192 MHZ. This setting automatically
* enables the right dividers, to ensure the reference clock output
* from WiFi to the CMN PLL is 48 MHZ.
*/
&ref_48mhz_clk {
clock-div = <1>;
clock-mult = <1>;
};
/*
* The frequency of xo_board is fixed to 24 MHZ, which is routed
* from WiFi output clock 48 MHZ divided by 2.
*/
&xo_board {
clock-div = <2>;
clock-mult = <1>;
};
&xo_clk {
clock-frequency = <48000000>;
};

144
arch/arm64/boot/dts/qcom/ipq5424.dtsi
View File

@ -3,10 +3,12 @@
* IPQ5424 device tree source
*
* Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,apss-ipq.h>
#include <dt-bindings/clock/qcom,ipq5424-cmn-pll.h>
#include <dt-bindings/clock/qcom,ipq5424-gcc.h>
#include <dt-bindings/reset/qcom,ipq5424-gcc.h>
#include <dt-bindings/interconnect/qcom,ipq5424.h>
@ -18,12 +20,24 @@ / {
interrupt-parent = <&intc>;
clocks {
ref_48mhz_clk: ref-48mhz-clk {
compatible = "fixed-factor-clock";
clocks = <&xo_clk>;
#clock-cells = <0>;
};
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
};
xo_board: xo-board-clk {
compatible = "fixed-factor-clock";
clocks = <&ref_48mhz_clk>;
#clock-cells = <0>;
};
xo_clk: xo-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
};
@ -39,6 +53,11 @@ cpu0: cpu@0 {
reg = <0x0>;
enable-method = "psci";
next-level-cache = <&l2_0>;
clocks = <&apss_clk APSS_SILVER_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>;
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
@ -59,6 +78,10 @@ cpu1: cpu@100 {
enable-method = "psci";
reg = <0x100>;
next-level-cache = <&l2_100>;
clocks = <&apss_clk APSS_SILVER_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>;
l2_100: l2-cache {
compatible = "cache";
@ -74,6 +97,10 @@ cpu2: cpu@200 {
enable-method = "psci";
reg = <0x200>;
next-level-cache = <&l2_200>;
clocks = <&apss_clk APSS_SILVER_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>;
l2_200: l2-cache {
compatible = "cache";
@ -89,6 +116,10 @@ cpu3: cpu@300 {
enable-method = "psci";
reg = <0x300>;
next-level-cache = <&l2_300>;
clocks = <&apss_clk APSS_SILVER_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>;
l2_300: l2-cache {
compatible = "cache";
@ -106,6 +137,36 @@ scm {
};
};
cpu_opp_table: opp-table-cpu {
compatible = "operating-points-v2-kryo-cpu";
opp-shared;
nvmem-cells = <&cpu_speed_bin>;
opp-816000000 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <850000>;
opp-supported-hw = <0x3>;
clock-latency-ns = <200000>;
opp-peak-kBps = <816000>;
};
opp-1416000000 {
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <850000>;
opp-supported-hw = <0x3>;
clock-latency-ns = <200000>;
opp-peak-kBps = <984000>;
};
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1000000>;
opp-supported-hw = <0x1>;
clock-latency-ns = <200000>;
opp-peak-kBps = <1272000>;
};
};
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
@ -150,6 +211,12 @@ smem@8a800000 {
hwlocks = <&tcsr_mutex 3>;
};
tfa@8a832000 {
reg = <0x0 0x8a832000 0x0 0x7d000>;
no-map;
status = "disabled";
};
};
soc@0 {
@ -210,6 +277,18 @@ pcie1_phy: phy@8c000 {
status = "disabled";
};
cmn_pll: clock-controller@9b000 {
compatible = "qcom,ipq5424-cmn-pll";
reg = <0 0x0009b000 0 0x800>;
clocks = <&ref_48mhz_clk>,
<&gcc GCC_CMN_12GPLL_AHB_CLK>,
<&gcc GCC_CMN_12GPLL_SYS_CLK>;
clock-names = "ref", "ahb", "sys";
#clock-cells = <1>;
assigned-clocks = <&cmn_pll IPQ5424_CMN_PLL_CLK>;
assigned-clock-rates-u64 = /bits/ 64 <12000000000>;
};
efuse@a4000 {
compatible = "qcom,ipq5424-qfprom", "qcom,qfprom";
reg = <0 0x000a4000 0 0x741>;
@ -363,6 +442,18 @@ system-cache-controller@800000 {
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
};
qfprom@a6000 {
compatible = "qcom,ipq5424-qfprom", "qcom,qfprom";
reg = <0x0 0x000a6000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
cpu_speed_bin: cpu-speed-bin@234 {
reg = <0x234 0x1>;
bits = <0 8>;
};
};
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq5424-tlmm";
reg = <0 0x01000000 0 0x300000>;
@ -417,6 +508,15 @@ qupv3: geniqup@1ac0000 {
#address-cells = <2>;
#size-cells = <2>;
uart0: serial@1a80000 {
compatible = "qcom,geni-uart";
reg = <0 0x01a80000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_UART0_CLK>;
clock-names = "se";
interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uart1: serial@1a84000 {
compatible = "qcom,geni-debug-uart";
reg = <0 0x01a84000 0 0x4000>;
@ -471,6 +571,7 @@ intc: interrupt-controller@f200000 {
compatible = "arm,gic-v3";
reg = <0 0xf200000 0 0x10000>, /* GICD */
<0 0xf240000 0 0x80000>; /* GICR * 4 regions */
#address-cells = <0>;
#interrupt-cells = <0x3>;
interrupt-controller;
#redistributor-regions = <1>;
@ -705,6 +806,15 @@ frame@f42d000 {
};
};
apss_clk: clock-controller@fa80000 {
compatible = "qcom,ipq5424-apss-clk";
reg = <0x0 0x0fa80000 0x0 0x20000>;
clocks = <&xo_board>,
<&gcc GPLL0>;
#clock-cells = <1>;
#interconnect-cells = <1>;
};
pcie3: pcie@40000000 {
compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574";
reg = <0x0 0x40000000 0x0 0xf1c>,
@ -752,10 +862,10 @@ pcie3: pcie@40000000 {
#interrupt-cells = <1>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 479 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 480 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 481 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 482 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map = <0 0 0 1 &intc GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc GIC_SPI 480 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc GIC_SPI 482 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE3_AXI_M_CLK>,
<&gcc GCC_PCIE3_AXI_S_CLK>,
@ -855,10 +965,10 @@ pcie2: pcie@50000000 {
#interrupt-cells = <1>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 464 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 465 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 466 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 467 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map = <0 0 0 1 &intc GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE2_AXI_M_CLK>,
<&gcc GCC_PCIE2_AXI_S_CLK>,
@ -958,10 +1068,10 @@ pcie1: pcie@60000000 {
#interrupt-cells = <1>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 449 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 450 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 451 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 452 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map = <0 0 0 1 &intc GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE1_AXI_M_CLK>,
<&gcc GCC_PCIE1_AXI_S_CLK>,
@ -1061,10 +1171,10 @@ pcie0: pcie@70000000 {
#interrupt-cells = <1>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 436 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 437 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE0_AXI_M_CLK>,
<&gcc GCC_PCIE0_AXI_S_CLK>,

8
arch/arm64/boot/dts/qcom/ipq6018.dtsi
View File

@ -906,10 +906,10 @@ pcie0: pcie@20000000 {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 0 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 0 0 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 0 0 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 0 0 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 0 GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 0 GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 0 GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
<&gcc GCC_PCIE0_AXI_M_CLK>,

16
arch/arm64/boot/dts/qcom/ipq8074.dtsi
View File

@ -867,13 +867,13 @@ pcie1: pcie@10000000 {
"global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 142
interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 142
IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 0 143
<0 0 0 2 &intc 0 GIC_SPI 143
IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 0 144
<0 0 0 3 &intc 0 GIC_SPI 144
IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 0 145
<0 0 0 4 &intc 0 GIC_SPI 145
IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
@ -955,13 +955,13 @@ pcie0: pcie@20000000 {
"global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 75
interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 75
IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 0 78
<0 0 0 2 &intc 0 GIC_SPI 78
IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 0 79
<0 0 0 3 &intc 0 GIC_SPI 79
IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 0 83
<0 0 0 4 &intc 0 GIC_SPI 83
IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,

32
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
View File

@ -128,36 +128,4 @@ wake-n-pins {
bias-pull-up;
};
};
sdc_default_state: sdc-default-state {
clk-pins {
pins = "gpio5";
function = "sdc_clk";
drive-strength = <8>;
bias-disable;
};
cmd-pins {
pins = "gpio4";
function = "sdc_cmd";
drive-strength = <8>;
bias-pull-up;
};
data-pins {
pins = "gpio0", "gpio1", "gpio2",
"gpio3", "gpio6", "gpio7",
"gpio8", "gpio9";
function = "sdc_data";
drive-strength = <8>;
bias-pull-up;
};
rclk-pins {
pins = "gpio10";
function = "sdc_rclk";
drive-strength = <8>;
bias-pull-down;
};
};
};

34
arch/arm64/boot/dts/qcom/ipq9574.dtsi
View File

@ -946,10 +946,10 @@ pcie1: pcie@10000000 {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 35 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 0 49 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 0 84 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 0 85 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE1_AXI_M_CLK>,
<&gcc GCC_PCIE1_AXI_S_CLK>,
@ -1032,10 +1032,10 @@ pcie3: pcie@18000000 {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 189 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 0 190 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 0 191 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 0 192 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE3_AXI_M_CLK>,
<&gcc GCC_PCIE3_AXI_S_CLK>,
@ -1118,10 +1118,10 @@ pcie2: pcie@20000000 {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 164 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 0 165 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 0 186 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 0 187 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE2_AXI_M_CLK>,
<&gcc GCC_PCIE2_AXI_S_CLK>,
@ -1161,7 +1161,7 @@ pcie2: pcie@20000000 {
status = "disabled";
};
pcie0: pci@28000000 {
pcie0: pcie@28000000 {
compatible = "qcom,pcie-ipq9574";
reg = <0x28000000 0xf1d>,
<0x28000f20 0xa8>,
@ -1203,10 +1203,10 @@ pcie0: pci@28000000 {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 75 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 0 78 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 0 79 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 0 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE0_AXI_M_CLK>,
<&gcc GCC_PCIE0_AXI_S_CLK>,

104
arch/arm64/boot/dts/qcom/lemans-auto.dtsi Normal file
View File

@ -0,0 +1,104 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023, Linaro Limited
*/
/dts-v1/;
#include "lemans.dtsi"
/delete-node/ &pil_camera_mem;
/delete-node/ &pil_adsp_mem;
/delete-node/ &q6_adsp_dtb_mem;
/delete-node/ &q6_gdsp0_dtb_mem;
/delete-node/ &pil_gdsp0_mem;
/delete-node/ &pil_gdsp1_mem;
/delete-node/ &q6_gdsp1_dtb_mem;
/delete-node/ &q6_cdsp0_dtb_mem;
/delete-node/ &pil_cdsp0_mem;
/delete-node/ &pil_gpu_mem;
/delete-node/ &pil_cdsp1_mem;
/delete-node/ &q6_cdsp1_dtb_mem;
/delete-node/ &pil_cvp_mem;
/delete-node/ &pil_video_mem;
/delete-node/ &gunyah_md_mem;
/ {
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
tz_ffi_mem: tz-ffi@91c00000 {
compatible = "shared-dma-pool";
reg = <0x0 0x91c00000 0x0 0x1400000>;
no-map;
};
pil_camera_mem: pil-camera@95200000 {
reg = <0x0 0x95200000 0x0 0x500000>;
no-map;
};
pil_adsp_mem: pil-adsp@95c00000 {
reg = <0x0 0x95c00000 0x0 0x1e00000>;
no-map;
};
pil_gdsp0_mem: pil-gdsp0@97b00000 {
reg = <0x0 0x97b00000 0x0 0x1e00000>;
no-map;
};
pil_gdsp1_mem: pil-gdsp1@99900000 {
reg = <0x0 0x99900000 0x0 0x1e00000>;
no-map;
};
pil_cdsp0_mem: pil-cdsp0@9b800000 {
reg = <0x0 0x9b800000 0x0 0x1e00000>;
no-map;
};
pil_gpu_mem: pil-gpu@9d600000 {
reg = <0x0 0x9d600000 0x0 0x2000>;
no-map;
};
pil_cdsp1_mem: pil-cdsp1@9d700000 {
reg = <0x0 0x9d700000 0x0 0x1e00000>;
no-map;
};
pil_cvp_mem: pil-cvp@9f500000 {
reg = <0x0 0x9f500000 0x0 0x700000>;
no-map;
};
pil_video_mem: pil-video@9fc00000 {
reg = <0x0 0x9fc00000 0x0 0x700000>;
no-map;
};
audio_mdf_mem: audio-mdf-region@ae000000 {
reg = <0x0 0xae000000 0x0 0x1000000>;
no-map;
};
hyptz_reserved_mem: hyptz-reserved@beb00000 {
reg = <0x0 0xbeb00000 0x0 0x11500000>;
no-map;
};
trusted_apps_mem: trusted-apps@d1900000 {
reg = <0x0 0xd1900000 0x0 0x3800000>;
no-map;
};
};
firmware {
scm {
memory-region = <&tz_ffi_mem>;
};
};
};

413
arch/arm64/boot/dts/qcom/lemans-evk.dts Normal file
View File

@ -0,0 +1,413 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024-2025, Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "lemans.dtsi"
#include "lemans-pmics.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Lemans EVK";
compatible = "qcom,lemans-evk", "qcom,qcs9100", "qcom,sa8775p";
aliases {
serial0 = &uart10;
};
dmic: audio-codec-0 {
compatible = "dmic-codec";
#sound-dai-cells = <0>;
num-channels = <1>;
};
max98357a: audio-codec-1 {
compatible = "maxim,max98357a";
#sound-dai-cells = <0>;
};
chosen {
stdout-path = "serial0:115200n8";
};
edp0-connector {
compatible = "dp-connector";
label = "EDP0";
type = "mini";
port {
edp0_connector_in: endpoint {
remote-endpoint = <&mdss0_dp0_out>;
};
};
};
edp1-connector {
compatible = "dp-connector";
label = "EDP1";
type = "mini";
port {
edp1_connector_in: endpoint {
remote-endpoint = <&mdss0_dp1_out>;
};
};
};
sound {
compatible = "qcom,qcs9100-sndcard";
model = "LEMANS-EVK";
pinctrl-0 = <&hs0_mi2s_active>, <&hs2_mi2s_active>;
pinctrl-names = "default";
hs0-mi2s-playback-dai-link {
link-name = "HS0 MI2S Playback";
codec {
sound-dai = <&max98357a>;
};
cpu {
sound-dai = <&q6apmbedai PRIMARY_MI2S_RX>;
};
platform {
sound-dai = <&q6apm>;
};
};
hs2-mi2s-capture-dai-link {
link-name = "HS2 MI2S Capture";
codec {
sound-dai = <&dmic>;
};
cpu {
sound-dai = <&q6apmbedai TERTIARY_MI2S_TX>;
};
platform {
sound-dai = <&q6apm>;
};
};
};
};
&apps_rsc {
regulators-0 {
compatible = "qcom,pmm8654au-rpmh-regulators";
qcom,pmic-id = "a";
vreg_s4a: smps4 {
regulator-name = "vreg_s4a";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1816000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s5a: smps5 {
regulator-name = "vreg_s5a";
regulator-min-microvolt = <1850000>;
regulator-max-microvolt = <1996000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s9a: smps9 {
regulator-name = "vreg_s9a";
regulator-min-microvolt = <535000>;
regulator-max-microvolt = <1120000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4a: ldo4 {
regulator-name = "vreg_l4a";
regulator-min-microvolt = <788000>;
regulator-max-microvolt = <1050000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l5a: ldo5 {
regulator-name = "vreg_l5a";
regulator-min-microvolt = <870000>;
regulator-max-microvolt = <950000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6a: ldo6 {
regulator-name = "vreg_l6a";
regulator-min-microvolt = <870000>;
regulator-max-microvolt = <970000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7a: ldo7 {
regulator-name = "vreg_l7a";
regulator-min-microvolt = <720000>;
regulator-max-microvolt = <950000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8a: ldo8 {
regulator-name = "vreg_l8a";
regulator-min-microvolt = <2504000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9a: ldo9 {
regulator-name = "vreg_l9a";
regulator-min-microvolt = <2970000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
};
regulators-1 {
compatible = "qcom,pmm8654au-rpmh-regulators";
qcom,pmic-id = "c";
vreg_l1c: ldo1 {
regulator-name = "vreg_l1c";
regulator-min-microvolt = <1140000>;
regulator-max-microvolt = <1260000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2c: ldo2 {
regulator-name = "vreg_l2c";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1100000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3c: ldo3 {
regulator-name = "vreg_l3c";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1300000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4c: ldo4 {
regulator-name = "vreg_l4c";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l5c: ldo5 {
regulator-name = "vreg_l5c";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1300000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6c: ldo6 {
regulator-name = "vreg_l6c";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <1980000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7c: ldo7 {
regulator-name = "vreg_l7c";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <2000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8c: ldo8 {
regulator-name = "vreg_l8c";
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9c: ldo9 {
regulator-name = "vreg_l9c";
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <2700000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
};
regulators-2 {
compatible = "qcom,pmm8654au-rpmh-regulators";
qcom,pmic-id = "e";
vreg_s4e: smps4 {
regulator-name = "vreg_s4e";
regulator-min-microvolt = <970000>;
regulator-max-microvolt = <1520000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s7e: smps7 {
regulator-name = "vreg_s7e";
regulator-min-microvolt = <1010000>;
regulator-max-microvolt = <1170000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s9e: smps9 {
regulator-name = "vreg_s9e";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <570000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6e: ldo6 {
regulator-name = "vreg_l6e";
regulator-min-microvolt = <1280000>;
regulator-max-microvolt = <1450000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8e: ldo8 {
regulator-name = "vreg_l8e";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1950000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
};
};
&mdss0 {
status = "okay";
};
&mdss0_dp0 {
pinctrl-0 = <&dp0_hot_plug_det>;
pinctrl-names = "default";
status = "okay";
};
&mdss0_dp0_out {
data-lanes = <0 1 2 3>;
link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
remote-endpoint = <&edp0_connector_in>;
};
&mdss0_dp0_phy {
vdda-phy-supply = <&vreg_l1c>;
vdda-pll-supply = <&vreg_l4a>;
status = "okay";
};
&mdss0_dp1 {
pinctrl-0 = <&dp1_hot_plug_det>;
pinctrl-names = "default";
status = "okay";
};
&mdss0_dp1_out {
data-lanes = <0 1 2 3>;
link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
remote-endpoint = <&edp1_connector_in>;
};
&mdss0_dp1_phy {
vdda-phy-supply = <&vreg_l1c>;
vdda-pll-supply = <&vreg_l4a>;
status = "okay";
};
&qupv3_id_1 {
status = "okay";
};
&sleep_clk {
clock-frequency = <32768>;
};
&uart10 {
compatible = "qcom,geni-debug-uart";
pinctrl-0 = <&qup_uart10_default>;
pinctrl-names = "default";
status = "okay";
};
&ufs_mem_hc {
reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
vcc-supply = <&vreg_l8a>;
vcc-max-microamp = <1100000>;
vccq-supply = <&vreg_l4c>;
vccq-max-microamp = <1200000>;
status = "okay";
};
&ufs_mem_phy {
vdda-phy-supply = <&vreg_l4a>;
vdda-pll-supply = <&vreg_l1c>;
status = "okay";
};
&xo_board_clk {
clock-frequency = <38400000>;
};

0
arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi → arch/arm64/boot/dts/qcom/lemans-pmics.dtsi
View File

168
arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi → arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi
View File

@ -3,18 +3,11 @@
* Copyright (c) 2023, Linaro Limited
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sa8775p.dtsi"
#include "sa8775p-pmics.dtsi"
/ {
aliases {
ethernet0 = &ethernet0;
ethernet1 = &ethernet1;
i2c11 = &i2c11;
i2c18 = &i2c18;
serial0 = &uart10;
@ -443,151 +436,6 @@ vreg_l8e: ldo8 {
};
};
&ethernet0 {
phy-handle = <&sgmii_phy0>;
pinctrl-0 = <&ethernet0_default>;
pinctrl-names = "default";
snps,mtl-rx-config = <&mtl_rx_setup>;
snps,mtl-tx-config = <&mtl_tx_setup>;
snps,ps-speed = <1000>;
status = "okay";
mdio: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
};
mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <4>;
snps,rx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x0>;
snps,route-up;
snps,priority = <0x1>;
};
queue1 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x1>;
snps,route-ptp;
};
queue2 {
snps,avb-algorithm;
snps,map-to-dma-channel = <0x2>;
snps,route-avcp;
};
queue3 {
snps,avb-algorithm;
snps,map-to-dma-channel = <0x3>;
snps,priority = <0xc>;
};
};
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <4>;
queue0 {
snps,dcb-algorithm;
};
queue1 {
snps,dcb-algorithm;
};
queue2 {
snps,avb-algorithm;
snps,send_slope = <0x1000>;
snps,idle_slope = <0x1000>;
snps,high_credit = <0x3e800>;
snps,low_credit = <0xffc18000>;
};
queue3 {
snps,avb-algorithm;
snps,send_slope = <0x1000>;
snps,idle_slope = <0x1000>;
snps,high_credit = <0x3e800>;
snps,low_credit = <0xffc18000>;
};
};
};
&ethernet1 {
phy-handle = <&sgmii_phy1>;
snps,mtl-rx-config = <&mtl_rx_setup1>;
snps,mtl-tx-config = <&mtl_tx_setup1>;
snps,ps-speed = <1000>;
status = "okay";
mtl_rx_setup1: rx-queues-config {
snps,rx-queues-to-use = <4>;
snps,rx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x0>;
snps,route-up;
snps,priority = <0x1>;
};
queue1 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x1>;
snps,route-ptp;
};
queue2 {
snps,avb-algorithm;
snps,map-to-dma-channel = <0x2>;
snps,route-avcp;
};
queue3 {
snps,avb-algorithm;
snps,map-to-dma-channel = <0x3>;
snps,priority = <0xc>;
};
};
mtl_tx_setup1: tx-queues-config {
snps,tx-queues-to-use = <4>;
queue0 {
snps,dcb-algorithm;
};
queue1 {
snps,dcb-algorithm;
};
queue2 {
snps,avb-algorithm;
snps,send_slope = <0x1000>;
snps,idle_slope = <0x1000>;
snps,high_credit = <0x3e800>;
snps,low_credit = <0xffc18000>;
};
queue3 {
snps,avb-algorithm;
snps,send_slope = <0x1000>;
snps,idle_slope = <0x1000>;
snps,high_credit = <0x3e800>;
snps,low_credit = <0xffc18000>;
};
};
};
&i2c11 {
clock-frequency = <400000>;
status = "okay";
@ -960,22 +808,6 @@ dp1_hot_plug_det: dp1-hot-plug-det-state {
bias-disable;
};
ethernet0_default: ethernet0-default-state {
ethernet0_mdc: ethernet0-mdc-pins {
pins = "gpio8";
function = "emac0_mdc";
drive-strength = <16>;
bias-pull-up;
};
ethernet0_mdio: ethernet0-mdio-pins {
pins = "gpio9";
function = "emac0_mdio";
drive-strength = <16>;
bias-pull-up;
};
};
io_expander_intr_active: io-expander-intr-active-state {
pins = "gpio98";
function = "gpio";

205
arch/arm64/boot/dts/qcom/lemans-ride-ethernet-88ea1512.dtsi Normal file
View File

@ -0,0 +1,205 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023, Linaro Limited
*/
/*
* Ethernet card for Lemans based Ride boards.
* It supports 2x 1G - SGMII (Marvell 88EA1512-B2) phy for Main domain
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
aliases {
ethernet0 = &ethernet0;
ethernet1 = &ethernet1;
};
};
&tlmm {
ethernet0_default: ethernet0-default-state {
ethernet0_mdc: ethernet0-mdc-pins {
pins = "gpio8";
function = "emac0_mdc";
drive-strength = <16>;
bias-pull-up;
};
ethernet0_mdio: ethernet0-mdio-pins {
pins = "gpio9";
function = "emac0_mdio";
drive-strength = <16>;
bias-pull-up;
};
};
};
&ethernet0 {
phy-handle = <&sgmii_phy0>;
phy-mode = "sgmii";
pinctrl-0 = <&ethernet0_default>;
pinctrl-names = "default";
snps,mtl-rx-config = <&mtl_rx_setup>;
snps,mtl-tx-config = <&mtl_tx_setup>;
snps,ps-speed = <1000>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
sgmii_phy0: phy@8 {
compatible = "ethernet-phy-id0141.0dd4";
reg = <0x8>;
device_type = "ethernet-phy";
interrupts-extended = <&tlmm 7 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>;
reset-assert-us = <11000>;
reset-deassert-us = <70000>;
};
sgmii_phy1: phy@a {
compatible = "ethernet-phy-id0141.0dd4";
reg = <0xa>;
device_type = "ethernet-phy";
interrupts-extended = <&tlmm 26 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>;
reset-assert-us = <11000>;
reset-deassert-us = <70000>;
};
};
mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <4>;
snps,rx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x0>;
snps,route-up;
snps,priority = <0x1>;
};
queue1 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x1>;
snps,route-ptp;
};
queue2 {
snps,avb-algorithm;
snps,map-to-dma-channel = <0x2>;
snps,route-avcp;
};
queue3 {
snps,avb-algorithm;
snps,map-to-dma-channel = <0x3>;
snps,priority = <0xc>;
};
};
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <4>;
queue0 {
snps,dcb-algorithm;
};
queue1 {
snps,dcb-algorithm;
};
queue2 {
snps,avb-algorithm;
snps,send_slope = <0x1000>;
snps,idle_slope = <0x1000>;
snps,high_credit = <0x3e800>;
snps,low_credit = <0xffc18000>;
};
queue3 {
snps,avb-algorithm;
snps,send_slope = <0x1000>;
snps,idle_slope = <0x1000>;
snps,high_credit = <0x3e800>;
snps,low_credit = <0xffc18000>;
};
};
};
&ethernet1 {
phy-handle = <&sgmii_phy1>;
phy-mode = "sgmii";
snps,mtl-rx-config = <&mtl_rx_setup1>;
snps,mtl-tx-config = <&mtl_tx_setup1>;
snps,ps-speed = <1000>;
status = "okay";
mtl_rx_setup1: rx-queues-config {
snps,rx-queues-to-use = <4>;
snps,rx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x0>;
snps,route-up;
snps,priority = <0x1>;
};
queue1 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x1>;
snps,route-ptp;
};
queue2 {
snps,avb-algorithm;
snps,map-to-dma-channel = <0x2>;
snps,route-avcp;
};
queue3 {
snps,avb-algorithm;
snps,map-to-dma-channel = <0x3>;
snps,priority = <0xc>;
};
};
mtl_tx_setup1: tx-queues-config {
snps,tx-queues-to-use = <4>;
queue0 {
snps,dcb-algorithm;
};
queue1 {
snps,dcb-algorithm;
};
queue2 {
snps,avb-algorithm;
snps,send_slope = <0x1000>;
snps,idle_slope = <0x1000>;
snps,high_credit = <0x3e800>;
snps,low_credit = <0xffc18000>;
};
queue3 {
snps,avb-algorithm;
snps,send_slope = <0x1000>;
snps,idle_slope = <0x1000>;
snps,high_credit = <0x3e800>;
snps,low_credit = <0xffc18000>;
};
};
};

205
arch/arm64/boot/dts/qcom/lemans-ride-ethernet-aqr115c.dtsi Normal file
View File

@ -0,0 +1,205 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023, Linaro Limited
*/
/*
* Ethernet card for Lemans based Ride r3 boards.
* It supports 2x 2.5G - HSGMII (Marvell hsgmii) phy for Main domain
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
aliases {
ethernet0 = &ethernet0;
ethernet1 = &ethernet1;
};
};
&tlmm {
ethernet0_default: ethernet0-default-state {
ethernet0_mdc: ethernet0-mdc-pins {
pins = "gpio8";
function = "emac0_mdc";
drive-strength = <16>;
bias-pull-up;
};
ethernet0_mdio: ethernet0-mdio-pins {
pins = "gpio9";
function = "emac0_mdio";
drive-strength = <16>;
bias-pull-up;
};
};
};
&ethernet0 {
phy-handle = <&hsgmii_phy0>;
phy-mode = "2500base-x";
pinctrl-0 = <&ethernet0_default>;
pinctrl-names = "default";
snps,mtl-rx-config = <&mtl_rx_setup>;
snps,mtl-tx-config = <&mtl_tx_setup>;
snps,ps-speed = <1000>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
hsgmii_phy0: phy@8 {
compatible = "ethernet-phy-id31c3.1c33";
reg = <0x8>;
device_type = "ethernet-phy";
interrupts-extended = <&tlmm 7 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>;
reset-assert-us = <11000>;
reset-deassert-us = <70000>;
};
hsgmii_phy1: phy@0 {
compatible = "ethernet-phy-id31c3.1c33";
reg = <0x0>;
device_type = "ethernet-phy";
interrupts-extended = <&tlmm 26 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>;
reset-assert-us = <11000>;
reset-deassert-us = <70000>;
};
};
mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <4>;
snps,rx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x0>;
snps,route-up;
snps,priority = <0x1>;
};
queue1 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x1>;
snps,route-ptp;
};
queue2 {
snps,avb-algorithm;
snps,map-to-dma-channel = <0x2>;
snps,route-avcp;
};
queue3 {
snps,avb-algorithm;
snps,map-to-dma-channel = <0x3>;
snps,priority = <0xc>;
};
};
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <4>;
queue0 {
snps,dcb-algorithm;
};
queue1 {
snps,dcb-algorithm;
};
queue2 {
snps,avb-algorithm;
snps,send_slope = <0x1000>;
snps,idle_slope = <0x1000>;
snps,high_credit = <0x3e800>;
snps,low_credit = <0xffc18000>;
};
queue3 {
snps,avb-algorithm;
snps,send_slope = <0x1000>;
snps,idle_slope = <0x1000>;
snps,high_credit = <0x3e800>;
snps,low_credit = <0xffc18000>;
};
};
};
&ethernet1 {
phy-handle = <&hsgmii_phy1>;
phy-mode = "2500base-x";
snps,mtl-rx-config = <&mtl_rx_setup1>;
snps,mtl-tx-config = <&mtl_tx_setup1>;
snps,ps-speed = <1000>;
status = "okay";
mtl_rx_setup1: rx-queues-config {
snps,rx-queues-to-use = <4>;
snps,rx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x0>;
snps,route-up;
snps,priority = <0x1>;
};
queue1 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x1>;
snps,route-ptp;
};
queue2 {
snps,avb-algorithm;
snps,map-to-dma-channel = <0x2>;
snps,route-avcp;
};
queue3 {
snps,avb-algorithm;
snps,map-to-dma-channel = <0x3>;
snps,priority = <0xc>;
};
};
mtl_tx_setup1: tx-queues-config {
snps,tx-queues-to-use = <4>;
queue0 {
snps,dcb-algorithm;
};
queue1 {
snps,dcb-algorithm;
};
queue2 {
snps,avb-algorithm;
snps,send_slope = <0x1000>;
snps,idle_slope = <0x1000>;
snps,high_credit = <0x3e800>;
snps,low_credit = <0xffc18000>;
};
queue3 {
snps,avb-algorithm;
snps,send_slope = <0x1000>;
snps,idle_slope = <0x1000>;
snps,high_credit = <0x3e800>;
snps,low_credit = <0xffc18000>;
};
};
};

273
arch/arm64/boot/dts/qcom/sa8775p.dtsi → arch/arm64/boot/dts/qcom/lemans.dtsi
View File

@ -17,8 +17,8 @@
#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,gpr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
/ {
@ -514,7 +514,6 @@ firmware {
scm {
compatible = "qcom,scm-sa8775p", "qcom,scm";
qcom,dload-mode = <&tcsr 0x13000>;
memory-region = <&tz_ffi_mem>;
};
};
@ -773,6 +772,11 @@ sail_ota_mem: sail-ss@90e00000 {
no-map;
};
gunyah_md_mem: gunyah-md@91a80000 {
reg = <0x0 0x91a80000 0x0 0x80000>;
no-map;
};
aoss_backup_mem: aoss-backup@91b00000 {
reg = <0x0 0x91b00000 0x0 0x40000>;
no-map;
@ -798,12 +802,6 @@ cdt_data_backup_mem: cdt-data-backup@91ba0000 {
no-map;
};
tz_ffi_mem: tz-ffi@91c00000 {
compatible = "shared-dma-pool";
reg = <0x0 0x91c00000 0x0 0x1400000>;
no-map;
};
lpass_machine_learning_mem: lpass-machine-learning@93b00000 {
reg = <0x0 0x93b00000 0x0 0xf00000>;
no-map;
@ -815,52 +813,72 @@ adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 {
};
pil_camera_mem: pil-camera@95200000 {
reg = <0x0 0x95200000 0x0 0x500000>;
reg = <0x0 0x95200000 0x0 0x700000>;
no-map;
};
pil_adsp_mem: pil-adsp@95c00000 {
reg = <0x0 0x95c00000 0x0 0x1e00000>;
pil_adsp_mem: pil-adsp@95900000 {
reg = <0x0 0x95900000 0x0 0x1e00000>;
no-map;
};
pil_gdsp0_mem: pil-gdsp0@97b00000 {
reg = <0x0 0x97b00000 0x0 0x1e00000>;
q6_adsp_dtb_mem: q6-adsp-dtb@97700000 {
reg = <0x0 0x97700000 0x0 0x80000>;
no-map;
};
pil_gdsp1_mem: pil-gdsp1@99900000 {
reg = <0x0 0x99900000 0x0 0x1e00000>;
q6_gdsp0_dtb_mem: q6-gdsp0-dtb@97780000 {
reg = <0x0 0x97780000 0x0 0x80000>;
no-map;
};
pil_cdsp0_mem: pil-cdsp0@9b800000 {
reg = <0x0 0x9b800000 0x0 0x1e00000>;
pil_gdsp0_mem: pil-gdsp0@97800000 {
reg = <0x0 0x97800000 0x0 0x1e00000>;
no-map;
};
pil_gpu_mem: pil-gpu@9d600000 {
reg = <0x0 0x9d600000 0x0 0x2000>;
pil_gdsp1_mem: pil-gdsp1@99600000 {
reg = <0x0 0x99600000 0x0 0x1e00000>;
no-map;
};
pil_cdsp1_mem: pil-cdsp1@9d700000 {
reg = <0x0 0x9d700000 0x0 0x1e00000>;
q6_gdsp1_dtb_mem: q6-gdsp1-dtb@9b400000 {
reg = <0x0 0x9b400000 0x0 0x80000>;
no-map;
};
pil_cvp_mem: pil-cvp@9f500000 {
reg = <0x0 0x9f500000 0x0 0x700000>;
q6_cdsp0_dtb_mem: q6-cdsp0-dtb@9b480000 {
reg = <0x0 0x9b480000 0x0 0x80000>;
no-map;
};
pil_video_mem: pil-video@9fc00000 {
reg = <0x0 0x9fc00000 0x0 0x700000>;
pil_cdsp0_mem: pil-cdsp0@9b500000 {
reg = <0x0 0x9b500000 0x0 0x1e00000>;
no-map;
};
audio_mdf_mem: audio-mdf-region@ae000000 {
reg = <0x0 0xae000000 0x0 0x1000000>;
pil_gpu_mem: pil-gpu@9d300000 {
reg = <0x0 0x9d300000 0x0 0x2000>;
no-map;
};
q6_cdsp1_dtb_mem: q6-cdsp1-dtb@9d380000 {
reg = <0x0 0x9d380000 0x0 0x80000>;
no-map;
};
pil_cdsp1_mem: pil-cdsp1@9d400000 {
reg = <0x0 0x9d400000 0x0 0x1e00000>;
no-map;
};
pil_cvp_mem: pil-cvp@9f200000 {
reg = <0x0 0x9f200000 0x0 0x700000>;
no-map;
};
pil_video_mem: pil-video@9f900000 {
reg = <0x0 0x9f900000 0x0 0x1000000>;
no-map;
};
@ -869,11 +887,6 @@ firmware_mem: firmware-region@b0000000 {
no-map;
};
hyptz_reserved_mem: hyptz-reserved@beb00000 {
reg = <0x0 0xbeb00000 0x0 0x11500000>;
no-map;
};
scmi_mem: scmi-region@d0000000 {
reg = <0x0 0xd0000000 0x0 0x40000>;
no-map;
@ -915,7 +928,7 @@ deepsleep_backup_mem: deepsleep-backup@d1800000 {
};
trusted_apps_mem: trusted-apps@d1900000 {
reg = <0x0 0xd1900000 0x0 0x3800000>;
reg = <0x0 0xd1900000 0x0 0x1c00000>;
no-map;
};
@ -4405,7 +4418,7 @@ mdss0_mdp: display-controller@ae01000 {
<&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "bus",
clock-names = "nrt_bus",
"iface",
"lut",
"core",
@ -4992,6 +5005,32 @@ tlmm: pinctrl@f000000 {
gpio-ranges = <&tlmm 0 0 149>;
wakeup-parent = <&pdc>;
dp0_hot_plug_det: dp0-hot-plug-det-state {
pins = "gpio101";
function = "edp0_hot";
bias-disable;
};
dp1_hot_plug_det: dp1-hot-plug-det-state {
pins = "gpio102";
function = "edp1_hot";
bias-disable;
};
hs0_mi2s_active: hs0-mi2s-active-state {
pins = "gpio114", "gpio115", "gpio116", "gpio117";
function = "hs0_mi2s";
drive-strength = <8>;
bias-disable;
};
hs2_mi2s_active: hs2-mi2s-active-state {
pins = "gpio122", "gpio123", "gpio124", "gpio125";
function = "hs2_mi2s";
drive-strength = <8>;
bias-disable;
};
qup_i2c0_default: qup-i2c0-state {
pins = "gpio20", "gpio21";
function = "qup0_se0";
@ -5854,6 +5893,7 @@ intc: interrupt-controller@17a00000 {
reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
<0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <3>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
#redistributor-regions = <1>;
@ -6055,8 +6095,8 @@ remoteproc_gpdsp0: remoteproc@20c00000 {
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&rpmhpd RPMHPD_CX>,
<&rpmhpd RPMHPD_MXC>;
power-domains = <&rpmhpd SA8775P_CX>,
<&rpmhpd SA8775P_MXC>;
power-domain-names = "cx", "mxc";
interconnects = <&gpdsp_anoc MASTER_DSP0 0
@ -6080,6 +6120,35 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
label = "gpdsp0";
qcom,remote-pid = <17>;
fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "gdsp0";
#address-cells = <1>;
#size-cells = <0>;
compute-cb@1 {
compatible = "qcom,fastrpc-compute-cb";
reg = <1>;
iommus = <&apps_smmu 0x38a1 0x0>;
dma-coherent;
};
compute-cb@2 {
compatible = "qcom,fastrpc-compute-cb";
reg = <2>;
iommus = <&apps_smmu 0x38a2 0x0>;
dma-coherent;
};
compute-cb@3 {
compatible = "qcom,fastrpc-compute-cb";
reg = <3>;
iommus = <&apps_smmu 0x38a3 0x0>;
dma-coherent;
};
};
};
};
@ -6098,8 +6167,8 @@ remoteproc_gpdsp1: remoteproc@21c00000 {
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&rpmhpd RPMHPD_CX>,
<&rpmhpd RPMHPD_MXC>;
power-domains = <&rpmhpd SA8775P_CX>,
<&rpmhpd SA8775P_MXC>;
power-domain-names = "cx", "mxc";
interconnects = <&gpdsp_anoc MASTER_DSP1 0
@ -6123,6 +6192,35 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
label = "gpdsp1";
qcom,remote-pid = <18>;
fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "gdsp1";
#address-cells = <1>;
#size-cells = <0>;
compute-cb@1 {
compatible = "qcom,fastrpc-compute-cb";
reg = <1>;
iommus = <&apps_smmu 0x38c1 0x0>;
dma-coherent;
};
compute-cb@2 {
compatible = "qcom,fastrpc-compute-cb";
reg = <2>;
iommus = <&apps_smmu 0x38c2 0x0>;
dma-coherent;
};
compute-cb@3 {
compatible = "qcom,fastrpc-compute-cb";
reg = <3>;
iommus = <&apps_smmu 0x38c3 0x0>;
dma-coherent;
};
};
};
};
@ -6239,9 +6337,9 @@ remoteproc_cdsp0: remoteproc@26300000 {
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&rpmhpd RPMHPD_CX>,
<&rpmhpd RPMHPD_MXC>,
<&rpmhpd RPMHPD_NSP0>;
power-domains = <&rpmhpd SA8775P_CX>,
<&rpmhpd SA8775P_MXC>,
<&rpmhpd SA8775P_NSP0>;
power-domain-names = "cx", "mxc", "nsp";
interconnects = <&nspa_noc MASTER_CDSP_PROC 0
@ -6371,9 +6469,9 @@ remoteproc_cdsp1: remoteproc@2a300000 {
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&rpmhpd RPMHPD_CX>,
<&rpmhpd RPMHPD_MXC>,
<&rpmhpd RPMHPD_NSP1>;
power-domains = <&rpmhpd SA8775P_CX>,
<&rpmhpd SA8775P_MXC>,
<&rpmhpd SA8775P_NSP1>;
power-domain-names = "cx", "mxc", "nsp";
interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0
@ -6527,8 +6625,8 @@ remoteproc_adsp: remoteproc@30000000 {
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&rpmhpd RPMHPD_LCX>,
<&rpmhpd RPMHPD_LMX>;
power-domains = <&rpmhpd SA8775P_LCX>,
<&rpmhpd SA8775P_LMX>;
power-domain-names = "lcx", "lmx";
interconnects = <&lpass_ag_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>;
@ -6584,6 +6682,45 @@ compute-cb@5 {
dma-coherent;
};
};
gpr {
compatible = "qcom,gpr";
qcom,glink-channels = "adsp_apps";
qcom,domain = <GPR_DOMAIN_ID_ADSP>;
qcom,intents = <512 20>;
#address-cells = <1>;
#size-cells = <0>;
q6apm: service@1 {
compatible = "qcom,q6apm";
reg = <GPR_APM_MODULE_IID>;
#sound-dai-cells = <0>;
qcom,protection-domain = "avs/audio",
"msm/adsp/audio_pd";
q6apmbedai: bedais {
compatible = "qcom,q6apm-lpass-dais";
#sound-dai-cells = <1>;
};
q6apmdai: dais {
compatible = "qcom,q6apm-dais";
iommus = <&apps_smmu 0x3001 0x0>;
};
};
q6prm: service@2 {
compatible = "qcom,q6prm";
reg = <GPR_PRM_MODULE_IID>;
qcom,protection-domain = "avs/audio",
"msm/adsp/audio_pd";
q6prmcc: clock-controller {
compatible = "qcom,q6prm-lpass-clocks";
#clock-cells = <2>;
};
};
};
};
};
};
@ -7635,8 +7772,11 @@ pcie0: pcie@1c00000 {
iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
<0x100 &pcie_smmu 0x0001 0x1>;
resets = <&gcc GCC_PCIE_0_BCR>;
reset-names = "pci";
resets = <&gcc GCC_PCIE_0_BCR>,
<&gcc GCC_PCIE_0_LINK_DOWN_BCR>;
reset-names = "pci",
"link_down";
power-domains = <&gcc PCIE_0_GDSC>;
phys = <&pcie0_phy>;
@ -7696,7 +7836,6 @@ pcie0_ep: pcie-ep@1c00000 {
power-domains = <&gcc PCIE_0_GDSC>;
phys = <&pcie0_phy>;
phy-names = "pciephy";
max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */
num-lanes = <2>;
linux,pci-domain = <0>;
@ -7707,16 +7846,18 @@ pcie0_phy: phy@1c04000 {
compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy";
reg = <0x0 0x1c04000 0x0 0x2000>;
clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_CLKREF_EN>,
<&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
<&gcc GCC_PCIE_0_PIPE_CLK>,
<&gcc GCC_PCIE_0_PIPEDIV2_CLK>,
<&gcc GCC_PCIE_0_PHY_AUX_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe",
"pipediv2", "phy_aux";
<&gcc GCC_PCIE_0_PIPEDIV2_CLK>;
clock-names = "aux",
"cfg_ahb",
"ref",
"rchng",
"pipe",
"pipediv2";
assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
assigned-clock-rates = <100000000>;
@ -7801,8 +7942,11 @@ pcie1: pcie@1c10000 {
iommu-map = <0x0 &pcie_smmu 0x0080 0x1>,
<0x100 &pcie_smmu 0x0081 0x1>;
resets = <&gcc GCC_PCIE_1_BCR>;
reset-names = "pci";
resets = <&gcc GCC_PCIE_1_BCR>,
<&gcc GCC_PCIE_1_LINK_DOWN_BCR>;
reset-names = "pci",
"link_down";
power-domains = <&gcc PCIE_1_GDSC>;
phys = <&pcie1_phy>;
@ -7862,7 +8006,6 @@ pcie1_ep: pcie-ep@1c10000 {
power-domains = <&gcc PCIE_1_GDSC>;
phys = <&pcie1_phy>;
phy-names = "pciephy";
max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */
num-lanes = <4>;
linux,pci-domain = <1>;
@ -7873,16 +8016,18 @@ pcie1_phy: phy@1c14000 {
compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
reg = <0x0 0x1c14000 0x0 0x4000>;
clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
<&gcc GCC_PCIE_CLKREF_EN>,
<&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
<&gcc GCC_PCIE_1_PIPE_CLK>,
<&gcc GCC_PCIE_1_PIPEDIV2_CLK>,
<&gcc GCC_PCIE_1_PHY_AUX_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe",
"pipediv2", "phy_aux";
<&gcc GCC_PCIE_1_PIPEDIV2_CLK>;
clock-names = "aux",
"cfg_ahb",
"ref",
"rchng",
"pipe",
"pipediv2";
assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
assigned-clock-rates = <100000000>;

501
arch/arm64/boot/dts/qcom/monaco-evk.dts Normal file
View File

@ -0,0 +1,501 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "qcs8300.dtsi"
#include "qcs8300-pmics.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Monaco EVK";
compatible = "qcom,monaco-evk", "qcom,qcs8300";
aliases {
ethernet0 = &ethernet0;
i2c1 = &i2c1;
serial0 = &uart7;
};
chosen {
stdout-path = "serial0:115200n8";
};
dmic: audio-codec-0 {
compatible = "dmic-codec";
#sound-dai-cells = <0>;
num-channels = <1>;
};
max98357a: audio-codec-1 {
compatible = "maxim,max98357a";
#sound-dai-cells = <0>;
};
sound {
compatible = "qcom,qcs8275-sndcard";
model = "MONACO-EVK";
pinctrl-0 = <&hs0_mi2s_active>, <&mi2s1_active>;
pinctrl-names = "default";
hs0-mi2s-playback-dai-link {
link-name = "HS0 MI2S Playback";
codec {
sound-dai = <&max98357a>;
};
cpu {
sound-dai = <&q6apmbedai PRIMARY_MI2S_RX>;
};
platform {
sound-dai = <&q6apm>;
};
};
sec-mi2s-capture-dai-link {
link-name = "Secondary MI2S Capture";
codec {
sound-dai = <&dmic>;
};
cpu {
sound-dai = <&q6apmbedai SECONDARY_MI2S_TX>;
};
platform {
sound-dai = <&q6apm>;
};
};
};
};
&apps_rsc {
regulators-0 {
compatible = "qcom,pmm8654au-rpmh-regulators";
qcom,pmic-id = "a";
vreg_l3a: ldo3 {
regulator-name = "vreg_l3a";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4a: ldo4 {
regulator-name = "vreg_l4a";
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <912000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l5a: ldo5 {
regulator-name = "vreg_l5a";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6a: ldo6 {
regulator-name = "vreg_l6a";
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <912000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7a: ldo7 {
regulator-name = "vreg_l7a";
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <912000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8a: ldo8 {
regulator-name = "vreg_l8a";
regulator-min-microvolt = <2504000>;
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9a: ldo9 {
regulator-name = "vreg_l9a";
regulator-min-microvolt = <2970000>;
regulator-max-microvolt = <3072000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
};
};
regulators-1 {
compatible = "qcom,pmm8654au-rpmh-regulators";
qcom,pmic-id = "c";
vreg_s5c: smps5 {
regulator-name = "vreg_s5c";
regulator-min-microvolt = <1104000>;
regulator-max-microvolt = <1104000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l1c: ldo1 {
regulator-name = "vreg_l1c";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <512000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2c: ldo2 {
regulator-name = "vreg_l2c";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <904000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4c: ldo4 {
regulator-name = "vreg_l4c";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7c: ldo7 {
regulator-name = "vreg_l7c";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8c: ldo8 {
regulator-name = "vreg_l8c";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9c: ldo9 {
regulator-name = "vreg_l9c";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
};
};
};
&ethernet0 {
phy-mode = "2500base-x";
phy-handle = <&hsgmii_phy0>;
pinctrl-0 = <&ethernet0_default>;
pinctrl-names = "default";
snps,mtl-rx-config = <&mtl_rx_setup>;
snps,mtl-tx-config = <&mtl_tx_setup>;
nvmem-cells = <&mac_addr0>;
nvmem-cell-names = "mac-address";
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
hsgmii_phy0: ethernet-phy@1c {
compatible = "ethernet-phy-id004d.d101";
reg = <0x1c>;
reset-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
reset-assert-us = <11000>;
reset-deassert-us = <70000>;
};
};
mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <4>;
snps,rx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x0>;
snps,route-up;
snps,priority = <0x1>;
};
queue1 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x1>;
snps,route-ptp;
};
queue2 {
snps,avb-algorithm;
snps,map-to-dma-channel = <0x2>;
snps,route-avcp;
};
queue3 {
snps,avb-algorithm;
snps,map-to-dma-channel = <0x3>;
snps,priority = <0xc>;
};
};
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <4>;
queue0 {
snps,dcb-algorithm;
};
queue1 {
snps,dcb-algorithm;
};
queue2 {
snps,avb-algorithm;
snps,send_slope = <0x1000>;
snps,idle_slope = <0x1000>;
snps,high_credit = <0x3e800>;
snps,low_credit = <0xffc18000>;
};
queue3 {
snps,avb-algorithm;
snps,send_slope = <0x1000>;
snps,idle_slope = <0x1000>;
snps,high_credit = <0x3e800>;
snps,low_credit = <0xffc18000>;
};
};
};
&gpi_dma0 {
status = "okay";
};
&gpi_dma1 {
status = "okay";
};
&i2c1 {
pinctrl-0 = <&qup_i2c1_default>;
pinctrl-names = "default";
status = "okay";
eeprom0: eeprom@50 {
compatible = "atmel,24c256";
reg = <0x50>;
pagesize = <64>;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
mac_addr0: mac-addr@0 {
reg = <0x0 0x6>;
};
};
};
};
&i2c15 {
pinctrl-0 = <&qup_i2c15_default>;
pinctrl-names = "default";
status = "okay";
expander0: gpio@38 {
compatible = "ti,tca9538";
reg = <0x38>;
#gpio-cells = <2>;
gpio-controller;
};
expander1: gpio@39 {
compatible = "ti,tca9538";
reg = <0x39>;
#gpio-cells = <2>;
gpio-controller;
};
expander2: gpio@3a {
compatible = "ti,tca9538";
reg = <0x3a>;
#gpio-cells = <2>;
gpio-controller;
};
expander3: gpio@3b {
compatible = "ti,tca9538";
reg = <0x3b>;
#gpio-cells = <2>;
gpio-controller;
};
expander4: gpio@3c {
compatible = "ti,tca9538";
reg = <0x3c>;
#gpio-cells = <2>;
gpio-controller;
};
expander5: gpio@3d {
compatible = "ti,tca9538";
reg = <0x3d>;
#gpio-cells = <2>;
gpio-controller;
};
expander6: gpio@3e {
compatible = "ti,tca9538";
reg = <0x3e>;
#gpio-cells = <2>;
gpio-controller;
};
};
&iris {
status = "okay";
};
&qupv3_id_0 {
status = "okay";
};
&qupv3_id_1 {
status = "okay";
};
&remoteproc_adsp {
firmware-name = "qcom/qcs8300/adsp.mbn";
status = "okay";
};
&remoteproc_cdsp {
firmware-name = "qcom/qcs8300/cdsp0.mbn";
status = "okay";
};
&remoteproc_gpdsp {
firmware-name = "qcom/qcs8300/gpdsp0.mbn";
status = "okay";
};
&serdes0 {
phy-supply = <&vreg_l4a>;
status = "okay";
};
&tlmm {
ethernet0_default: ethernet0-default-state {
ethernet0_mdc: ethernet0-mdc-pins {
pins = "gpio5";
function = "emac0_mdc";
drive-strength = <16>;
bias-pull-up;
};
ethernet0_mdio: ethernet0-mdio-pins {
pins = "gpio6";
function = "emac0_mdio";
drive-strength = <16>;
bias-pull-up;
};
};
qup_i2c1_default: qup-i2c1-state {
pins = "gpio19", "gpio20";
function = "qup0_se1";
drive-strength = <2>;
bias-pull-up;
};
qup_i2c15_default: qup-i2c15-state {
pins = "gpio91", "gpio92";
function = "qup1_se7";
drive-strength = <2>;
bias-pull-up;
};
};
&uart7 {
status = "okay";
};
&ufs_mem_hc {
reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>;
vcc-supply = <&vreg_l8a>;
vcc-max-microamp = <1100000>;
vccq-supply = <&vreg_l4c>;
vccq-max-microamp = <1200000>;
status = "okay";
};
&ufs_mem_phy {
vdda-phy-supply = <&vreg_l4a>;
vdda-pll-supply = <&vreg_l5a>;
status = "okay";
};
&usb_1 {
status = "okay";
};
&usb_1_dwc3 {
dr_mode = "peripheral";
};
&usb_1_hsphy {
vdda-pll-supply = <&vreg_l7a>;
vdda18-supply = <&vreg_l7c>;
vdda33-supply = <&vreg_l9a>;
status = "okay";
};
&usb_qmpphy {
vdda-phy-supply = <&vreg_l7a>;
vdda-pll-supply = <&vreg_l5a>;
status = "okay";
};

8
arch/arm64/boot/dts/qcom/msm8916.dtsi
View File

@ -1834,14 +1834,6 @@ venus: video-codec@1d00000 {
iommus = <&apps_iommu 5>;
memory-region = <&venus_mem>;
status = "disabled";
video-decoder {
compatible = "venus-decoder";
};
video-encoder {
compatible = "venus-encoder";
};
};
apps_iommu: iommu@1ef0000 {

255
arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts Normal file
View File

@ -0,0 +1,255 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2025, Cristian Cozzolino
*/
/dts-v1/;
#include "msm8953.dtsi"
#include "pm8953.dtsi"
#include "pmi8950.dtsi"
/delete-node/ &cont_splash_mem;
/delete-node/ &qseecom_mem;
/ {
model = "Billion Capture+";
compatible = "flipkart,rimob", "qcom,msm8953";
chassis-type = "handset";
qcom,msm-id = <293 0>;
qcom,board-id = <0x340008 0>;
chosen {
#address-cells = <2>;
#size-cells = <2>;
ranges;
framebuffer@90001000 {
compatible = "simple-framebuffer";
reg = <0 0x90001000 0 (1920 * 1080 * 3)>;
width = <1080>;
height = <1920>;
stride = <(1080 * 3)>;
format = "r8g8b8";
power-domains = <&gcc MDSS_GDSC>;
clocks = <&gcc GCC_MDSS_AHB_CLK>,
<&gcc GCC_MDSS_AXI_CLK>,
<&gcc GCC_MDSS_VSYNC_CLK>,
<&gcc GCC_MDSS_MDP_CLK>,
<&gcc GCC_MDSS_BYTE0_CLK>,
<&gcc GCC_MDSS_PCLK0_CLK>,
<&gcc GCC_MDSS_ESC0_CLK>;
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&gpio_key_default>;
pinctrl-names = "default";
key-volume-up {
label = "Volume Up";
gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
debounce-interval = <15>;
};
};
reserved-memory {
qseecom_mem: qseecom@84a00000 {
reg = <0x0 0x84a00000 0x0 0x1900000>;
no-map;
};
cont_splash_mem: cont-splash@90001000 {
reg = <0x0 0x90001000 0x0 (1080 * 1920 * 3)>;
no-map;
};
};
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-always-on;
regulator-boot-on;
};
};
&hsusb_phy {
vdd-supply = <&pm8953_l3>;
vdda-pll-supply = <&pm8953_l7>;
vdda-phy-dpdm-supply = <&pm8953_l13>;
status = "okay";
};
&pm8953_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
};
&rpm_requests {
regulators {
compatible = "qcom,rpm-pm8953-regulators";
vdd_s1-supply = <&vph_pwr>;
vdd_s2-supply = <&vph_pwr>;
vdd_s3-supply = <&vph_pwr>;
vdd_s4-supply = <&vph_pwr>;
vdd_s5-supply = <&vph_pwr>;
vdd_s6-supply = <&vph_pwr>;
vdd_s7-supply = <&vph_pwr>;
vdd_l1-supply = <&pm8953_s3>;
vdd_l2_l3-supply = <&pm8953_s3>;
vdd_l4_l5_l6_l7_l16_l19-supply = <&pm8953_s4>;
vdd_l8_l11_l12_l13_l14_l15-supply = <&vph_pwr>;
vdd_l9_l10_l17_l18_l22-supply = <&vph_pwr>;
vdd_l23-supply = <&pm8953_s3>;
pm8953_s1: s1 {
regulator-min-microvolt = <870000>;
regulator-max-microvolt = <1156000>;
};
pm8953_s3: s3 {
regulator-min-microvolt = <1224000>;
regulator-max-microvolt = <1224000>;
};
pm8953_s4: s4 {
regulator-min-microvolt = <1900000>;
regulator-max-microvolt = <2050000>;
};
pm8953_l1: l1 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
pm8953_l2: l2 {
regulator-min-microvolt = <975000>;
regulator-max-microvolt = <1225000>;
};
pm8953_l3: l3 {
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <925000>;
};
pm8953_l5: l5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-allow-set-load;
};
pm8953_l6: l6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm8953_l7: l7 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1900000>;
};
pm8953_l8: l8 {
regulator-min-microvolt = <2900000>;
regulator-max-microvolt = <2900000>;
regulator-allow-set-load;
};
pm8953_l9: l9 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
};
pm8953_l10: l10 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
};
pm8953_l11: l11 {
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
regulator-allow-set-load;
};
pm8953_l12: l12 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2950000>;
regulator-allow-set-load;
};
pm8953_l13: l13 {
regulator-min-microvolt = <3125000>;
regulator-max-microvolt = <3125000>;
};
pm8953_l16: l16 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm8953_l17: l17 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
};
pm8953_l19: l19 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1350000>;
};
pm8953_l22: l22 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
pm8953_l23: l23 {
regulator-min-microvolt = <975000>;
regulator-max-microvolt = <1225000>;
};
};
};
&sdhc_1 {
vmmc-supply = <&pm8953_l8>;
vqmmc-supply = <&pm8953_l5>;
status = "okay";
};
&sdhc_2 {
vmmc-supply = <&pm8953_l11>;
vqmmc-supply = <&pm8953_l12>;
cd-gpios = <&tlmm 133 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
pinctrl-names = "default", "sleep";
status = "okay";
};
&tlmm {
gpio-reserved-ranges = <0 4>, <135 4>;
gpio_key_default: gpio-key-default-state {
pins = "gpio85";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
&usb3 {
status = "okay";
};
&usb3_dwc3 {
dr_mode = "peripheral";
};

162
arch/arm64/boot/dts/qcom/msm8953.dtsi
View File

@ -775,45 +775,131 @@ i2c_8_sleep: i2c-8-sleep-state {
};
spi_3_default: spi-3-default-state {
pins = "gpio10", "gpio11";
function = "blsp_spi3";
drive-strength = <2>;
bias-disable;
cs-pins {
pins = "gpio10";
function = "blsp_spi3";
drive-strength = <2>;
bias-disable;
};
spi-pins {
pins = "gpio8", "gpio9", "gpio11";
function = "blsp_spi3";
drive-strength = <12>;
bias-disable;
};
};
spi_3_sleep: spi-3-sleep-state {
pins = "gpio10", "gpio11";
function = "gpio";
drive-strength = <2>;
bias-disable;
cs-pins {
pins = "gpio10";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
spi-pins {
pins = "gpio8", "gpio9", "gpio11";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
};
spi_5_default: spi-5-default-state {
pins = "gpio18", "gpio19";
function = "blsp_spi5";
drive-strength = <2>;
bias-disable;
cs-pins {
pins = "gpio18";
function = "blsp_spi5";
drive-strength = <2>;
bias-disable;
};
spi-pins {
pins = "gpio16", "gpio17", "gpio19";
function = "blsp_spi5";
drive-strength = <12>;
bias-disable;
};
};
spi_5_sleep: spi-5-sleep-state {
pins = "gpio18", "gpio19";
function = "gpio";
drive-strength = <2>;
bias-disable;
cs-pins {
pins = "gpio18";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
spi-pins {
pins = "gpio16", "gpio17", "gpio19";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
};
spi_6_default: spi-6-default-state {
pins = "gpio22", "gpio23";
function = "blsp_spi6";
drive-strength = <2>;
bias-disable;
cs-pins {
pins = "gpio22";
function = "blsp_spi6";
drive-strength = <2>;
bias-disable;
};
spi-pins {
pins = "gpio20", "gpio21", "gpio23";
function = "blsp_spi6";
drive-strength = <12>;
bias-disable;
};
};
spi_6_sleep: spi-6-sleep-state {
pins = "gpio22", "gpio23";
function = "gpio";
drive-strength = <2>;
bias-disable;
cs-pins {
pins = "gpio22";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
spi-pins {
pins = "gpio20", "gpio21", "gpio23";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
};
spi_7_default: spi-7-default-state {
cs-pins {
pins = "gpio136";
function = "blsp_spi7";
drive-strength = <2>;
bias-disable;
};
spi-pins {
pins = "gpio135", "gpio137", "gpio138";
function = "blsp_spi7";
drive-strength = <12>;
bias-disable;
};
};
spi_7_sleep: spi-7-sleep-state {
cs-pins {
pins = "gpio136";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
spi-pins {
pins = "gpio135", "gpio137", "gpio138";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
};
uart_5_default: uart-5-default-state {
@ -1147,7 +1233,7 @@ &bimc SLV_EBI RPM_ALWAYS_TAG>,
status = "disabled";
zap-shader {
gpu_zap_shader: zap-shader {
memory-region = <&zap_shader_region>;
};
@ -1660,7 +1746,7 @@ spi_3: spi@78b7000 {
reg = <0x078b7000 0x600>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
dma-names = "tx", "rx";
@ -1751,7 +1837,7 @@ spi_5: spi@7af5000 {
reg = <0x07af5000 0x600>;
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
clocks = <&gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
dmas = <&blsp2_dma 4>, <&blsp2_dma 5>;
dma-names = "tx", "rx";
@ -1791,7 +1877,7 @@ spi_6: spi@7af6000 {
reg = <0x07af6000 0x600>;
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
dma-names = "tx", "rx";
@ -1826,6 +1912,26 @@ i2c_7: i2c@7af7000 {
status = "disabled";
};
spi_7: spi@7af7000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x07af7000 0x600>;
interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi_7_default>;
pinctrl-1 = <&spi_7_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c_8: i2c@7af8000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x07af8000 0x600>;

6
arch/arm64/boot/dts/qcom/msm8976-longcheer-l9360.dts
View File

@ -190,6 +190,12 @@ rmi4-f12@12 {
reg = <0x12>;
syna,sensor-type = <1>;
};
rmi4-f1a@1a {
reg = <0x1a>;
/* Keys listed from right to left */
linux,keycodes = <KEY_APPSELECT KEY_HOMEPAGE KEY_BACK>;
};
};
};

25
arch/arm64/boot/dts/qcom/msm8996.dtsi
View File

@ -1928,10 +1928,10 @@ pcie0: pcie@600000 {
"msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
interrupt-map = <0 0 0 1 &intc GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pcie0_state_on>;
@ -2005,10 +2005,10 @@ pcie1: pcie@608000 {
"msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
interrupt-map = <0 0 0 1 &intc GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pcie1_state_on>;
@ -2080,10 +2080,10 @@ pcie2: pcie@610000 {
"msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
interrupt-map = <0 0 0 1 &intc GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pcie2_state_on>;
@ -3766,6 +3766,7 @@ cbf: clock-controller@9a11000 {
intc: interrupt-controller@9bc0000 {
compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
#address-cells = <0>;
#interrupt-cells = <3>;
interrupt-controller;
#redistributor-regions = <1>;

6
arch/arm64/boot/dts/qcom/msm8998.dtsi
View File

@ -3082,9 +3082,9 @@ mdss_dsi1_phy: phy@c996400 {
mdss_hdmi: hdmi-tx@c9a0000 {
compatible = "qcom,hdmi-tx-8998";
reg = <0x0c9a0000 0x50c>,
<0x00780000 0x6220>,
<0x0c9e0000 0x2c>;
reg = <0x0c9a0000 0x50c>,
<0x00780000 0x6220>,
<0x0c9e0000 0x2c>;
reg-names = "core_physical",
"qfprom_physical",
"hdcp_physical";

2
arch/arm64/boot/dts/qcom/pmk8550.dtsi
View File

@ -64,7 +64,7 @@ reboot_reason: reboot-reason@48 {
};
};
pmk8550_gpios: gpio@8800 {
pmk8550_gpios: gpio@b800 {
compatible = "qcom,pmk8550-gpio", "qcom,spmi-gpio";
reg = <0xb800>;
gpio-controller;

62
arch/arm64/boot/dts/qcom/qcm2290.dtsi
View File

@ -154,6 +154,7 @@ scm: scm {
compatible = "qcom,scm-qcm2290", "qcom,scm";
clocks = <&rpmcc RPM_SMD_CE1_CLK>;
clock-names = "core";
qcom,dload-mode = <&tcsr_regs 0x13000>;
#reset-cells = <1>;
interconnects = <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG
&bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
@ -953,6 +954,11 @@ &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
qcom,ddr-config = <0x80040868>;
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
status = "disabled";
sdhc1_opp_table: opp-table {
@ -1454,6 +1460,7 @@ usb_dwc3: usb@4e00000 {
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x10>;
snps,usb3_lpm_capable;
snps,parkmode-disable-ss-quirk;
maximum-speed = "super-speed";
dr_mode = "otg";
usb-role-switch;
@ -2096,6 +2103,61 @@ apps_smmu: iommu@c600000 {
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
};
venus: video-codec@5a00000 {
compatible = "qcom,qcm2290-venus";
reg = <0 0x5a00000 0 0xf0000>;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&gcc GCC_VENUS_GDSC>,
<&gcc GCC_VCODEC0_GDSC>,
<&rpmpd QCM2290_VDDCX>;
power-domain-names = "venus",
"vcodec0",
"cx";
operating-points-v2 = <&venus_opp_table>;
clocks = <&gcc GCC_VIDEO_VENUS_CTL_CLK>,
<&gcc GCC_VIDEO_AHB_CLK>,
<&gcc GCC_VENUS_CTL_AXI_CLK>,
<&gcc GCC_VIDEO_THROTTLE_CORE_CLK>,
<&gcc GCC_VIDEO_VCODEC0_SYS_CLK>,
<&gcc GCC_VCODEC0_AXI_CLK>;
clock-names = "core",
"iface",
"bus",
"throttle",
"vcodec0_core",
"vcodec0_bus";
memory-region = <&pil_video_mem>;
iommus = <&apps_smmu 0x860 0x0>,
<&apps_smmu 0x880 0x0>,
<&apps_smmu 0x861 0x04>,
<&apps_smmu 0x863 0x0>,
<&apps_smmu 0x804 0xe0>;
interconnects = <&mmnrt_virt MASTER_VIDEO_P0 RPM_ALWAYS_TAG
&bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
<&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG
&config_noc SLAVE_VENUS_CFG RPM_ACTIVE_TAG>;
interconnect-names = "video-mem",
"cpu-cfg";
venus_opp_table: opp-table {
compatible = "operating-points-v2";
opp-133333333 {
opp-hz = /bits/ 64 <133333333>;
required-opps = <&rpmpd_opp_low_svs>;
};
opp-240000000 {
opp-hz = /bits/ 64 <240000000>;
required-opps = <&rpmpd_opp_svs>;
};
};
};
wifi: wifi@c800000 {
compatible = "qcom,wcn3990-wifi";
reg = <0x0 0x0c800000 0x0 0x800000>;

22
arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts
View File

@ -1176,6 +1176,22 @@ platform {
sound-dai = <&q6routing>;
};
};
usb-dai-link {
link-name = "USB Playback";
codec {
sound-dai = <&q6usbdai USB_RX>;
};
cpu {
sound-dai = <&q6afedai USB_RX>;
};
platform {
sound-dai = <&q6routing>;
};
};
};
&spi13 {
@ -1364,12 +1380,10 @@ &ufs_mem_phy {
};
&usb_1 {
status = "okay";
};
&usb_1_dwc3 {
dr_mode = "otg";
usb-role-switch;
status = "okay";
};
&usb_1_dwc3_hs {

214
arch/arm64/boot/dts/qcom/qcm6490-idp.dts
View File

@ -18,6 +18,7 @@
#include "pm7325.dtsi"
#include "pm8350c.dtsi"
#include "pmk8350.dtsi"
#include "qcs6490-audioreach.dtsi"
/delete-node/ &ipa_fw_mem;
/delete-node/ &rmtfs_mem;
@ -169,6 +170,30 @@ vph_pwr: vph-pwr-regulator {
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
};
wcd9370: audio-codec-0 {
compatible = "qcom,wcd9370-codec";
pinctrl-0 = <&wcd_default>;
pinctrl-names = "default";
reset-gpios = <&tlmm 83 GPIO_ACTIVE_HIGH>;
vdd-buck-supply = <&vreg_l17b_1p7>;
vdd-rxtx-supply = <&vreg_l18b_1p8>;
vdd-px-supply = <&vreg_l18b_1p8>;
vdd-mic-bias-supply = <&vreg_bob_3p296>;
qcom,micbias1-microvolt = <1800000>;
qcom,micbias2-microvolt = <1800000>;
qcom,micbias3-microvolt = <1800000>;
qcom,micbias4-microvolt = <1800000>;
qcom,rx-device = <&wcd937x_rx>;
qcom,tx-device = <&wcd937x_tx>;
#sound-dai-cells = <1>;
};
};
&apps_rsc {
@ -536,6 +561,22 @@ &gpu_zap_shader {
firmware-name = "qcom/qcm6490/a660_zap.mbn";
};
&lpass_rx_macro {
status = "okay";
};
&lpass_tx_macro {
status = "okay";
};
&lpass_va_macro {
status = "okay";
};
&lpass_wsa_macro {
status = "okay";
};
&mdss {
status = "okay";
};
@ -716,6 +757,165 @@ &sdhc_2 {
cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>;
};
&sound {
compatible = "qcom,qcm6490-idp-sndcard";
model = "QCM6490-IDP";
audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT",
"SpkrRight IN", "WSA_SPK2 OUT",
"IN1_HPHL", "HPHL_OUT",
"IN2_HPHR", "HPHR_OUT",
"AMIC2", "MIC BIAS2",
"TX DMIC0", "MIC BIAS1",
"TX DMIC1", "MIC BIAS2",
"TX DMIC2", "MIC BIAS3",
"TX SWR_ADC1", "ADC2_OUTPUT",
"VA DMIC0", "VA MIC BIAS3",
"VA DMIC1", "VA MIC BIAS3",
"VA DMIC2", "VA MIC BIAS1",
"VA DMIC3", "VA MIC BIAS1";
wsa-dai-link {
link-name = "WSA Playback";
codec {
sound-dai = <&left_spkr>, <&right_spkr>,
<&swr2 0>, <&lpass_wsa_macro 0>;
};
cpu {
sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
};
platform {
sound-dai = <&q6apm>;
};
};
wcd-playback-dai-link {
link-name = "WCD Playback";
codec {
sound-dai = <&wcd9370 0>, <&swr0 0>, <&lpass_rx_macro 0>;
};
cpu {
sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
};
platform {
sound-dai = <&q6apm>;
};
};
wcd-capture-dai-link {
link-name = "WCD Capture";
codec {
sound-dai = <&wcd9370 1>, <&swr1 0>, <&lpass_tx_macro 0>;
};
cpu {
sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
};
platform {
sound-dai = <&q6apm>;
};
};
va-dai-link {
link-name = "VA Capture";
codec {
sound-dai = <&lpass_va_macro 0>;
};
cpu {
sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
};
platform {
sound-dai = <&q6apm>;
};
};
};
&swr0 {
status = "okay";
wcd937x_rx: codec@0,4 {
compatible = "sdw20217010a00";
reg = <0 4>;
/*
* WCD9370 RX Port 1 (HPH_L/R) <==> SWR1 Port 1 (HPH_L/R)
* WCD9370 RX Port 2 (CLSH) <==> SWR1 Port 2 (CLSH)
* WCD9370 RX Port 3 (COMP_L/R) <==> SWR1 Port 3 (COMP_L/R)
* WCD9370 RX Port 4 (LO) <==> SWR1 Port 4 (LO)
* WCD9370 RX Port 5 (DSD_L/R) <==> SWR1 Port 5 (DSD)
*/
qcom,rx-port-mapping = <1 2 3 4 5>;
/*
* Static channels mapping between slave and master rx port channels.
* In the order of slave port channels, which is
* hph_l, hph_r, clsh, comp_l, comp_r, lo, dsd_r, dsd_l.
*/
qcom,rx-channel-mapping = /bits/ 8 <1 2 1 1 2 1 1 2>;
};
};
&swr1 {
status = "okay";
wcd937x_tx: codec@0,3 {
compatible = "sdw20217010a00";
reg = <0 3>;
/*
* WCD9370 TX Port 1 (ADC1) <=> SWR2 Port 2
* WCD9370 TX Port 2 (ADC2, 3) <=> SWR2 Port 2
* WCD9370 TX Port 3 (DMIC0,1,2,3 & MBHC) <=> SWR2 Port 3
* WCD9370 TX Port 4 (DMIC4,5,6,7) <=> SWR2 Port 4
*/
qcom,tx-port-mapping = <1 1 2 3>;
/*
* Static channel mapping between slave and master tx port channels.
* In the order of slave port channels which is adc1, adc2, adc3,
* mic0, dmic1, mbhc, dmic2, dmic3, dmci4, dmic5, dmic6, dmic7.
*/
qcom,tx-channel-mapping = /bits/ 8 <1 2 1 1 2 3 3 4 1 2 3 4>;
};
};
&swr2 {
status = "okay";
left_spkr: speaker@0,1 {
compatible = "sdw10217020200";
reg = <0 1>;
powerdown-gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
#sound-dai-cells = <0>;
sound-name-prefix = "SpkrLeft";
#thermal-sensor-cells = <0>;
vdd-supply = <&vreg_l18b_1p8>;
qcom,port-mapping = <1 2 3 7>;
};
right_spkr: speaker@0,2 {
compatible = "sdw10217020200";
reg = <0 2>;
powerdown-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>;
#sound-dai-cells = <0>;
sound-name-prefix = "SpkrRight";
#thermal-sensor-cells = <0>;
vdd-supply = <&vreg_l18b_1p8>;
qcom,port-mapping = <4 5 6 8>;
};
};
&tlmm {
gpio-reserved-ranges = <32 2>, /* ADSP */
<48 4>; /* NFC */
@ -725,6 +925,13 @@ sd_cd: sd-cd-state {
function = "gpio";
bias-pull-up;
};
wcd_default: wcd-reset-n-active-state {
pins = "gpio83";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
};
&uart5 {
@ -751,12 +958,9 @@ &ufs_mem_phy {
};
&usb_1 {
status = "okay";
};
&usb_1_dwc3 {
/delete-property/ usb-role-switch;
dr_mode = "peripheral";
status = "okay";
};
&usb_1_hsphy {

6
arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts
View File

@ -910,12 +910,10 @@ &ufs_mem_phy {
};
&usb_1 {
status = "okay";
};
&usb_1_dwc3 {
dr_mode = "otg";
usb-role-switch;
status = "okay";
};
&usb_1_dwc3_hs {

1
arch/arm64/boot/dts/qcom/qcs404.dtsi
View File

@ -1312,6 +1312,7 @@ pil-reloc@94c {
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <3>;
reg = <0x0b000000 0x1000>,
<0x0b002000 0x1000>;

192
arch/arm64/boot/dts/qcom/qcs615-ride.dts
View File

@ -7,17 +7,18 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include <dt-bindings/gpio/gpio.h>
#include "qcs615.dtsi"
#include "sm6150.dtsi"
#include "pm8150.dtsi"
/ {
model = "Qualcomm Technologies, Inc. QCS615 Ride";
compatible = "qcom,qcs615-ride", "qcom,qcs615";
compatible = "qcom,qcs615-ride", "qcom,qcs615", "qcom,sm6150";
chassis-type = "embedded";
aliases {
mmc0 = &sdhc_1;
mmc1 = &sdhc_2;
serial0 = &uart0;
serial1 = &uart7;
};
chosen {
@ -38,6 +39,22 @@ xo_board_clk: xo-board-clk {
};
};
vreg_conn_1p8: regulator-conn-1p8 {
compatible = "regulator-fixed";
regulator-name = "vreg_conn_1p8";
startup-delay-us = <4000>;
enable-active-high;
gpio = <&pm8150_gpios 1 GPIO_ACTIVE_HIGH>;
};
vreg_conn_pa: regulator-conn-pa {
compatible = "regulator-fixed";
regulator-name = "vreg_conn_pa";
startup-delay-us = <4000>;
enable-active-high;
gpio = <&pm8150_gpios 6 GPIO_ACTIVE_HIGH>;
};
regulator-usb2-vbus {
compatible = "regulator-fixed";
regulator-name = "USB2_VBUS";
@ -47,6 +64,69 @@ regulator-usb2-vbus {
enable-active-high;
regulator-always-on;
};
wcn6855-pmu {
compatible = "qcom,wcn6855-pmu";
pinctrl-0 = <&bt_en_state>, <&wlan_en_state>;
pinctrl-names = "default";
bt-enable-gpios = <&tlmm 85 GPIO_ACTIVE_HIGH>;
wlan-enable-gpios = <&tlmm 98 GPIO_ACTIVE_HIGH>;
vddio-supply = <&vreg_conn_pa>;
vddaon-supply = <&vreg_s5a>;
vddpmu-supply = <&vreg_conn_1p8>;
vddpmumx-supply = <&vreg_conn_1p8>;
vddpmucx-supply = <&vreg_conn_pa>;
vddrfa0p95-supply = <&vreg_s5a>;
vddrfa1p3-supply = <&vreg_s6a>;
vddrfa1p9-supply = <&vreg_l15a>;
vddpcie1p3-supply = <&vreg_s6a>;
vddpcie1p9-supply = <&vreg_l15a>;
regulators {
vreg_pmu_rfa_cmn: ldo0 {
regulator-name = "vreg_pmu_rfa_cmn";
};
vreg_pmu_aon_0p59: ldo1 {
regulator-name = "vreg_pmu_aon_0p59";
};
vreg_pmu_wlcx_0p8: ldo2 {
regulator-name = "vreg_pmu_wlcx_0p8";
};
vreg_pmu_wlmx_0p85: ldo3 {
regulator-name = "vreg_pmu_wlmx_0p85";
};
vreg_pmu_btcmx_0p85: ldo4 {
regulator-name = "vreg_pmu_btcmx_0p85";
};
vreg_pmu_rfa_0p8: ldo5 {
regulator-name = "vreg_pmu_rfa_0p8";
};
vreg_pmu_rfa_1p2: ldo6 {
regulator-name = "vreg_pmu_rfa_1p2";
};
vreg_pmu_rfa_1p7: ldo7 {
regulator-name = "vreg_pmu_rfa_1p7";
};
vreg_pmu_pcie_0p9: ldo8 {
regulator-name = "vreg_pmu_pcie_0p9";
};
vreg_pmu_pcie_1p8: ldo9 {
regulator-name = "vreg_pmu_pcie_1p8";
};
};
};
};
&apps_rsc {
@ -166,10 +246,7 @@ vreg_l12a: ldo12 {
regulator-name = "vreg_l12a";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1890000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l13a: ldo13 {
@ -211,10 +288,40 @@ vreg_l17a: ldo17 {
};
};
&gcc {
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
&pcie {
perst-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pcie_default_state>;
pinctrl-names = "default";
status = "okay";
};
&pcie_phy {
vdda-phy-supply = <&vreg_l5a>;
vdda-pll-supply = <&vreg_l12a>;
status = "okay";
};
&pcie_port0 {
wifi@0 {
compatible = "pci17cb,1103";
reg = <0x10000 0x0 0x0 0x0 0x0>;
qcom,calibration-variant = "QC_QCS615_Ride";
vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
vddaon-supply = <&vreg_pmu_aon_0p59>;
vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>;
vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
};
};
&pm8150_gpios {
@ -240,6 +347,10 @@ &qupv3_id_0 {
status = "okay";
};
&qupv3_id_1 {
status = "okay";
};
&remoteproc_adsp {
firmware-name = "qcom/qcs615/adsp.mbn";
@ -252,8 +363,43 @@ &remoteproc_cdsp {
status = "okay";
};
&rpmhcc {
clocks = <&xo_board_clk>;
&tlmm {
bt_en_state: bt-en-state {
pins = "gpio85";
function = "gpio";
bias-pull-down;
output-low;
};
pcie_default_state: pcie-default-state {
clkreq-pins {
pins = "gpio90";
function = "pcie_clk_req";
drive-strength = <2>;
bias-pull-up;
};
perst-pins {
pins = "gpio101";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
wake-pins {
pins = "gpio100";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
wlan_en_state: wlan-en-state {
pins = "gpio98";
function = "gpio";
bias-pull-down;
output-low;
};
};
&sdhc_1 {
@ -294,6 +440,24 @@ &uart0 {
status = "okay";
};
&uart7 {
status = "okay";
bluetooth {
compatible = "qcom,wcn6855-bt";
firmware-name = "QCA6698/hpnv21", "QCA6698/hpbtfw21.tlv";
vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
vddaon-supply = <&vreg_pmu_aon_0p59>;
vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>;
vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>;
};
};
&usb_1_hsphy {
vdd-supply = <&vreg_l5a>;
vdda-pll-supply = <&vreg_l12a>;
@ -350,6 +514,6 @@ &ufs_mem_phy {
status = "okay";
};
&watchdog {
clocks = <&sleep_clk>;
&venus {
status = "okay";
};

119
arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi Normal file
View File

@ -0,0 +1,119 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*
* Common definitions for SC7280-based boards with AudioReach.
*/
#include <dt-bindings/clock/qcom,lpass-sc7280.h>
#include <dt-bindings/soc/qcom,gpr.h>
#include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
&lpass_rx_macro {
/delete-property/ power-domains;
/delete-property/ power-domain-names;
clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&lpass_va_macro>;
clock-names = "mclk",
"npl",
"macro",
"dcodec",
"fsgen";
};
&lpass_tlmm {
clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "core",
"audio";
};
&lpass_tx_macro {
/delete-property/ power-domains;
/delete-property/ power-domain-names;
clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&lpass_va_macro>;
clock-names = "mclk",
"npl",
"macro",
"dcodec",
"fsgen";
};
&lpass_va_macro {
/delete-property/ power-domains;
/delete-property/ power-domain-names;
clocks = <&q6prmcc LPASS_CLK_ID_VA_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "mclk",
"macro",
"dcodec";
pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>,
<&lpass_dmic23_clk>, <&lpass_dmic23_data>;
pinctrl-names = "default";
qcom,dmic-sample-rate = <4800000>;
};
&lpass_wsa_macro {
clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&lpass_va_macro>;
clock-names = "mclk",
"npl",
"macro",
"dcodec",
"fsgen";
};
&remoteproc_adsp_glink {
/delete-node/ apr;
gpr {
compatible = "qcom,gpr";
qcom,glink-channels = "adsp_apps";
qcom,domain = <GPR_DOMAIN_ID_ADSP>;
qcom,intents = <512 20>;
#address-cells = <1>;
#size-cells = <0>;
q6apm: service@1 {
compatible = "qcom,q6apm";
reg = <GPR_APM_MODULE_IID>;
#sound-dai-cells = <0>;
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
q6apmdai: dais {
compatible = "qcom,q6apm-dais";
iommus = <&apps_smmu 0x1801 0x0>;
};
q6apmbedai: bedais {
compatible = "qcom,q6apm-lpass-dais";
#sound-dai-cells = <1>;
};
};
q6prm: service@2 {
compatible = "qcom,q6prm";
reg = <GPR_PRM_MODULE_IID>;
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
q6prmcc: clock-controller {
compatible = "qcom,q6prm-lpass-clocks";
#clock-cells = <2>;
};
};
};
};

88
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
View File

@ -19,6 +19,7 @@
#include "pm7325.dtsi"
#include "pm8350c.dtsi"
#include "pmk8350.dtsi"
#include "qcs6490-audioreach.dtsi"
/delete-node/ &ipa_fw_mem;
/delete-node/ &rmtfs_mem;
@ -765,6 +766,14 @@ redriver_usb_con_sbu: endpoint {
};
};
&lpass_va_macro {
status = "okay";
};
&lpass_wsa_macro {
status = "okay";
};
&mdss {
status = "okay";
};
@ -811,7 +820,7 @@ &mdss_edp_phy {
&pcie1 {
perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>;
pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>, <&pcie1_clkreq_n>;
pinctrl-names = "default";
iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
@ -1039,6 +1048,77 @@ &sdhc_2 {
status = "okay";
};
&sound {
compatible = "qcom,qcs6490-rb3gen2-sndcard";
model = "QCS6490-RB3Gen2";
audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT",
"SpkrRight IN", "WSA_SPK2 OUT",
"VA DMIC0", "vdd-micb",
"VA DMIC1", "vdd-micb",
"VA DMIC2", "vdd-micb",
"VA DMIC3", "vdd-micb";
wsa-dai-link {
link-name = "WSA Playback";
codec {
sound-dai = <&left_spkr>, <&right_spkr>,
<&swr2 0>, <&lpass_wsa_macro 0>;
};
cpu {
sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
};
platform {
sound-dai = <&q6apm>;
};
};
va-dai-link {
link-name = "VA Capture";
codec {
sound-dai = <&lpass_va_macro 0>;
};
cpu {
sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
};
platform {
sound-dai = <&q6apm>;
};
};
};
&swr2 {
status = "okay";
left_spkr: speaker@0,1 {
compatible = "sdw10217020200";
reg = <0 1>;
reset-gpios = <&tlmm 158 GPIO_ACTIVE_LOW>;
#sound-dai-cells = <0>;
sound-name-prefix = "SpkrLeft";
#thermal-sensor-cells = <0>;
vdd-supply = <&vreg_l18b_1p8>;
qcom,port-mapping = <1 2 3 7>;
};
right_spkr: speaker@0,2 {
compatible = "sdw10217020200";
reg = <0 2>;
reset-gpios = <&tlmm 158 GPIO_ACTIVE_LOW>;
#sound-dai-cells = <0>;
sound-name-prefix = "SpkrRight";
#thermal-sensor-cells = <0>;
vdd-supply = <&vreg_l18b_1p8>;
qcom,port-mapping = <4 5 6 8>;
};
};
&tlmm {
gpio-reserved-ranges = <32 2>, /* ADSP */
<48 4>; /* NFC */
@ -1127,12 +1207,10 @@ bluetooth: bluetooth {
};
&usb_1 {
status = "okay";
};
&usb_1_dwc3 {
dr_mode = "otg";
usb-role-switch;
status = "okay";
};
&usb_1_dwc3_hs {

21
arch/arm64/boot/dts/qcom/qcs8300-ride.dts
View File

@ -17,6 +17,7 @@ / {
aliases {
serial0 = &uart7;
mmc0 = &sdhc_1;
};
chosen {
@ -332,6 +333,26 @@ &serdes0 {
status = "okay";
};
&sdhc_1 {
pinctrl-0 = <&sdc1_state_on>;
pinctrl-1 = <&sdc1_state_off>;
pinctrl-names = "default", "sleep";
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
vmmc-supply = <&vreg_l8a>;
vqmmc-supply = <&vreg_s4a>;
non-removable;
no-sd;
no-sdio;
status = "okay";
};
&tlmm {
ethernet0_default: ethernet0-default-state {
ethernet0_mdc: ethernet0-mdc-pins {

499
arch/arm64/boot/dts/qcom/qcs8300.dtsi
View File

@ -12,11 +12,13 @@
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,gpr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
/ {
@ -53,6 +55,11 @@ cpu0: cpu@0 {
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <472>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&epss_l3_cl0 MASTER_EPSS_L3_APPS
&epss_l3_cl0 SLAVE_EPSS_L3_SHARED>;
l2_0: l2-cache {
compatible = "cache";
@ -73,6 +80,11 @@ cpu1: cpu@100 {
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <472>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&epss_l3_cl0 MASTER_EPSS_L3_APPS
&epss_l3_cl0 SLAVE_EPSS_L3_SHARED>;
l2_1: l2-cache {
compatible = "cache";
@ -93,6 +105,11 @@ cpu2: cpu@200 {
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <507>;
qcom,freq-domain = <&cpufreq_hw 2>;
operating-points-v2 = <&cpu2_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&epss_l3_cl0 MASTER_EPSS_L3_APPS
&epss_l3_cl0 SLAVE_EPSS_L3_SHARED>;
l2_2: l2-cache {
compatible = "cache";
@ -113,6 +130,11 @@ cpu3: cpu@300 {
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <507>;
qcom,freq-domain = <&cpufreq_hw 2>;
operating-points-v2 = <&cpu2_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&epss_l3_cl0 MASTER_EPSS_L3_APPS
&epss_l3_cl0 SLAVE_EPSS_L3_SHARED>;
l2_3: l2-cache {
compatible = "cache";
@ -133,6 +155,11 @@ cpu4: cpu@10000 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&epss_l3_cl1 MASTER_EPSS_L3_APPS
&epss_l3_cl1 SLAVE_EPSS_L3_SHARED>;
l2_4: l2-cache {
compatible = "cache";
@ -153,6 +180,11 @@ cpu5: cpu@10100 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&epss_l3_cl1 MASTER_EPSS_L3_APPS
&epss_l3_cl1 SLAVE_EPSS_L3_SHARED>;
l2_5: l2-cache {
compatible = "cache";
@ -173,6 +205,11 @@ cpu6: cpu@10200 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&epss_l3_cl1 MASTER_EPSS_L3_APPS
&epss_l3_cl1 SLAVE_EPSS_L3_SHARED>;
l2_6: l2-cache {
compatible = "cache";
@ -193,6 +230,11 @@ cpu7: cpu@10300 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&epss_l3_cl1 MASTER_EPSS_L3_APPS
&epss_l3_cl1 SLAVE_EPSS_L3_SHARED>;
l2_7: l2-cache {
compatible = "cache";
@ -323,6 +365,248 @@ system_sleep: domain-sleep {
};
};
cpu0_opp_table: opp-table-cpu0 {
compatible = "operating-points-v2";
opp-shared;
opp-902400000 {
opp-hz = /bits/ 64 <902400000>;
opp-peak-kBps = <(681600 * 4) (921600 * 32)>;
};
opp-1017600000 {
opp-hz = /bits/ 64 <1017600000>;
opp-peak-kBps = <(1017600 * 4) (921600 * 32)>;
};
opp-1190400000 {
opp-hz = /bits/ 64 <1190400000>;
opp-peak-kBps = <(1708800 * 4) (921600 * 32)>;
};
opp-1267200000 {
opp-hz = /bits/ 64 <1267200000>;
opp-peak-kBps = <(2092800 * 4) (998400 * 32)>;
};
opp-1344000000 {
opp-hz = /bits/ 64 <1344000000>;
opp-peak-kBps = <(2092800 * 4) (1075200 * 32)>;
};
opp-1420800000 {
opp-hz = /bits/ 64 <1420800000>;
opp-peak-kBps = <(2092800 * 4) (1152000 * 32)>;
};
opp-1497600000 {
opp-hz = /bits/ 64 <1497600000>;
opp-peak-kBps = <(2092800 * 4) (1228800 * 32)>;
};
opp-1574400000 {
opp-hz = /bits/ 64 <1574400000>;
opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>;
};
opp-1670400000 {
opp-hz = /bits/ 64 <1670400000>;
opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>;
};
opp-1747200000 {
opp-hz = /bits/ 64 <1747200000>;
opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>;
};
opp-1824000000 {
opp-hz = /bits/ 64 <1824000000>;
opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>;
};
opp-1900800000 {
opp-hz = /bits/ 64 <1900800000>;
opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>;
};
opp-1977600000 {
opp-hz = /bits/ 64 <1977600000>;
opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>;
};
opp-2054400000 {
opp-hz = /bits/ 64 <2054400000>;
opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>;
};
opp-2112000000 {
opp-hz = /bits/ 64 <2112000000>;
opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
};
};
cpu2_opp_table: opp-table-cpu2 {
compatible = "operating-points-v2";
opp-shared;
opp-940800000 {
opp-hz = /bits/ 64 <940800000>;
opp-peak-kBps = <(681600 * 4) (921600 * 32)>;
};
opp-1094400000 {
opp-hz = /bits/ 64 <1094400000>;
opp-peak-kBps = <(1017600 * 4) (921600 * 32)>;
};
opp-1267200000 {
opp-hz = /bits/ 64 <1267200000>;
opp-peak-kBps = <(1708800 * 4) (921600 * 32)>;
};
opp-1344000000 {
opp-hz = /bits/ 64 <1344000000>;
opp-peak-kBps = <(2092800 * 4) (998400 * 32)>;
};
opp-1420800000 {
opp-hz = /bits/ 64 <1420800000>;
opp-peak-kBps = <(2092800 * 4) (998400 * 32)>;
};
opp-1497600000 {
opp-hz = /bits/ 64 <1497600000>;
opp-peak-kBps = <(2092800 * 4) (1075200 * 32)>;
};
opp-1574400000 {
opp-hz = /bits/ 64 <1574400000>;
opp-peak-kBps = <(2092800 * 4) (1152000 * 32)>;
};
opp-1632000000 {
opp-hz = /bits/ 64 <1632000000>;
opp-peak-kBps = <(2092800 * 4) (1228800 * 32)>;
};
opp-1708800000 {
opp-hz = /bits/ 64 <1708800000>;
opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>;
};
opp-1804800000 {
opp-hz = /bits/ 64 <1804800000>;
opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>;
};
opp-1900800000 {
opp-hz = /bits/ 64 <1900800000>;
opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>;
};
opp-1977600000 {
opp-hz = /bits/ 64 <1977600000>;
opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>;
};
opp-2054400000 {
opp-hz = /bits/ 64 <2054400000>;
opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>;
};
opp-2131200000 {
opp-hz = /bits/ 64 <2131200000>;
opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>;
};
opp-2208000000 {
opp-hz = /bits/ 64 <2208000000>;
opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>;
};
opp-2284800000 {
opp-hz = /bits/ 64 <2284800000>;
opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
};
opp-2361600000 {
opp-hz = /bits/ 64 <2361600000>;
opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
};
};
cpu4_opp_table: opp-table-cpu4 {
compatible = "operating-points-v2";
opp-shared;
opp-844800000 {
opp-hz = /bits/ 64 <844800000>;
opp-peak-kBps = <(681600 * 4) (921600 * 32)>;
};
opp-1113600000 {
opp-hz = /bits/ 64 <1113600000>;
opp-peak-kBps = <(1708800 * 4) (921600 * 32)>;
};
opp-1209600000 {
opp-hz = /bits/ 64 <1209600000>;
opp-peak-kBps = <(2092800 * 4) (998400 * 32)>;
};
opp-1305600000 {
opp-hz = /bits/ 64 <1305600000>;
opp-peak-kBps = <(2092800 * 4) (1075200 * 32)>;
};
opp-1382400000 {
opp-hz = /bits/ 64 <1382400000>;
opp-peak-kBps = <(2092800 * 4) (1152000 * 32)>;
};
opp-1459200000 {
opp-hz = /bits/ 64 <1459200000>;
opp-peak-kBps = <(2092800 * 4) (1228800 * 32)>;
};
opp-1497600000 {
opp-hz = /bits/ 64 <1497600000>;
opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>;
};
opp-1574400000 {
opp-hz = /bits/ 64 <1574400000>;
opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>;
};
opp-1651200000 {
opp-hz = /bits/ 64 <1651200000>;
opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>;
};
opp-1728000000 {
opp-hz = /bits/ 64 <1728000000>;
opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>;
};
opp-1804800000 {
opp-hz = /bits/ 64 <1804800000>;
opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>;
};
opp-1881600000 {
opp-hz = /bits/ 64 <1881600000>;
opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>;
};
opp-1958400000 {
opp-hz = /bits/ 64 <1958400000>;
opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
};
};
dummy_eud: dummy-sink {
compatible = "arm,coresight-dummy-sink";
@ -817,7 +1101,7 @@ uart1: serial@984000 {
<&qup_uart1_tx>, <&qup_uart1_rx>;
pinctrl-names = "default";
interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
@ -984,7 +1268,7 @@ i2c4: i2c@990000 {
interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
@ -1057,7 +1341,7 @@ i2c5: i2c@994000 {
interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
@ -1130,7 +1414,7 @@ i2c6: i2c@998000 {
interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
@ -2144,6 +2428,45 @@ compute-cb@5 {
dma-coherent;
};
};
gpr {
compatible = "qcom,gpr";
qcom,glink-channels = "adsp_apps";
qcom,domain = <GPR_DOMAIN_ID_ADSP>;
qcom,intents = <512 20>;
#address-cells = <1>;
#size-cells = <0>;
q6apm: service@1 {
compatible = "qcom,q6apm";
reg = <GPR_APM_MODULE_IID>;
#sound-dai-cells = <0>;
qcom,protection-domain = "avs/audio",
"msm/adsp/audio_pd";
q6apmbedai: bedais {
compatible = "qcom,q6apm-lpass-dais";
#sound-dai-cells = <1>;
};
q6apmdai: dais {
compatible = "qcom,q6apm-dais";
iommus = <&apps_smmu 0x2001 0x0>;
};
};
q6prm: service@2 {
compatible = "qcom,q6prm";
reg = <GPR_PRM_MODULE_IID>;
qcom,protection-domain = "avs/audio",
"msm/adsp/audio_pd";
q6prmcc: clock-controller {
compatible = "qcom,q6prm-lpass-clocks";
#clock-cells = <2>;
};
};
};
};
};
@ -3837,6 +4160,69 @@ cti@6900000 {
clock-names = "apb_pclk";
};
sdhc_1: mmc@87c4000 {
compatible = "qcom,qcs8300-sdhci", "qcom,sdhci-msm-v5";
reg = <0x0 0x087c4000 0x0 0x1000>,
<0x0 0x087c5000 0x0 0x1000>;
reg-names = "hc",
"cqhci";
interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq",
"pwr_irq";
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface",
"core",
"xo";
resets = <&gcc GCC_SDCC1_BCR>;
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&sdhc1_opp_table>;
iommus = <&apps_smmu 0x0 0x0>;
interconnects = <&aggre1_noc MASTER_SDC QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_SDC1 QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "sdhc-ddr",
"cpu-sdhc";
qcom,dll-config = <0x000f64ee>;
qcom,ddr-config = <0x80040868>;
supports-cqe;
dma-coherent;
status = "disabled";
sdhc1_opp_table: opp-table {
compatible = "operating-points-v2";
opp-50000000 {
opp-hz = /bits/ 64 <50000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
opp-384000000 {
opp-hz = /bits/ 64 <384000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
};
usb_1_hsphy: phy@8904000 {
compatible = "qcom,qcs8300-usb-hs-phy",
"qcom,usb-snps-hs-7nm-phy";
@ -4418,6 +4804,43 @@ tlmm: pinctrl@f100000 {
#interrupt-cells = <2>;
wakeup-parent = <&pdc>;
hs0_mi2s_active: hs0-mi2s-active-state {
pins = "gpio106", "gpio107", "gpio108", "gpio109";
function = "hs0_mi2s";
drive-strength = <8>;
bias-disable;
};
mi2s1_active: mi2s1-active-state {
data0-pins {
pins = "gpio100";
function = "mi2s1_data0";
drive-strength = <8>;
bias-disable;
};
data1-pins {
pins = "gpio101";
function = "mi2s1_data1";
drive-strength = <8>;
bias-disable;
};
sclk-pins {
pins = "gpio98";
function = "mi2s1_sck";
drive-strength = <8>;
bias-disable;
};
ws-pins {
pins = "gpio99";
function = "mi2s1_ws";
drive-strength = <8>;
bias-disable;
};
};
qup_i2c0_data_clk: qup-i2c0-data-clk-state {
pins = "gpio17", "gpio18";
function = "qup0_se0";
@ -5042,6 +5465,56 @@ qup_uart16_rx: qup-uart16-rx-state {
pins = "gpio13";
function = "qup2_se0";
};
sdc1_state_on: sdc1-on-state {
clk-pins {
pins = "sdc1_clk";
drive-strength = <16>;
bias-disable;
};
cmd-pins {
pins = "sdc1_cmd";
drive-strength = <10>;
bias-pull-up;
};
data-pins {
pins = "sdc1_data";
drive-strength = <10>;
bias-pull-up;
};
rclk-pins {
pins = "sdc1_rclk";
bias-pull-down;
};
};
sdc1_state_off: sdc1-off-state {
clk-pins {
pins = "sdc1_clk";
drive-strength = <2>;
bias-bus-hold;
};
cmd-pins {
pins = "sdc1_cmd";
drive-strength = <2>;
bias-bus-hold;
};
data-pins {
pins = "sdc1_data";
drive-strength = <2>;
bias-bus-hold;
};
rclk-pins {
pins = "sdc1_rclk";
bias-bus-hold;
};
};
};
sram: sram@146d8000 {
@ -5433,6 +5906,15 @@ rpmhpd_opp_turbo_l1: opp-9 {
};
};
epss_l3_cl0: interconnect@18590000 {
compatible = "qcom,qcs8300-epss-l3", "qcom,sa8775p-epss-l3",
"qcom,epss-l3";
reg = <0x0 0x18590000 0x0 0x1000>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
clock-names = "xo", "alternate";
#interconnect-cells = <1>;
};
cpufreq_hw: cpufreq@18591000 {
compatible = "qcom,qcs8300-cpufreq-epss", "qcom,cpufreq-epss";
reg = <0x0 0x18591000 0x0 0x1000>,
@ -5455,6 +5937,15 @@ cpufreq_hw: cpufreq@18591000 {
#freq-domain-cells = <1>;
};
epss_l3_cl1: interconnect@18592000 {
compatible = "qcom,qcs8300-epss-l3", "qcom,sa8775p-epss-l3",
"qcom,epss-l3";
reg = <0x0 0x18592000 0x0 0x1000>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
clock-names = "xo", "alternate";
#interconnect-cells = <1>;
};
remoteproc_gpdsp: remoteproc@20c00000 {
compatible = "qcom,qcs8300-gpdsp-pas", "qcom,sa8775p-gpdsp0-pas";
reg = <0x0 0x20c00000 0x0 0x10000>;

9
arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts
View File

@ -4,8 +4,13 @@
*/
/dts-v1/;
#include "sa8775p-ride-r3.dts"
#include "lemans.dtsi"
#include "lemans-pmics.dtsi"
#include "lemans-ride-common.dtsi"
#include "lemans-ride-ethernet-aqr115c.dtsi"
/ {
model = "Qualcomm QCS9100 Ride Rev3";
model = "Qualcomm Technologies, Inc. Lemans Ride Rev3";
compatible = "qcom,qcs9100-ride-r3", "qcom,qcs9100", "qcom,sa8775p";
};

9
arch/arm64/boot/dts/qcom/qcs9100-ride.dts
View File

@ -4,8 +4,13 @@
*/
/dts-v1/;
#include "sa8775p-ride.dts"
#include "lemans.dtsi"
#include "lemans-pmics.dtsi"
#include "lemans-ride-common.dtsi"
#include "lemans-ride-ethernet-88ea1512.dtsi"
/ {
model = "Qualcomm QCS9100 Ride";
model = "Qualcomm Technologies, Inc. Lemans Ride";
compatible = "qcom,qcs9100-ride", "qcom,qcs9100", "qcom,sa8775p";
};

9
arch/arm64/boot/dts/qcom/qrb2210-rb1.dts
View File

@ -5,6 +5,7 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include "qcm2290.dtsi"
#include "pm4125.dtsi"
@ -63,8 +64,8 @@ hdmi_con: endpoint {
i2c2_gpio: i2c {
compatible = "i2c-gpio";
sda-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;
scl-gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>;
sda-gpios = <&tlmm 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&tlmm 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
#address-cells = <1>;
#size-cells = <0>;
@ -698,6 +699,10 @@ &usb_qmpphy_out {
remote-endpoint = <&pm4125_ss_in>;
};
&venus {
status = "okay";
};
&wifi {
vdd-0.8-cx-mx-supply = <&pm4125_l7>;
vdd-1.8-xo-supply = <&pm4125_l13>;

5
arch/arm64/boot/dts/qcom/qrb4210-rb2.dts
View File

@ -5,6 +5,7 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/sound/qcom,q6asm.h>
@ -65,8 +66,8 @@ hdmi_con: endpoint {
i2c2_gpio: i2c {
compatible = "i2c-gpio";
sda-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;
scl-gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>;
sda-gpios = <&tlmm 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&tlmm 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
#address-cells = <1>;
#size-cells = <0>;

12
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
View File

@ -725,15 +725,11 @@ &mdss_dsi0 {
qcom,dual-dsi-mode;
qcom,master-dsi;
#endif
};
ports {
port@1 {
endpoint {
remote-endpoint = <&lt9611_a>;
data-lanes = <0 1 2 3>;
};
};
};
&mdss_dsi0_out {
remote-endpoint = <&lt9611_a>;
data-lanes = <0 1 2 3>;
};
&mdss_dsi0_phy {

96
arch/arm64/boot/dts/qcom/sa8295p-adp.dts
View File

@ -35,7 +35,7 @@ dp2-connector {
port {
dp2_connector_in: endpoint {
remote-endpoint = <&mdss1_dp0_phy_out>;
remote-endpoint = <&mdss1_dp0_out>;
};
};
};
@ -49,7 +49,7 @@ dp3-connector {
port {
dp3_connector_in: endpoint {
remote-endpoint = <&mdss1_dp1_phy_out>;
remote-endpoint = <&mdss1_dp1_out>;
};
};
};
@ -63,7 +63,7 @@ edp0-connector {
port {
edp0_connector_in: endpoint {
remote-endpoint = <&mdss0_dp2_phy_out>;
remote-endpoint = <&mdss0_dp2_out>;
};
};
};
@ -77,7 +77,7 @@ edp1-connector {
port {
edp1_connector_in: endpoint {
remote-endpoint = <&mdss0_dp3_phy_out>;
remote-endpoint = <&mdss0_dp3_out>;
};
};
};
@ -91,7 +91,7 @@ edp2-connector {
port {
edp2_connector_in: endpoint {
remote-endpoint = <&mdss1_dp2_phy_out>;
remote-endpoint = <&mdss1_dp2_out>;
};
};
};
@ -105,7 +105,7 @@ edp3-connector {
port {
edp3_connector_in: endpoint {
remote-endpoint = <&mdss1_dp3_phy_out>;
remote-endpoint = <&mdss1_dp3_out>;
};
};
};
@ -361,18 +361,12 @@ &mdss0 {
};
&mdss0_dp2 {
data-lanes = <0 1 2 3>;
status = "okay";
};
ports {
port@1 {
reg = <1>;
mdss0_dp2_phy_out: endpoint {
remote-endpoint = <&edp0_connector_in>;
};
};
};
&mdss0_dp2_out {
data-lanes = <0 1 2 3>;
remote-endpoint = <&edp0_connector_in>;
};
&mdss0_dp2_phy {
@ -383,18 +377,12 @@ &mdss0_dp2_phy {
};
&mdss0_dp3 {
data-lanes = <0 1 2 3>;
status = "okay";
};
ports {
port@1 {
reg = <1>;
mdss0_dp3_phy_out: endpoint {
remote-endpoint = <&edp1_connector_in>;
};
};
};
&mdss0_dp3_out {
data-lanes = <0 1 2 3>;
remote-endpoint = <&edp1_connector_in>;
};
&mdss0_dp3_phy {
@ -409,18 +397,12 @@ &mdss1 {
};
&mdss1_dp0 {
data-lanes = <0 1 2 3>;
status = "okay";
};
ports {
port@1 {
reg = <1>;
mdss1_dp0_phy_out: endpoint {
remote-endpoint = <&dp2_connector_in>;
};
};
};
&mdss1_dp0_out {
data-lanes = <0 1 2 3>;
remote-endpoint = <&dp2_connector_in>;
};
&mdss1_dp0_phy {
@ -431,18 +413,12 @@ &mdss1_dp0_phy {
};
&mdss1_dp1 {
data-lanes = <0 1 2 3>;
status = "okay";
};
ports {
port@1 {
reg = <1>;
mdss1_dp1_phy_out: endpoint {
remote-endpoint = <&dp3_connector_in>;
};
};
};
&mdss1_dp1_out {
data-lanes = <0 1 2 3>;
remote-endpoint = <&dp3_connector_in>;
};
&mdss1_dp1_phy {
@ -453,18 +429,12 @@ &mdss1_dp1_phy {
};
&mdss1_dp2 {
data-lanes = <0 1 2 3>;
status = "okay";
};
ports {
port@1 {
reg = <1>;
mdss1_dp2_phy_out: endpoint {
remote-endpoint = <&edp2_connector_in>;
};
};
};
&mdss1_dp2_out {
data-lanes = <0 1 2 3>;
remote-endpoint = <&edp2_connector_in>;
};
&mdss1_dp2_phy {
@ -475,18 +445,12 @@ &mdss1_dp2_phy {
};
&mdss1_dp3 {
data-lanes = <0 1 2 3>;
status = "okay";
};
ports {
port@1 {
reg = <1>;
mdss1_dp3_phy_out: endpoint {
remote-endpoint = <&edp3_connector_in>;
};
};
};
&mdss1_dp3_out {
data-lanes = <0 1 2 3>;
remote-endpoint = <&edp3_connector_in>;
};
&mdss1_dp3_phy {

40
arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts
View File

@ -5,43 +5,13 @@
/dts-v1/;
#include "sa8775p-ride.dtsi"
#include "lemans-auto.dtsi"
#include "lemans-pmics.dtsi"
#include "lemans-ride-common.dtsi"
#include "lemans-ride-ethernet-aqr115c.dtsi"
/ {
model = "Qualcomm SA8775P Ride Rev3";
compatible = "qcom,sa8775p-ride-r3", "qcom,sa8775p";
};
&ethernet0 {
phy-mode = "2500base-x";
};
&ethernet1 {
phy-mode = "2500base-x";
};
&mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
sgmii_phy0: phy@8 {
compatible = "ethernet-phy-id31c3.1c33";
reg = <0x8>;
device_type = "ethernet-phy";
interrupts-extended = <&tlmm 7 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>;
reset-assert-us = <11000>;
reset-deassert-us = <70000>;
};
sgmii_phy1: phy@0 {
compatible = "ethernet-phy-id31c3.1c33";
reg = <0x0>;
device_type = "ethernet-phy";
interrupts-extended = <&tlmm 26 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>;
reset-assert-us = <11000>;
reset-deassert-us = <70000>;
};
};

40
arch/arm64/boot/dts/qcom/sa8775p-ride.dts
View File

@ -5,43 +5,13 @@
/dts-v1/;
#include "sa8775p-ride.dtsi"
#include "lemans-auto.dtsi"
#include "lemans-pmics.dtsi"
#include "lemans-ride-common.dtsi"
#include "lemans-ride-ethernet-88ea1512.dtsi"
/ {
model = "Qualcomm SA8775P Ride";
compatible = "qcom,sa8775p-ride", "qcom,sa8775p";
};
&ethernet0 {
phy-mode = "sgmii";
};
&ethernet1 {
phy-mode = "sgmii";
};
&mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
sgmii_phy0: phy@8 {
compatible = "ethernet-phy-id0141.0dd4";
reg = <0x8>;
device_type = "ethernet-phy";
interrupts-extended = <&tlmm 7 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>;
reset-assert-us = <11000>;
reset-deassert-us = <70000>;
};
sgmii_phy1: phy@a {
compatible = "ethernet-phy-id0141.0dd4";
reg = <0xa>;
device_type = "ethernet-phy";
interrupts-extended = <&tlmm 26 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>;
reset-assert-us = <11000>;
reset-deassert-us = <70000>;
};
};

39
arch/arm64/boot/dts/qcom/sar2130p.dtsi
View File

@ -3,6 +3,7 @@
* Copyright (c) 2024, Linaro Limited
*/
#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sar2130p-gcc.h>
#include <dt-bindings/clock/qcom,sar2130p-gpucc.h>
@ -1302,10 +1303,10 @@ pcie0: pcie@1c00000 {
"global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
@ -1421,10 +1422,10 @@ pcie1: pcie@1c08000 {
"global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
@ -2036,8 +2037,8 @@ mdss: display-subsystem@ae00000 {
power-domains = <&dispcc MDSS_GDSC>;
interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "mdp0-mem", "cpu-cfg";
@ -2053,7 +2054,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
mdss_mdp: display-controller@ae01000 {
compatible = "qcom,sar2130p-dpu";
reg = <0x0 0x0ae01000 0x0 0x8f000>,
<0x0 0x0aeb0000 0x0 0x2008>;
<0x0 0x0aeb0000 0x0 0x3000>;
reg-names = "mdp",
"vbif";
@ -2237,8 +2238,8 @@ mdss_dsi0: dsi@ae94000 {
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
assigned-clock-parents = <&mdss_dsi0_phy 0>,
<&mdss_dsi0_phy 1>;
assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
operating-points-v2 = <&mdss_dsi_opp_table>;
@ -2333,8 +2334,8 @@ mdss_dsi1: dsi@ae96000 {
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
<&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
assigned-clock-parents = <&mdss_dsi1_phy 0>,
<&mdss_dsi1_phy 1>;
assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
<&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>;
operating-points-v2 = <&mdss_dsi_opp_table>;
@ -2392,10 +2393,10 @@ dispcc: clock-controller@af00000 {
<&rpmhcc RPMH_CXO_CLK_A>,
<&gcc GCC_DISP_AHB_CLK>,
<&sleep_clk>,
<&mdss_dsi0_phy 0>,
<&mdss_dsi0_phy 1>,
<&mdss_dsi1_phy 0>,
<&mdss_dsi1_phy 1>,
<&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
<&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
<&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>,
<&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<0>, /* dp1 */

6
arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts
View File

@ -438,15 +438,11 @@ &mdss {
};
&mdss_dp {
data-lanes = <0 1>;
vdda-1p2-supply = <&vreg_l3c_1p2>;
vdda-0p9-supply = <&vreg_l4a_0p8>;
status = "okay";
};
&mdss_dp_out {
data-lanes = <0 1>;
remote-endpoint = <&ec_dp_in>;
};

12
arch/arm64/boot/dts/qcom/sc7180-idp.dts
View File

@ -323,15 +323,11 @@ panel0_in: endpoint {
};
};
};
};
ports {
port@1 {
endpoint {
remote-endpoint = <&panel0_in>;
data-lanes = <0 1 2 3>;
};
};
};
&mdss_dsi0_out {
remote-endpoint = <&panel0_in>;
data-lanes = <0 1 2 3>;
};
&mdss_dsi0_phy {

12
arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi
View File

@ -90,15 +90,11 @@ panel_in: endpoint {
};
};
};
};
ports {
port@1 {
endpoint {
remote-endpoint = <&panel_in>;
data-lanes = <0 1 2 3>;
};
};
};
&mdss_dsi0_out {
remote-endpoint = <&panel_in>;
data-lanes = <0 1 2 3>;
};
&sdhc_2 {

12
arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi
View File

@ -148,15 +148,11 @@ panel_in: endpoint {
};
};
};
};
ports {
port@1 {
endpoint {
remote-endpoint = <&panel_in>;
data-lanes = <0 1 2 3>;
};
};
};
&mdss_dsi0_out {
remote-endpoint = <&panel_in>;
data-lanes = <0 1 2 3>;
};
&pm6150_adc {

56
arch/arm64/boot/dts/qcom/sc7180.dtsi
View File

@ -2897,6 +2897,31 @@ usb_1_qmpphy: phy@88e8000 {
#clock-cells = <1>;
#phy-cells = <1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_1_qmpphy_out: endpoint { };
};
port@1 {
reg = <1>;
usb_1_qmpphy_usb_ss_in: endpoint {
remote-endpoint = <&usb_1_dwc3_ss>;
};
};
port@2 {
reg = <2>;
usb_1_qmpphy_dp_in: endpoint { };
};
};
};
pmu@90b6300 {
@ -3070,6 +3095,26 @@ usb_1_dwc3: usb@a600000 {
phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
maximum-speed = "super-speed";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_1_dwc3_hs: endpoint {
};
};
port@1 {
reg = <1>;
usb_1_dwc3_ss: endpoint {
remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
};
};
};
};
};
@ -3095,14 +3140,6 @@ venus: video-codec@aa00000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
interconnect-names = "video-mem", "cpu-cfg";
video-decoder {
compatible = "venus-decoder";
};
video-encoder {
compatible = "venus-encoder";
};
venus_opp_table: opp-table {
compatible = "operating-points-v2";
@ -3392,8 +3429,10 @@ mdss_dp: displayport-controller@ae90000 {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dp_in: endpoint {
remote-endpoint = <&dpu_intf0_out>;
};
@ -3401,6 +3440,7 @@ dp_in: endpoint {
port@1 {
reg = <1>;
mdss_dp_out: endpoint { };
};
};

5
arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
View File

@ -44,11 +44,6 @@ camera_mem: memory@8ad00000 {
reg = <0x0 0x8ad00000 0x0 0x500000>;
no-map;
};
venus_mem: memory@8b200000 {
reg = <0x0 0x8b200000 0x0 0x500000>;
no-map;
};
};
};

6
arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
View File

@ -621,15 +621,13 @@ CROS_STD_MAIN_KEYMAP
};
&usb_1 {
status = "okay";
};
&usb_1_dwc3 {
dr_mode = "host";
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
/* 2.x hub on port 1 */
usb_hub_2_x: hub@1 {
compatible = "usbbda,5411";

6
arch/arm64/boot/dts/qcom/sc7280-idp.dts
View File

@ -81,11 +81,9 @@ channel@403 {
};
&usb_2 {
status = "okay";
};
&usb_2_dwc3 {
dr_mode = "otg";
status = "okay";
};
&usb_2_hsphy {

6
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
View File

@ -520,11 +520,9 @@ &ufs_mem_phy {
};
&usb_1 {
status = "okay";
};
&usb_1_dwc3 {
dr_mode = "host";
status = "okay";
};
&usb_1_hsphy {

375
arch/arm64/boot/dts/qcom/sc7280.dtsi
View File

@ -28,6 +28,7 @@
#include <dt-bindings/soc/qcom,apr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/sound/qcom,lpass.h>
#include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/sound/qcom,q6asm.h>
#include <dt-bindings/thermal/thermal.h>
@ -620,12 +621,12 @@ cpu4_opp_2208mhz: opp-2208000000 {
cpu4_opp_2400mhz: opp-2400000000 {
opp-hz = /bits/ 64 <2400000000>;
opp-peak-kBps = <8532000 48537600>;
opp-peak-kBps = <12787200 48537600>;
};
cpu4_opp_2611mhz: opp-2611200000 {
opp-hz = /bits/ 64 <2611200000>;
opp-peak-kBps = <8532000 48537600>;
opp-peak-kBps = <12787200 48537600>;
};
};
@ -685,22 +686,22 @@ cpu7_opp_2381mhz: opp-2380800000 {
cpu7_opp_2400mhz: opp-2400000000 {
opp-hz = /bits/ 64 <2400000000>;
opp-peak-kBps = <8532000 48537600>;
opp-peak-kBps = <12787200 48537600>;
};
cpu7_opp_2515mhz: opp-2515200000 {
opp-hz = /bits/ 64 <2515200000>;
opp-peak-kBps = <8532000 48537600>;
opp-peak-kBps = <12787200 48537600>;
};
cpu7_opp_2707mhz: opp-2707200000 {
opp-hz = /bits/ 64 <2707200000>;
opp-peak-kBps = <8532000 48537600>;
opp-peak-kBps = <12787200 48537600>;
};
cpu7_opp_3014mhz: opp-3014400000 {
opp-hz = /bits/ 64 <3014400000>;
opp-peak-kBps = <8532000 48537600>;
opp-peak-kBps = <12787200 48537600>;
};
};
@ -2200,6 +2201,135 @@ wifi: wifi@17a10040 {
qcom,smem-state-names = "wlan-smp2p-out";
};
pcie0: pcie@1c00000 {
compatible = "qcom,pcie-sc7280";
reg = <0 0x01c00000 0 0x3000>,
<0 0x60000000 0 0xf1d>,
<0 0x60000f20 0 0xa8>,
<0 0x60001000 0 0x1000>,
<0 0x60100000 0 0x100000>,
<0 0x01c03000 0 0x1000>;
reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
device_type = "pci";
linux,pci-domain = <0>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
"msi3",
"msi4",
"msi5",
"msi6",
"msi7",
"global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
<&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
<&pcie0_phy>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_PCIE_0_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
<&gcc GCC_DDRSS_PCIE_SF_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>;
clock-names = "pipe",
"pipe_mux",
"phy_pipe",
"ref",
"aux",
"cfg",
"bus_master",
"bus_slave",
"slave_q2a",
"tbu",
"ddrss_sf_tbu",
"aggre0",
"aggre1";
iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
<0x100 &apps_smmu 0x1c01 0x1>;
resets = <&gcc GCC_PCIE_0_BCR>;
reset-names = "pci";
power-domains = <&gcc GCC_PCIE_0_GDSC>;
phys = <&pcie0_phy>;
phy-names = "pciephy";
pinctrl-names = "default";
pinctrl-0 = <&pcie0_clkreq_n>;
dma-coherent;
status = "disabled";
pcie0_port: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
pcie0_phy: phy@1c06000 {
compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
reg = <0 0x01c06000 0 0x1000>;
clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_CLKREF_EN>,
<&gcc GCC_PCIE0_PHY_RCHNG_CLK>,
<&gcc GCC_PCIE_0_PIPE_CLK>;
clock-names = "aux",
"cfg_ahb",
"ref",
"refgen",
"pipe";
clock-output-names = "pcie_0_pipe_clk";
#clock-cells = <0>;
#phy-cells = <0>;
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
reset-names = "phy";
assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>;
assigned-clock-rates = <100000000>;
status = "disabled";
};
pcie1: pcie@1c08000 {
compatible = "qcom,pcie-sc7280";
reg = <0 0x01c08000 0 0x3000>,
@ -2240,10 +2370,10 @@ pcie1: pcie@1c08000 {
"global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
<&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
@ -2644,6 +2774,66 @@ swr1: soundwire@3230000 {
status = "disabled";
};
lpass_wsa_macro: codec@3240000 {
compatible = "qcom,sc7280-lpass-wsa-macro";
reg = <0x0 0x03240000 0x0 0x1000>;
clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>,
<&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>,
<&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&lpass_va_macro>;
clock-names = "mclk",
"npl",
"macro",
"dcodec",
"fsgen";
pinctrl-0 = <&lpass_wsa_swr_clk>, <&lpass_wsa_swr_data>;
pinctrl-names = "default";
#clock-cells = <0>;
clock-output-names = "mclk";
#sound-dai-cells = <1>;
status = "disabled";
};
swr2: soundwire@3250000 {
compatible = "qcom,soundwire-v1.6.0";
reg = <0x0 0x03250000 0x0 0x2000>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&lpass_wsa_macro>;
clock-names = "iface";
resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>;
reset-names = "swr_audio_cgcr";
qcom,din-ports = <2>;
qcom,dout-ports = <6>;
qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07
0x1f 0x3f 0x0f 0x0f>;
qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01
0xff 0xff>;
qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff
0xff 0xff>;
qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff
0xff 0xff>;
#address-cells = <2>;
#size-cells = <0>;
#sound-dai-cells = <1>;
status = "disabled";
};
lpass_audiocc: clock-controller@3300000 {
compatible = "qcom,sc7280-lpassaudiocc";
reg = <0 0x03300000 0 0x30000>,
@ -2811,41 +3001,77 @@ lpass_tlmm: pinctrl@33c0000 {
lpass_dmic01_clk: dmic01-clk-state {
pins = "gpio6";
function = "dmic1_clk";
drive-strength = <8>;
bias-disable;
};
lpass_dmic01_data: dmic01-data-state {
pins = "gpio7";
function = "dmic1_data";
drive-strength = <8>;
bias-pull-down;
};
lpass_dmic23_clk: dmic23-clk-state {
pins = "gpio8";
function = "dmic2_clk";
drive-strength = <8>;
bias-disable;
};
lpass_dmic23_data: dmic23-data-state {
pins = "gpio9";
function = "dmic2_data";
drive-strength = <8>;
bias-pull-down;
};
lpass_rx_swr_clk: rx-swr-clk-state {
pins = "gpio3";
function = "swr_rx_clk";
drive-strength = <2>;
slew-rate = <1>;
bias-disable;
};
lpass_rx_swr_data: rx-swr-data-state {
pins = "gpio4", "gpio5";
function = "swr_rx_data";
drive-strength = <2>;
slew-rate = <1>;
bias-bus-hold;
};
lpass_tx_swr_clk: tx-swr-clk-state {
pins = "gpio0";
function = "swr_tx_clk";
drive-strength = <2>;
slew-rate = <1>;
bias-disable;
};
lpass_tx_swr_data: tx-swr-data-state {
pins = "gpio1", "gpio2", "gpio14";
function = "swr_tx_data";
drive-strength = <2>;
slew-rate = <1>;
bias-bus-hold;
};
lpass_wsa_swr_clk: wsa-swr-clk-state {
pins = "gpio10";
function = "wsa_swr_clk";
drive-strength = <2>;
slew-rate = <1>;
bias-disable;
};
lpass_wsa_swr_data: wsa-swr-data-state {
pins = "gpio11";
function = "wsa_swr_data";
drive-strength = <2>;
slew-rate = <1>;
bias-bus-hold;
};
};
@ -3711,14 +3937,10 @@ usb_dp_qmpphy_dp_in: endpoint {
};
};
usb_2: usb@8cf8800 {
compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
reg = <0 0x08cf8800 0 0x400>;
usb_2: usb@8c00000 {
compatible = "qcom,sc7280-dwc3", "qcom,snps-dwc3";
reg = <0 0x08c00000 0 0xfc100>;
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
ranges;
dma-ranges;
clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
<&gcc GCC_USB30_SEC_MASTER_CLK>,
@ -3735,11 +3957,13 @@ usb_2: usb@8cf8800 {
<&gcc GCC_USB30_SEC_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
interrupts-extended = <&intc GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 12 IRQ_TYPE_EDGE_BOTH>,
<&pdc 13 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "pwr_event",
interrupt-names = "dwc_usb3",
"pwr_event",
"hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq";
@ -3753,24 +3977,19 @@ usb_2: usb@8cf8800 {
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>;
interconnect-names = "usb-ddr", "apps-usb";
usb_2_dwc3: usb@8c00000 {
compatible = "snps,dwc3";
reg = <0 0x08c00000 0 0xe000>;
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&apps_smmu 0xa0 0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
phys = <&usb_2_hsphy>;
phy-names = "usb2-phy";
maximum-speed = "high-speed";
usb-role-switch;
iommus = <&apps_smmu 0xa0 0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
phys = <&usb_2_hsphy>;
phy-names = "usb2-phy";
maximum-speed = "high-speed";
usb-role-switch;
port {
usb2_role_switch: endpoint {
remote-endpoint = <&eud_ep>;
};
port {
usb2_role_switch: endpoint {
remote-endpoint = <&eud_ep>;
};
};
};
@ -3822,7 +4041,7 @@ remoteproc_adsp: remoteproc@3700000 {
status = "disabled";
glink-edge {
remoteproc_adsp_glink: glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
@ -3862,6 +4081,13 @@ q6afecc: clock-controller {
compatible = "qcom,q6afe-clocks";
#clock-cells = <2>;
};
q6usbdai: usbd {
compatible = "qcom,q6usb";
iommus = <&apps_smmu 0x180f 0x0>;
#sound-dai-cells = <1>;
qcom,usb-audio-intr-idx = /bits/ 16 <2>;
};
};
q6asm: service@7 {
@ -4013,6 +4239,12 @@ opp-6 {
opp-7 {
opp-peak-kBps = <8532000>;
};
opp-8 {
opp-peak-kBps = <10944000>;
};
opp-9 {
opp-peak-kBps = <12787200>;
};
};
};
@ -4252,14 +4484,10 @@ compute-cb@14 {
};
};
usb_1: usb@a6f8800 {
compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
reg = <0 0x0a6f8800 0 0x400>;
usb_1: usb@a600000 {
compatible = "qcom,sc7280-dwc3", "qcom,snps-dwc3";
reg = <0 0x0a600000 0 0xfc100>;
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
ranges;
dma-ranges;
clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_MASTER_CLK>,
@ -4276,12 +4504,14 @@ usb_1: usb@a6f8800 {
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 14 IRQ_TYPE_EDGE_BOTH>,
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
interrupt-names = "dwc_usb3",
"pwr_event",
"hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
@ -4298,37 +4528,33 @@ usb_1: usb@a6f8800 {
wakeup-source;
usb_1_dwc3: usb@a600000 {
compatible = "snps,dwc3";
reg = <0 0x0a600000 0 0xe000>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&apps_smmu 0xe0 0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,parkmode-disable-ss-quirk;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
maximum-speed = "super-speed";
iommus = <&apps_smmu 0xe0 0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,parkmode-disable-ss-quirk;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
num-hc-interrupters = /bits/ 16 <3>;
phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
maximum-speed = "super-speed";
ports {
#address-cells = <1>;
#size-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
port@0 {
reg = <0>;
usb_1_dwc3_hs: endpoint {
};
usb_1_dwc3_hs: endpoint {
};
};
port@1 {
reg = <1>;
port@1 {
reg = <1>;
usb_1_dwc3_ss: endpoint {
remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
};
usb_1_dwc3_ss: endpoint {
remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
};
};
};
@ -4724,6 +4950,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
iommus = <&apps_smmu 0x900 0x402>;
resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@ -5285,6 +5513,11 @@ mi2s1_ws: mi2s1-ws-state {
function = "mi2s1_ws";
};
pcie0_clkreq_n: pcie0-clkreq-n-state {
pins = "gpio88";
function = "pcie0_clkreqn";
};
pcie1_clkreq_n: pcie1-clkreq-n-state {
pins = "gpio79";
function = "pcie1_clkreqn";

14
arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts
View File

@ -436,8 +436,6 @@ &mdss_dp1_out {
};
&mdss_edp {
data-lanes = <0 1 2 3>;
pinctrl-0 = <&edp_hpd_active>;
pinctrl-names = "default";
@ -457,15 +455,11 @@ auo_b140han06_in: endpoint {
};
};
};
};
ports {
port@1 {
reg = <1>;
mdss_edp_out: endpoint {
remote-endpoint = <&auo_b140han06_in>;
};
};
};
&mdss_edp_out {
data-lanes = <0 1 2 3>;
remote-endpoint = <&auo_b140han06_in>;
};
&pcie3 {

14
arch/arm64/boot/dts/qcom/sc8180x-primus.dts
View File

@ -531,8 +531,6 @@ &mdss_dp1_out {
};
&mdss_edp {
data-lanes = <0 1 2 3>;
pinctrl-names = "default";
pinctrl-0 = <&edp_hpd_active>;
@ -551,15 +549,11 @@ auo_b133han05_in: endpoint {
};
};
};
};
ports {
port@1 {
reg = <1>;
mdss_edp_out: endpoint {
remote-endpoint = <&auo_b133han05_in>;
};
};
};
&mdss_edp_out {
data-lanes = <0 1 2 3>;
remote-endpoint = <&auo_b133han05_in>;
};
&pcie1 {

69
arch/arm64/boot/dts/qcom/sc8180x.dtsi
View File

@ -10,6 +10,7 @@
#include <dt-bindings/clock/qcom,gpucc-sm8150.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sc8180x-camcc.h>
#include <dt-bindings/clock/qcom,videocc-sm8150.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sc8180x.h>
@ -1740,10 +1741,10 @@ pcie0: pcie@1c00000 {
"global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
<&gcc GCC_PCIE_0_AUX_CLK>,
@ -1859,10 +1860,10 @@ pcie3: pcie@1c08000 {
"global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_PCIE_3_PIPE_CLK>,
<&gcc GCC_PCIE_3_AUX_CLK>,
@ -1979,10 +1980,10 @@ pcie1: pcie@1c10000 {
"global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 746 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 745 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 744 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
interrupt-map = <0 0 0 1 &intc GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
<&gcc GCC_PCIE_1_AUX_CLK>,
@ -2099,10 +2100,10 @@ pcie2: pcie@1c18000 {
"global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 662 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 661 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 660 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
interrupt-map = <0 0 0 1 &intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
<&gcc GCC_PCIE_2_AUX_CLK>,
@ -2927,6 +2928,20 @@ usb_sec_dwc3_ss: endpoint {
};
};
videocc: clock-controller@ab00000 {
compatible = "qcom,sc8180x-videocc",
"qcom,sm8150-videocc";
reg = <0 0x0ab00000 0 0x10000>;
clocks = <&gcc GCC_VIDEO_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "bi_tcxo";
power-domains = <&rpmhpd SC8180X_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
camcc: clock-controller@ad00000 {
compatible = "qcom,sc8180x-camcc";
reg = <0 0x0ad00000 0 0x20000>;
@ -2940,7 +2955,7 @@ camcc: clock-controller@ad00000 {
#power-domain-cells = <1>;
};
mdss: mdss@ae00000 {
mdss: display-subsystem@ae00000 {
compatible = "qcom,sc8180x-mdss";
reg = <0 0x0ae00000 0 0x1000>;
reg-names = "mdss";
@ -2980,7 +2995,7 @@ &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
status = "disabled";
mdss_mdp: mdp@ae01000 {
mdss_mdp: display-controller@ae01000 {
compatible = "qcom,sc8180x-dpu";
reg = <0 0x0ae01000 0 0x8f000>,
<0 0x0aeb0000 0 0x3000>;
@ -3074,7 +3089,8 @@ opp-460000000 {
};
mdss_dsi0: dsi@ae94000 {
compatible = "qcom,mdss-dsi-ctrl";
compatible = "qcom,sc8180x-dsi-ctrl",
"qcom,mdss-dsi-ctrl";
reg = <0 0x0ae94000 0 0x400>;
reg-names = "dsi_ctrl";
@ -3140,7 +3156,7 @@ opp-358000000 {
};
};
mdss_dsi0_phy: dsi-phy@ae94400 {
mdss_dsi0_phy: phy@ae94400 {
compatible = "qcom,dsi-phy-7nm";
reg = <0 0x0ae94400 0 0x200>,
<0 0x0ae94600 0 0x280>,
@ -3160,7 +3176,8 @@ mdss_dsi0_phy: dsi-phy@ae94400 {
};
mdss_dsi1: dsi@ae96000 {
compatible = "qcom,mdss-dsi-ctrl";
compatible = "qcom,sc8180x-dsi-ctrl",
"qcom,mdss-dsi-ctrl";
reg = <0 0x0ae96000 0 0x400>;
reg-names = "dsi_ctrl";
@ -3207,7 +3224,7 @@ mdss_dsi1_out: endpoint {
};
};
mdss_dsi1_phy: dsi-phy@ae96400 {
mdss_dsi1_phy: phy@ae96400 {
compatible = "qcom,dsi-phy-7nm";
reg = <0 0x0ae96400 0 0x200>,
<0 0x0ae96600 0 0x280>,
@ -3423,6 +3440,13 @@ edp_in: endpoint {
remote-endpoint = <&dpu_intf5_out>;
};
};
port@1 {
reg = <1>;
mdss_edp_out: endpoint {
};
};
};
edp_opp_table: opp-table {
@ -3714,6 +3738,7 @@ remoteproc_adsp_glink: glink-edge {
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <3>;
reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
<0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */

23
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
View File

@ -495,6 +495,18 @@ &dispcc0 {
status = "okay";
};
&gpi_dma0 {
status = "okay";
};
&gpi_dma1 {
status = "okay";
};
&gpi_dma2 {
status = "okay";
};
&gpu {
status = "okay";
@ -548,15 +560,10 @@ edp_panel_in: endpoint {
};
};
};
};
ports {
port@1 {
reg = <1>;
mdss0_dp3_out: endpoint {
remote-endpoint = <&edp_panel_in>;
};
};
};
&mdss0_dp3_out {
remote-endpoint = <&edp_panel_in>;
};
&mdss0_dp3_phy {

12
arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts
View File

@ -586,6 +586,18 @@ &dispcc0 {
status = "okay";
};
&gpi_dma0 {
status = "okay";
};
&gpi_dma1 {
status = "okay";
};
&gpi_dma2 {
status = "okay";
};
&gpu {
status = "okay";

29
arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
View File

@ -708,6 +708,18 @@ &dispcc0 {
status = "okay";
};
&gpi_dma0 {
status = "okay";
};
&gpi_dma1 {
status = "okay";
};
&gpi_dma2 {
status = "okay";
};
&gpu {
status = "okay";
@ -726,7 +738,7 @@ &mdss0_dp0 {
};
&mdss0_dp0_out {
data-lanes = <0 1>;
data-lanes = <0 1 2 3>;
remote-endpoint = <&usb_0_qmpphy_dp_in>;
};
@ -735,7 +747,7 @@ &mdss0_dp1 {
};
&mdss0_dp1_out {
data-lanes = <0 1>;
data-lanes = <0 1 2 3>;
remote-endpoint = <&usb_1_qmpphy_dp_in>;
};
@ -761,15 +773,10 @@ edp_panel_in: endpoint {
};
};
};
};
ports {
port@1 {
reg = <1>;
mdss0_dp3_out: endpoint {
remote-endpoint = <&edp_panel_in>;
};
};
};
&mdss0_dp3_out {
remote-endpoint = <&edp_panel_in>;
};
&mdss0_dp3_phy {
@ -1360,6 +1367,7 @@ &usb_0_qmpphy {
vdda-phy-supply = <&vreg_l9d>;
vdda-pll-supply = <&vreg_l4d>;
mode-switch;
orientation-switch;
status = "okay";
@ -1397,6 +1405,7 @@ &usb_1_qmpphy {
vdda-phy-supply = <&vreg_l4b>;
vdda-pll-supply = <&vreg_l3b>;
mode-switch;
orientation-switch;
status = "okay";

12
arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts
View File

@ -448,6 +448,18 @@ &dispcc1 {
status = "okay";
};
&gpi_dma0 {
status = "okay";
};
&gpi_dma1 {
status = "okay";
};
&gpi_dma2 {
status = "okay";
};
&gpu {
status = "okay";

25
arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts
View File

@ -63,7 +63,7 @@ dp3_connector: connector {
port {
dp1_connector_in: endpoint {
remote-endpoint = <&mdss0_dp2_phy_out>;
remote-endpoint = <&mdss0_dp2_out>;
};
};
};
@ -565,6 +565,18 @@ &dispcc0 {
status = "okay";
};
&gpi_dma0 {
status = "okay";
};
&gpi_dma1 {
status = "okay";
};
&gpi_dma2 {
status = "okay";
};
&gpu {
status = "okay";
@ -602,15 +614,10 @@ &mdss0_dp2 {
data-lanes = <0 1 2 3>;
status = "okay";
};
ports {
port@1 {
reg = <1>;
mdss0_dp2_phy_out: endpoint {
remote-endpoint = <&dp1_connector_in>;
};
};
};
&mdss0_dp2_out {
remote-endpoint = <&dp1_connector_in>;
};
&mdss0_dp2_phy {

426
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
View File

@ -10,6 +10,7 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sc8280xp-camcc.h>
#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sc8280xp.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@ -912,6 +913,32 @@ gpu_speed_bin: gpu-speed-bin@18b {
};
};
gpi_dma2: dma-controller@800000 {
compatible = "qcom,sc8280xp-gpi-dma", "qcom,sm6350-gpi-dma";
reg = <0 0x00800000 0 0x60000>;
interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <12>;
dma-channel-mask = <0xfff>;
#dma-cells = <3>;
iommus = <&apps_smmu 0xb6 0x0>;
status = "disabled";
};
qup2: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0 0x008c0000 0 0x2000>;
@ -939,6 +966,12 @@ i2c16: i2c@880000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
<&gpi_dma2 1 6 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -955,6 +988,12 @@ spi16: spi@880000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
<&gpi_dma2 1 0 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -971,6 +1010,12 @@ i2c17: i2c@884000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
<&gpi_dma2 1 0 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -987,6 +1032,12 @@ spi17: spi@884000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
<&gpi_dma2 1 1 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1017,6 +1068,12 @@ i2c18: i2c@888000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
<&gpi_dma2 1 1 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1033,6 +1090,12 @@ spi18: spi@888000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
<&gpi_dma2 1 2 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1067,6 +1130,12 @@ i2c19: i2c@88c000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
<&gpi_dma2 1 2 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1083,6 +1152,12 @@ spi19: spi@88c000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
<&gpi_dma2 1 3 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1099,6 +1174,12 @@ i2c20: i2c@890000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
<&gpi_dma2 1 3 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1115,6 +1196,12 @@ spi20: spi@890000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
<&gpi_dma2 1 4 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1131,6 +1218,12 @@ i2c21: i2c@894000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
<&gpi_dma2 1 5 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1147,6 +1240,12 @@ spi21: spi@894000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
<&gpi_dma2 1 4 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1163,6 +1262,12 @@ i2c22: i2c@898000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
<&gpi_dma2 1 6 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1179,6 +1284,12 @@ spi22: spi@898000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
<&gpi_dma2 1 5 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1195,6 +1306,12 @@ i2c23: i2c@89c000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
<&gpi_dma2 1 7 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1211,10 +1328,43 @@ spi23: spi@89c000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
<&gpi_dma2 1 7 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
status = "disabled";
};
};
gpi_dma0: dma-controller@900000 {
compatible = "qcom,sc8280xp-gpi-dma", "qcom,sm6350-gpi-dma";
reg = <0 0x00900000 0 0x60000>;
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <13>;
dma-channel-mask = <0x1fff>;
#dma-cells = <3>;
iommus = <&apps_smmu 0x576 0x0>;
status = "disabled";
};
qup0: geniqup@9c0000 {
compatible = "qcom,geni-se-qup";
reg = <0 0x009c0000 0 0x6000>;
@ -1242,6 +1392,12 @@ i2c0: i2c@980000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
<&gpi_dma0 1 7 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1258,6 +1414,12 @@ spi0: spi@980000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
<&gpi_dma0 1 0 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1274,6 +1436,12 @@ i2c1: i2c@984000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
<&gpi_dma0 1 0 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1290,6 +1458,12 @@ spi1: spi@984000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
<&gpi_dma0 1 1 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1306,6 +1480,12 @@ i2c2: i2c@988000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
<&gpi_dma0 1 1 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1322,6 +1502,12 @@ spi2: spi@988000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
<&gpi_dma0 1 2 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1352,6 +1538,12 @@ i2c3: i2c@98c000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
<&gpi_dma0 1 2 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1368,6 +1560,12 @@ spi3: spi@98c000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
<&gpi_dma0 1 3 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1384,6 +1582,12 @@ i2c4: i2c@990000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
<&gpi_dma0 1 3 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1400,6 +1604,12 @@ spi4: spi@990000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
<&gpi_dma0 1 4 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1416,6 +1626,12 @@ i2c5: i2c@994000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
<&gpi_dma0 1 4 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1432,6 +1648,12 @@ spi5: spi@994000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
<&gpi_dma0 1 5 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1448,6 +1670,12 @@ i2c6: i2c@998000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
<&gpi_dma0 1 5 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1464,6 +1692,12 @@ spi6: spi@998000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
<&gpi_dma0 1 6 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1480,6 +1714,12 @@ i2c7: i2c@99c000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
<&gpi_dma0 1 6 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1496,10 +1736,42 @@ spi7: spi@99c000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
<&gpi_dma0 1 7 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
status = "disabled";
};
};
gpi_dma1: dma-controller@a00000 {
compatible = "qcom,sc8280xp-gpi-dma", "qcom,sm6350-gpi-dma";
reg = <0 0x00a00000 0 0x60000>;
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <12>;
dma-channel-mask = <0xfff>;
#dma-cells = <3>;
iommus = <&apps_smmu 0x96 0x0>;
status = "disabled";
};
qup1: geniqup@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0 0x00ac0000 0 0x6000>;
@ -1527,6 +1799,12 @@ i2c8: i2c@a80000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
<&gpi_dma1 1 7 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1543,6 +1821,12 @@ spi8: spi@a80000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
<&gpi_dma1 1 0 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1559,6 +1843,12 @@ i2c9: i2c@a84000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
<&gpi_dma1 1 0 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1575,6 +1865,12 @@ spi9: spi@a84000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
<&gpi_dma1 1 1 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1591,6 +1887,12 @@ i2c10: i2c@a88000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
<&gpi_dma1 1 1 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1607,6 +1909,12 @@ spi10: spi@a88000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
<&gpi_dma1 1 2 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1623,6 +1931,12 @@ i2c11: i2c@a8c000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
<&gpi_dma1 1 2 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1639,6 +1953,12 @@ spi11: spi@a8c000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
<&gpi_dma1 1 3 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1655,6 +1975,12 @@ i2c12: i2c@a90000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
<&gpi_dma1 1 3 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1671,6 +1997,12 @@ spi12: spi@a90000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
<&gpi_dma1 1 4 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1687,6 +2019,12 @@ i2c13: i2c@a94000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
<&gpi_dma1 1 4 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1703,6 +2041,12 @@ spi13: spi@a94000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
<&gpi_dma1 1 5 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1719,6 +2063,12 @@ i2c14: i2c@a98000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
<&gpi_dma1 1 5 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1735,6 +2085,12 @@ spi14: spi@a98000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
<&gpi_dma1 1 6 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1751,6 +2107,12 @@ i2c15: i2c@a9c000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
<&gpi_dma1 1 6 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
status = "disabled";
};
@ -1767,6 +2129,12 @@ spi15: spi@a9c000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
<&gpi_dma1 1 7 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
status = "disabled";
};
};
@ -1809,10 +2177,10 @@ pcie4: pcie@1c00000 {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 GIC_SPI GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 GIC_SPI GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 GIC_SPI GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
<&gcc GCC_PCIE_4_CFG_AHB_CLK>,
@ -1922,10 +2290,10 @@ pcie3b: pcie@1c08000 {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 GIC_SPI GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 GIC_SPI GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 GIC_SPI GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
<&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
@ -2033,10 +2401,10 @@ pcie3a: pcie@1c10000 {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 GIC_SPI GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 GIC_SPI GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 GIC_SPI GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
<&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
@ -2147,10 +2515,10 @@ pcie2b: pcie@1c18000 {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 GIC_SPI GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 GIC_SPI GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 GIC_SPI GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
<&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
@ -2258,10 +2626,10 @@ pcie2a: pcie@1c20000 {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 GIC_SPI GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 GIC_SPI GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 GIC_SPI GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
<&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
@ -4526,6 +4894,9 @@ mdss0_dp2_in: endpoint {
port@1 {
reg = <1>;
mdss0_dp2_out: endpoint {
};
};
};
@ -4598,6 +4969,9 @@ mdss0_dp3_in: endpoint {
port@1 {
reg = <1>;
mdss0_dp3_out: endpoint {
};
};
};
@ -5701,6 +6075,9 @@ mdss1_dp0_in: endpoint {
port@1 {
reg = <1>;
mdss1_dp0_out: endpoint {
};
};
};
@ -5773,6 +6150,9 @@ mdss1_dp1_in: endpoint {
port@1 {
reg = <1>;
mdss1_dp1_out: endpoint {
};
};
};
@ -5845,6 +6225,9 @@ mdss1_dp2_in: endpoint {
port@1 {
reg = <1>;
mdss1_dp2_out: endpoint {
};
};
};
@ -5917,6 +6300,9 @@ mdss1_dp3_in: endpoint {
port@1 {
reg = <1>;
mdss1_dp3_out: endpoint {
};
};
};

62
arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts
View File

@ -36,6 +36,14 @@ key-volume-up {
};
};
/* Dummy regulator until PMI632 has LCDB VSP/VSN support */
lcdb_dummy: regulator-lcdb-dummy {
compatible = "regulator-fixed";
regulator-name = "lcdb_dummy";
regulator-min-microvolt = <5500000>;
regulator-max-microvolt = <5500000>;
};
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
@ -44,6 +52,14 @@ vph_pwr: vph-pwr-regulator {
};
};
&gpu {
status = "okay";
};
&gpu_zap_shader {
firmware-name = "qcom/msm8953/fairphone/fp3/a506_zap.mbn";
};
&hsusb_phy {
vdd-supply = <&pm8953_l3>;
vdda-pll-supply = <&pm8953_l7>;
@ -87,6 +103,45 @@ &lpass {
status = "okay";
};
&mdss {
status = "okay";
};
&mdss_dsi0 {
vdda-supply = <&pm8953_s3>;
status = "okay";
panel@0 {
compatible = "djn,98-03057-6598b-i";
reg = <0>;
reset-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
iovcc-supply = <&pm8953_l6>;
vsn-supply = <&lcdb_dummy>;
vsp-supply = <&lcdb_dummy>;
pinctrl-0 = <&mdss_te_default>;
pinctrl-names = "default";
port {
panel_in: endpoint {
remote-endpoint = <&mdss_dsi0_out>;
};
};
};
};
&mdss_dsi0_out {
data-lanes = <0 1 2 3>;
remote-endpoint = <&panel_in>;
};
&mdss_dsi0_phy {
vcca-supply = <&pm8953_l3>;
status = "okay";
};
&mpss {
firmware-name = "qcom/msm8953/fairphone/fp3/mba.mbn",
"qcom/msm8953/fairphone/fp3/modem.mbn";
@ -292,6 +347,13 @@ &tlmm {
* 135-138: fingerprint reader (SPI)
*/
gpio-reserved-ranges = <0 4>, <135 4>;
mdss_te_default: mdss-te-default-state {
pins = "gpio24";
function = "mdp_vsync";
drive-strength = <2>;
bias-pull-down;
};
};
&uart_0 {

17
arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts
View File

@ -33,6 +33,14 @@ / {
aliases { };
battery: battery {
compatible = "simple-battery";
voltage-min-design-microvolt = <3312000>;
voltage-max-design-microvolt = <4400000>;
charge-full-design-microamp-hours = <3000000>;
};
chosen {
stdout-path = "serial0:115200n8";
@ -478,6 +486,15 @@ &mdss_mdp {
status = "okay";
};
&pm660_charger {
monitored-battery = <&battery>;
status = "okay";
};
&pm660_rradc {
status = "okay";
};
&pm660l_flash {
status = "okay";

238
arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dts
View File

@ -1,238 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Cheza board device tree source
*
* Copyright 2018 Google LLC.
*/
/dts-v1/;
#include "sdm845-cheza.dtsi"
/ {
model = "Google Cheza (rev1)";
compatible = "google,cheza-rev1", "qcom,sdm845";
/*
* FIXED REGULATORS (not in sdm845-cheza.dtsi) - parents above children
*/
/*
* NOTE: Technically pp3500_a is not the exact same signal as
* pp3500_a_vbob (there's a load switch between them and the EC can
* control pp3500_a via "en_pp3300_a"), but from the AP's point of
* view they are the same.
*/
pp3500_a:
pp3500_a_vbob: pp3500-a-vbob-regulator {
compatible = "regulator-fixed";
regulator-name = "vreg_bob";
/*
* Comes on automatically when pp5000_ldo comes on, which
* comes on automatically when ppvar_sys comes on
*/
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3500000>;
regulator-max-microvolt = <3500000>;
vin-supply = <&ppvar_sys>;
};
pp3300_dx_edp: pp3300-dx-edp-regulator {
/* Yes, it's really 3.5 despite the name of the signal */
regulator-min-microvolt = <3500000>;
regulator-max-microvolt = <3500000>;
vin-supply = <&pp3500_a>;
};
};
/* FIXED REGULATOR OVERRIDES (modifications to sdm845-cheza.dtsi) */
/*
* L19 and L28 technically go to 3.3V, but most boards have old AOP firmware
* that limits them to 3.0, and trying to run at 3.3V with that old firmware
* prevents the system from booting.
*/
&src_pp3000_l19a {
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3008000>;
};
&src_pp3300_l22a {
/delete-property/regulator-boot-on;
/delete-property/regulator-always-on;
};
&src_pp3300_l28a {
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3008000>;
};
&src_vreg_bob {
regulator-min-microvolt = <3500000>;
regulator-max-microvolt = <3500000>;
vin-supply = <&pp3500_a_vbob>;
};
/*
* NON-REGULATOR OVERRIDES
* (modifications to sdm845-cheza.dtsi) - alphabetized by dtsi label
*/
/* PINCTRL - board-specific pinctrl */
&tlmm {
gpio-line-names = "AP_SPI_FP_MISO",
"AP_SPI_FP_MOSI",
"AP_SPI_FP_CLK",
"AP_SPI_FP_CS_L",
"UART_AP_TX_DBG_RX",
"UART_DBG_TX_AP_RX",
"",
"FP_RST_L",
"FCAM_EN",
"",
"EDP_BRIJ_IRQ",
"EC_IN_RW_ODL",
"",
"RCAM_MCLK",
"FCAM_MCLK",
"",
"RCAM_EN",
"CCI0_SDA",
"CCI0_SCL",
"CCI1_SDA",
"CCI1_SCL",
"FCAM_RST_L",
"",
"PEN_RST_L",
"PEN_IRQ_L",
"",
"RCAM_VSYNC",
"ESIM_MISO",
"ESIM_MOSI",
"ESIM_CLK",
"ESIM_CS_L",
"AP_PEN_1V8_SDA",
"AP_PEN_1V8_SCL",
"AP_TS_I2C_SDA",
"AP_TS_I2C_SCL",
"RCAM_RST_L",
"",
"AP_EDP_BKLTEN",
"AP_BRD_ID1",
"BOOT_CONFIG_4",
"AMP_IRQ_L",
"EDP_BRIJ_I2C_SDA",
"EDP_BRIJ_I2C_SCL",
"EN_PP3300_DX_EDP",
"SD_CD_ODL",
"BT_UART_RTS",
"BT_UART_CTS",
"BT_UART_RXD",
"BT_UART_TXD",
"AMP_I2C_SDA",
"AMP_I2C_SCL",
"AP_BRD_ID3",
"",
"AP_EC_SPI_CLK",
"AP_EC_SPI_CS_L",
"AP_EC_SPI_MISO",
"AP_EC_SPI_MOSI",
"FORCED_USB_BOOT",
"AMP_BCLK",
"AMP_LRCLK",
"AMP_DOUT",
"AMP_DIN",
"AP_BRD_ID2",
"PEN_PDCT_L",
"HP_MCLK",
"HP_BCLK",
"HP_LRCLK",
"HP_DOUT",
"HP_DIN",
"",
"",
"",
"",
"BT_SLIMBUS_DATA",
"BT_SLIMBUS_CLK",
"AMP_RESET_L",
"",
"FCAM_VSYNC",
"",
"AP_SKU_ID1",
"EC_WOV_BCLK",
"EC_WOV_LRCLK",
"EC_WOV_DOUT",
"",
"",
"AP_H1_SPI_MISO",
"AP_H1_SPI_MOSI",
"AP_H1_SPI_CLK",
"AP_H1_SPI_CS_L",
"",
"AP_SPI_CS0_L",
"AP_SPI_MOSI",
"AP_SPI_MISO",
"",
"",
"AP_SPI_CLK",
"",
"RFFE6_CLK",
"RFFE6_DATA",
"BOOT_CONFIG_1",
"BOOT_CONFIG_2",
"BOOT_CONFIG_0",
"EDP_BRIJ_EN",
"",
"USB_HS_TX_EN",
"UIM2_DATA",
"UIM2_CLK",
"UIM2_RST",
"UIM2_PRESENT",
"UIM1_DATA",
"UIM1_CLK",
"UIM1_RST",
"",
"AP_SKU_ID2",
"SDM_GRFC_8",
"SDM_GRFC_9",
"AP_RST_REQ",
"HP_IRQ",
"TS_RESET_L",
"PEN_EJECT_ODL",
"HUB_RST_L",
"FP_TO_AP_IRQ",
"AP_EC_INT_L",
"",
"",
"TS_INT_L",
"AP_SUSPEND_L",
"SDM_GRFC_3",
"",
"H1_AP_INT_ODL",
"QLINK_REQ",
"QLINK_EN",
"SDM_GRFC_2",
"BOOT_CONFIG_3",
"WMSS_RESET_L",
"SDM_GRFC_0",
"SDM_GRFC_1",
"RFFE3_DATA",
"RFFE3_CLK",
"RFFE4_DATA",
"RFFE4_CLK",
"RFFE5_DATA",
"RFFE5_CLK",
"GNSS_EN",
"WCI2_LTE_COEX_RXD",
"WCI2_LTE_COEX_TXD",
"AP_RAM_ID1",
"AP_RAM_ID2",
"RFFE1_DATA",
"RFFE1_CLK";
};

238
arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dts
View File

@ -1,238 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Cheza board device tree source
*
* Copyright 2018 Google LLC.
*/
/dts-v1/;
#include "sdm845-cheza.dtsi"
/ {
model = "Google Cheza (rev2)";
compatible = "google,cheza-rev2", "qcom,sdm845";
/*
* FIXED REGULATORS (not in sdm845-cheza.dtsi) - parents above children
*/
/*
* NOTE: Technically pp3500_a is not the exact same signal as
* pp3500_a_vbob (there's a load switch between them and the EC can
* control pp3500_a via "en_pp3300_a"), but from the AP's point of
* view they are the same.
*/
pp3500_a:
pp3500_a_vbob: pp3500-a-vbob-regulator {
compatible = "regulator-fixed";
regulator-name = "vreg_bob";
/*
* Comes on automatically when pp5000_ldo comes on, which
* comes on automatically when ppvar_sys comes on
*/
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3500000>;
regulator-max-microvolt = <3500000>;
vin-supply = <&ppvar_sys>;
};
pp3300_dx_edp: pp3300-dx-edp-regulator {
/* Yes, it's really 3.5 despite the name of the signal */
regulator-min-microvolt = <3500000>;
regulator-max-microvolt = <3500000>;
vin-supply = <&pp3500_a>;
};
};
/* FIXED REGULATOR OVERRIDES (modifications to sdm845-cheza.dtsi) */
/*
* L19 and L28 technically go to 3.3V, but most boards have old AOP firmware
* that limits them to 3.0, and trying to run at 3.3V with that old firmware
* prevents the system from booting.
*/
&src_pp3000_l19a {
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3008000>;
};
&src_pp3300_l22a {
/delete-property/regulator-boot-on;
/delete-property/regulator-always-on;
};
&src_pp3300_l28a {
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3008000>;
};
&src_vreg_bob {
regulator-min-microvolt = <3500000>;
regulator-max-microvolt = <3500000>;
vin-supply = <&pp3500_a_vbob>;
};
/*
* NON-REGULATOR OVERRIDES
* (modifications to sdm845-cheza.dtsi) - alphabetized by dtsi label
*/
/* PINCTRL - board-specific pinctrl */
&tlmm {
gpio-line-names = "AP_SPI_FP_MISO",
"AP_SPI_FP_MOSI",
"AP_SPI_FP_CLK",
"AP_SPI_FP_CS_L",
"UART_AP_TX_DBG_RX",
"UART_DBG_TX_AP_RX",
"BRIJ_SUSPEND",
"FP_RST_L",
"FCAM_EN",
"",
"EDP_BRIJ_IRQ",
"EC_IN_RW_ODL",
"",
"RCAM_MCLK",
"FCAM_MCLK",
"",
"RCAM_EN",
"CCI0_SDA",
"CCI0_SCL",
"CCI1_SDA",
"CCI1_SCL",
"FCAM_RST_L",
"FPMCU_BOOT0",
"PEN_RST_L",
"PEN_IRQ_L",
"FPMCU_SEL_OD",
"RCAM_VSYNC",
"ESIM_MISO",
"ESIM_MOSI",
"ESIM_CLK",
"ESIM_CS_L",
"AP_PEN_1V8_SDA",
"AP_PEN_1V8_SCL",
"AP_TS_I2C_SDA",
"AP_TS_I2C_SCL",
"RCAM_RST_L",
"",
"AP_EDP_BKLTEN",
"AP_BRD_ID1",
"BOOT_CONFIG_4",
"AMP_IRQ_L",
"EDP_BRIJ_I2C_SDA",
"EDP_BRIJ_I2C_SCL",
"EN_PP3300_DX_EDP",
"SD_CD_ODL",
"BT_UART_RTS",
"BT_UART_CTS",
"BT_UART_RXD",
"BT_UART_TXD",
"AMP_I2C_SDA",
"AMP_I2C_SCL",
"AP_BRD_ID3",
"",
"AP_EC_SPI_CLK",
"AP_EC_SPI_CS_L",
"AP_EC_SPI_MISO",
"AP_EC_SPI_MOSI",
"FORCED_USB_BOOT",
"AMP_BCLK",
"AMP_LRCLK",
"AMP_DOUT",
"AMP_DIN",
"AP_BRD_ID2",
"PEN_PDCT_L",
"HP_MCLK",
"HP_BCLK",
"HP_LRCLK",
"HP_DOUT",
"HP_DIN",
"",
"",
"",
"",
"BT_SLIMBUS_DATA",
"BT_SLIMBUS_CLK",
"AMP_RESET_L",
"",
"FCAM_VSYNC",
"",
"AP_SKU_ID1",
"EC_WOV_BCLK",
"EC_WOV_LRCLK",
"EC_WOV_DOUT",
"",
"",
"AP_H1_SPI_MISO",
"AP_H1_SPI_MOSI",
"AP_H1_SPI_CLK",
"AP_H1_SPI_CS_L",
"",
"AP_SPI_CS0_L",
"AP_SPI_MOSI",
"AP_SPI_MISO",
"",
"",
"AP_SPI_CLK",
"",
"RFFE6_CLK",
"RFFE6_DATA",
"BOOT_CONFIG_1",
"BOOT_CONFIG_2",
"BOOT_CONFIG_0",
"EDP_BRIJ_EN",
"",
"USB_HS_TX_EN",
"UIM2_DATA",
"UIM2_CLK",
"UIM2_RST",
"UIM2_PRESENT",
"UIM1_DATA",
"UIM1_CLK",
"UIM1_RST",
"",
"AP_SKU_ID2",
"SDM_GRFC_8",
"SDM_GRFC_9",
"AP_RST_REQ",
"HP_IRQ",
"TS_RESET_L",
"PEN_EJECT_ODL",
"HUB_RST_L",
"FP_TO_AP_IRQ",
"AP_EC_INT_L",
"",
"",
"TS_INT_L",
"AP_SUSPEND_L",
"SDM_GRFC_3",
"",
"H1_AP_INT_ODL",
"QLINK_REQ",
"QLINK_EN",
"SDM_GRFC_2",
"BOOT_CONFIG_3",
"WMSS_RESET_L",
"SDM_GRFC_0",
"SDM_GRFC_1",
"RFFE3_DATA",
"RFFE3_CLK",
"RFFE4_DATA",
"RFFE4_CLK",
"RFFE5_DATA",
"RFFE5_CLK",
"GNSS_EN",
"WCI2_LTE_COEX_RXD",
"WCI2_LTE_COEX_TXD",
"AP_RAM_ID1",
"AP_RAM_ID2",
"RFFE1_DATA",
"RFFE1_CLK";
};

174
arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dts
View File

@ -1,174 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Cheza board device tree source
*
* Copyright 2018 Google LLC.
*/
/dts-v1/;
#include "sdm845-cheza.dtsi"
/ {
model = "Google Cheza (rev3+)";
compatible = "google,cheza", "qcom,sdm845";
};
/* PINCTRL - board-specific pinctrl */
&tlmm {
gpio-line-names = "AP_SPI_FP_MISO",
"AP_SPI_FP_MOSI",
"AP_SPI_FP_CLK",
"AP_SPI_FP_CS_L",
"UART_AP_TX_DBG_RX",
"UART_DBG_TX_AP_RX",
"BRIJ_SUSPEND",
"FP_RST_L",
"FCAM_EN",
"",
"EDP_BRIJ_IRQ",
"EC_IN_RW_ODL",
"",
"RCAM_MCLK",
"FCAM_MCLK",
"",
"RCAM_EN",
"CCI0_SDA",
"CCI0_SCL",
"CCI1_SDA",
"CCI1_SCL",
"FCAM_RST_L",
"FPMCU_BOOT0",
"PEN_RST_L",
"PEN_IRQ_L",
"FPMCU_SEL_OD",
"RCAM_VSYNC",
"ESIM_MISO",
"ESIM_MOSI",
"ESIM_CLK",
"ESIM_CS_L",
"AP_PEN_1V8_SDA",
"AP_PEN_1V8_SCL",
"AP_TS_I2C_SDA",
"AP_TS_I2C_SCL",
"RCAM_RST_L",
"",
"AP_EDP_BKLTEN",
"AP_BRD_ID0",
"BOOT_CONFIG_4",
"AMP_IRQ_L",
"EDP_BRIJ_I2C_SDA",
"EDP_BRIJ_I2C_SCL",
"EN_PP3300_DX_EDP",
"SD_CD_ODL",
"BT_UART_RTS",
"BT_UART_CTS",
"BT_UART_RXD",
"BT_UART_TXD",
"AMP_I2C_SDA",
"AMP_I2C_SCL",
"AP_BRD_ID2",
"",
"AP_EC_SPI_CLK",
"AP_EC_SPI_CS_L",
"AP_EC_SPI_MISO",
"AP_EC_SPI_MOSI",
"FORCED_USB_BOOT",
"AMP_BCLK",
"AMP_LRCLK",
"AMP_DOUT",
"AMP_DIN",
"AP_BRD_ID1",
"PEN_PDCT_L",
"HP_MCLK",
"HP_BCLK",
"HP_LRCLK",
"HP_DOUT",
"HP_DIN",
"",
"",
"",
"",
"BT_SLIMBUS_DATA",
"BT_SLIMBUS_CLK",
"AMP_RESET_L",
"",
"FCAM_VSYNC",
"",
"AP_SKU_ID0",
"EC_WOV_BCLK",
"EC_WOV_LRCLK",
"EC_WOV_DOUT",
"",
"",
"AP_H1_SPI_MISO",
"AP_H1_SPI_MOSI",
"AP_H1_SPI_CLK",
"AP_H1_SPI_CS_L",
"",
"AP_SPI_CS0_L",
"AP_SPI_MOSI",
"AP_SPI_MISO",
"",
"",
"AP_SPI_CLK",
"",
"RFFE6_CLK",
"RFFE6_DATA",
"BOOT_CONFIG_1",
"BOOT_CONFIG_2",
"BOOT_CONFIG_0",
"EDP_BRIJ_EN",
"",
"USB_HS_TX_EN",
"UIM2_DATA",
"UIM2_CLK",
"UIM2_RST",
"UIM2_PRESENT",
"UIM1_DATA",
"UIM1_CLK",
"UIM1_RST",
"",
"AP_SKU_ID1",
"SDM_GRFC_8",
"SDM_GRFC_9",
"AP_RST_REQ",
"HP_IRQ",
"TS_RESET_L",
"PEN_EJECT_ODL",
"HUB_RST_L",
"FP_TO_AP_IRQ",
"AP_EC_INT_L",
"",
"",
"TS_INT_L",
"AP_SUSPEND_L",
"SDM_GRFC_3",
/*
* AP_FLASH_WP_L is crossystem ABI. Rev3 schematics
* call it BIOS_FLASH_WP_R_L.
*/
"AP_FLASH_WP_L",
"H1_AP_INT_ODL",
"QLINK_REQ",
"QLINK_EN",
"SDM_GRFC_2",
"BOOT_CONFIG_3",
"WMSS_RESET_L",
"SDM_GRFC_0",
"SDM_GRFC_1",
"RFFE3_DATA",
"RFFE3_CLK",
"RFFE4_DATA",
"RFFE4_CLK",
"RFFE5_DATA",
"RFFE5_CLK",
"GNSS_EN",
"WCI2_LTE_COEX_RXD",
"WCI2_LTE_COEX_TXD",
"AP_RAM_ID0",
"AP_RAM_ID1",
"RFFE1_DATA",
"RFFE1_CLK";
};

1330
arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
View File

File diff suppressed because it is too large Load Diff

3
arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso
View File

@ -44,7 +44,8 @@ camera@10 {
clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
clock-names = "xvclk";
clock-frequency = <19200000>;
assigned-clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
assigned-clock-rates = <19200000>;
/*
* The &vreg_s4a_1p8 trace is powered on as a,

27
arch/arm64/boot/dts/qcom/sdm845-db845c.dts
View File

@ -5,6 +5,7 @@
/dts-v1/;
#include <dt-bindings/arm/qcom,ids.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
@ -18,7 +19,7 @@
/ {
model = "Thundercomm Dragonboard 845c";
compatible = "thundercomm,db845c", "qcom,sdm845";
qcom,msm-id = <341 0x20001>;
qcom,msm-id = <QCOM_ID_SDA845 0x20001>;
qcom,board-id = <8 0>;
aliases {
@ -533,15 +534,11 @@ &mdss_dsi0 {
qcom,dual-dsi-mode;
qcom,master-dsi;
};
ports {
port@1 {
endpoint {
remote-endpoint = <&lt9611_a>;
data-lanes = <0 1 2 3>;
};
};
};
&mdss_dsi0_out {
remote-endpoint = <&lt9611_a>;
data-lanes = <0 1 2 3>;
};
&mdss_dsi0_phy {
@ -559,15 +556,11 @@ &mdss_dsi1 {
<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
status = "okay";
};
ports {
port@1 {
endpoint {
remote-endpoint = <&lt9611_b>;
data-lanes = <0 1 2 3>;
};
};
};
&mdss_dsi1_out {
remote-endpoint = <&lt9611_b>;
data-lanes = <0 1 2 3>;
};
&mdss_dsi1_phy {

26
arch/arm64/boot/dts/qcom/sdm845-mtp.dts
View File

@ -445,15 +445,6 @@ &mdss_dsi0 {
qcom,dual-dsi-mode;
qcom,master-dsi;
ports {
port@1 {
endpoint {
remote-endpoint = <&truly_in_0>;
data-lanes = <0 1 2 3>;
};
};
};
panel@0 {
compatible = "truly,nt35597-2K-display";
reg = <0>;
@ -483,6 +474,11 @@ truly_in_1: endpoint {
};
};
&mdss_dsi0_out {
remote-endpoint = <&truly_in_0>;
data-lanes = <0 1 2 3>;
};
&mdss_dsi0_phy {
status = "okay";
vdds-supply = <&vdda_mipi_dsi0_pll>;
@ -497,15 +493,11 @@ &mdss_dsi1 {
/* DSI1 is slave, so use DSI0 clocks */
assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
};
ports {
port@1 {
endpoint {
remote-endpoint = <&truly_in_1>;
data-lanes = <0 1 2 3>;
};
};
};
&mdss_dsi1_out {
remote-endpoint = <&truly_in_1>;
data-lanes = <0 1 2 3>;
};
&mdss_dsi1_phy {

4
arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi
View File

@ -7,6 +7,7 @@
/dts-v1/;
#include <dt-bindings/arm/qcom,ids.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
@ -21,6 +22,9 @@
/delete-node/ &rmtfs_mem;
/ {
chassis-type = "handset";
qcom,msm-id = <QCOM_ID_SDM845 0x20001>;
aliases {
serial0 = &uart9;
serial1 = &uart6;

10
arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts
View File

@ -10,8 +10,6 @@
/ {
model = "OnePlus 6";
compatible = "oneplus,enchilada", "qcom,sdm845";
chassis-type = "handset";
qcom,msm-id = <0x141 0x20001>;
qcom,board-id = <8 0 17819 22>;
battery: battery {
@ -20,6 +18,14 @@ battery: battery {
charge-full-design-microamp-hours = <3300000>;
voltage-min-design-microvolt = <3400000>;
voltage-max-design-microvolt = <4400000>;
/*
* Typical designs have multiple charger ICs which can handle more
* current but the OnePlus 6/T do not, hence the lower limit. This
* does not apply when using the Dash Charger, however this is not
* yet supported.
*/
constant-charge-current-max-microamp = <1800000>;
};
};

10
arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts
View File

@ -10,8 +10,6 @@
/ {
model = "OnePlus 6T";
compatible = "oneplus,fajita", "qcom,sdm845";
chassis-type = "handset";
qcom,msm-id = <0x141 0x20001>;
qcom,board-id = <8 0 18801 41>;
battery: battery {
@ -20,6 +18,14 @@ battery: battery {
charge-full-design-microamp-hours = <3700000>;
voltage-min-design-microvolt = <3400000>;
voltage-max-design-microvolt = <4400000>;
/*
* Typical designs have multiple charger ICs which can handle more
* current but the OnePlus 6/T do not, hence the lower limit. This
* does not apply when using the Dash Charger, however this is not
* yet supported.
*/
constant-charge-current-max-microamp = <1800000>;
};
};

7
arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts
View File

@ -145,8 +145,8 @@ rmtfs_mem: rmtfs-mem@fde00000 {
i2c21 {
compatible = "i2c-gpio";
sda-gpios = <&tlmm 127 GPIO_ACTIVE_HIGH>;
scl-gpios = <&tlmm 128 GPIO_ACTIVE_HIGH>;
sda-gpios = <&tlmm 127 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&tlmm 128 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <2>;
pinctrl-0 = <&i2c21_sda_state &i2c21_scl_state>;
pinctrl-names = "default";
@ -633,7 +633,6 @@ max77705_charger: charger@69 {
monitored-battery = <&battery>;
interrupt-parent = <&pm8998_gpios>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
};
fuel-gauge@36 {
@ -701,7 +700,7 @@ &sound {
pinctrl-names = "default";
status = "okay";
audio-routing = "RX_BIAS", "MCLK",
audio-routing = "RX_BIAS", "MCLK",
"AMIC2", "MIC BIAS2", /* Headset Mic */
"AMIC3", "MIC BIAS2", /* FM radio left Tx */
"AMIC4", "MIC BIAS2", /* FM radio right Tx */

4
arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts
View File

@ -7,6 +7,7 @@
/dts-v1/;
#include <dt-bindings/arm/qcom,ids.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
@ -17,7 +18,8 @@
/ {
model = "SHIFT SHIFT6mq";
compatible = "shift,axolotl", "qcom,sdm845";
qcom,msm-id = <321 0x20001>;
chassis-type = "handset";
qcom,msm-id = <QCOM_ID_SDM845 0x20001>;
qcom,board-id = <11 0>;
aliases {

3
arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi
View File

@ -3,6 +3,7 @@
* Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
*/
#include <dt-bindings/arm/qcom,ids.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
@ -12,7 +13,7 @@
#include "pmi8998.dtsi"
/ {
qcom,msm-id = <321 0x20001>; /* SDM845 v2.1 */
qcom,msm-id = <QCOM_ID_SDM845 0x20001>; /* SDM845 v2.1 */
qcom,board-id = <8 0>;
aliases {

3
arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi
View File

@ -2,6 +2,7 @@
/dts-v1/;
#include <dt-bindings/arm/qcom,ids.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
@ -32,7 +33,7 @@ / {
/* required for bootloader to select correct board */
qcom,board-id = <69 0>;
qcom,msm-id = <321 0x20001>;
qcom,msm-id = <QCOM_ID_SDM845 0x20001>;
aliases {
serial1 = &uart6;

3
arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts
View File

@ -6,6 +6,7 @@
/dts-v1/;
#include <dt-bindings/arm/qcom,ids.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
@ -38,7 +39,7 @@ / {
chassis-type = "handset";
/* required for bootloader to select correct board */
qcom,msm-id = <0x141 0x20001>;
qcom,msm-id = <QCOM_ID_SDM845 0x20001>;
qcom,board-id = <0x2a 0x0>;
aliases {

36
arch/arm64/boot/dts/qcom/sdm845.dtsi
View File

@ -2347,10 +2347,10 @@ pcie0: pcie@1c00000 {
"global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
<&gcc GCC_PCIE_0_AUX_CLK>,
@ -2472,10 +2472,10 @@ pcie1: pcie@1c08000 {
"global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
<&gcc GCC_PCIE_1_AUX_CLK>,
@ -4089,7 +4089,7 @@ port@2 {
reg = <2>;
usb_1_qmpphy_dp_in: endpoint {
remote-endpoint = <&dp_out>;
remote-endpoint = <&mdss_dp_out>;
};
};
};
@ -4286,14 +4286,6 @@ venus: video-codec@aa00000 {
status = "disabled";
video-core0 {
compatible = "venus-decoder";
};
video-core1 {
compatible = "venus-encoder";
};
venus_opp_table: opp-table {
compatible = "operating-points-v2";
@ -4603,7 +4595,7 @@ ports {
port@0 {
reg = <0>;
dpu_intf0_out: endpoint {
remote-endpoint = <&dp_in>;
remote-endpoint = <&mdss_dp_in>;
};
};
@ -4682,14 +4674,14 @@ ports {
#size-cells = <0>;
port@0 {
reg = <0>;
dp_in: endpoint {
mdss_dp_in: endpoint {
remote-endpoint = <&dpu_intf0_out>;
};
};
port@1 {
reg = <1>;
dp_out: endpoint {
mdss_dp_out: endpoint {
remote-endpoint = <&usb_1_qmpphy_dp_in>;
};
};
@ -5404,11 +5396,11 @@ slimbam: dma-controller@17184000 {
compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
qcom,controlled-remotely;
reg = <0 0x17184000 0 0x2a000>;
num-channels = <31>;
num-channels = <23>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
qcom,ee = <1>;
qcom,num-ees = <2>;
qcom,num-ees = <4>;
iommus = <&apps_smmu 0x1806 0x0>;
};

116
arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts
View File

@ -421,9 +421,46 @@ connector@1 {
data-role = "host";
/*
* connected to the onboard USB hub, orientation is
* handled by the controller
* connected to the onboard USB hub, each pair of lanes
* (and D+/D- pair) is connected to a separate port on
* the hub.
*/
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
ucsi1_hs_in_1: endpoint@1 {
reg = <1>;
remote-endpoint = <&usb_hub_2_1>;
};
ucsi1_hs_in_2: endpoint@2 {
reg = <2>;
remote-endpoint = <&usb_hub_2_2>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
ucsi1_ss_in_1: endpoint@1 {
reg = <1>;
remote-endpoint = <&usb_hub_3_1>;
};
ucsi1_ss_in_2: endpoint@2 {
reg = <2>;
remote-endpoint = <&usb_hub_3_2>;
};
};
};
};
};
};
@ -561,15 +598,11 @@ &mdss {
&mdss_dsi0 {
status = "okay";
vdda-supply = <&vreg_l26a_1p2>;
};
ports {
port@1 {
endpoint {
remote-endpoint = <&sn65dsi86_in_a>;
data-lanes = <0 1 2 3>;
};
};
};
&mdss_dsi0_out {
remote-endpoint = <&sn65dsi86_in_a>;
data-lanes = <0 1 2 3>;
};
&mdss_dsi0_phy {
@ -842,6 +875,69 @@ &usb_2 {
&usb_2_dwc3 {
dr_mode = "host";
#address-cells = <1>;
#size-cells = <0>;
usb_hub_2_x: hub@1 {
compatible = "usb5e3,610";
reg = <1>;
peer-hub = <&usb_hub_3_x>;
#address-cells = <1>;
#size-cells = <0>;
camera@3 {
compatible = "usb4f2,b61e";
reg = <3>;
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
usb_hub_2_1: endpoint {
remote-endpoint = <&ucsi1_hs_in_1>;
};
};
port@2 {
reg = <2>;
usb_hub_2_2: endpoint {
remote-endpoint = <&ucsi1_hs_in_2>;
};
};
};
};
usb_hub_3_x: hub@2 {
compatible = "usb5e3,620";
reg = <2>;
peer-hub = <&usb_hub_2_x>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
usb_hub_3_1: endpoint {
remote-endpoint = <&ucsi1_ss_in_1>;
};
};
port@2 {
reg = <2>;
usb_hub_3_2: endpoint {
remote-endpoint = <&ucsi1_ss_in_2>;
};
};
};
};
};
&usb_2_hsphy {

410
arch/arm64/boot/dts/qcom/qcs615.dtsi → arch/arm64/boot/dts/qcom/sm6150.dtsi
View File

@ -3,7 +3,11 @@
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/clock/qcom,qcs615-camcc.h>
#include <dt-bindings/clock/qcom,qcs615-dispcc.h>
#include <dt-bindings/clock/qcom,qcs615-gcc.h>
#include <dt-bindings/clock/qcom,qcs615-gpucc.h>
#include <dt-bindings/clock/qcom,qcs615-videocc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/interconnect/qcom,icc.h>
@ -32,6 +36,8 @@ cpu0: cpu@0 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&l2_0>;
clocks = <&cpufreq_hw 0>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
l2_0: l2-cache {
@ -52,6 +58,8 @@ cpu1: cpu@100 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&l2_100>;
clocks = <&cpufreq_hw 0>;
qcom,freq-domain = <&cpufreq_hw 0>;
l2_100: l2-cache {
compatible = "cache";
@ -71,6 +79,8 @@ cpu2: cpu@200 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&l2_200>;
clocks = <&cpufreq_hw 0>;
qcom,freq-domain = <&cpufreq_hw 0>;
l2_200: l2-cache {
compatible = "cache";
@ -90,6 +100,8 @@ cpu3: cpu@300 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&l2_300>;
clocks = <&cpufreq_hw 0>;
qcom,freq-domain = <&cpufreq_hw 0>;
l2_300: l2-cache {
compatible = "cache";
@ -109,6 +121,8 @@ cpu4: cpu@400 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&l2_400>;
clocks = <&cpufreq_hw 0>;
qcom,freq-domain = <&cpufreq_hw 0>;
l2_400: l2-cache {
compatible = "cache";
@ -128,6 +142,8 @@ cpu5: cpu@500 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&l2_500>;
clocks = <&cpufreq_hw 0>;
qcom,freq-domain = <&cpufreq_hw 0>;
l2_500: l2-cache {
compatible = "cache";
@ -147,6 +163,8 @@ cpu6: cpu@600 {
capacity-dmips-mhz = <1740>;
dynamic-power-coefficient = <404>;
next-level-cache = <&l2_600>;
clocks = <&cpufreq_hw 1>;
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
l2_600: l2-cache {
@ -167,6 +185,8 @@ cpu7: cpu@700 {
capacity-dmips-mhz = <1740>;
dynamic-power-coefficient = <404>;
next-level-cache = <&l2_700>;
clocks = <&cpufreq_hw 1>;
qcom,freq-domain = <&cpufreq_hw 1>;
l2_700: l2-cache {
compatible = "cache";
@ -474,6 +494,11 @@ smem_region: smem@86000000 {
hwlocks = <&tcsr_mutex 3>;
};
pil_video_mem: pil-video@93400000 {
reg = <0x0 0x93400000 0x0 0x500000>;
no-map;
};
rproc_cdsp_mem: rproc-cdsp@93b00000 {
reg = <0x0 0x93b00000 0x0 0x1e00000>;
no-map;
@ -495,6 +520,9 @@ soc: soc@0 {
gcc: clock-controller@100000 {
compatible = "qcom,qcs615-gcc";
reg = <0 0x00100000 0 0x1f0000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
#clock-cells = <1>;
#reset-cells = <1>;
@ -631,6 +659,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
interconnect-names = "qup-core",
"qup-config";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
@ -654,6 +683,7 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
"qup-config",
"qup-memory";
power-domains = <&rpmhpd RPMHPD_CX>;
required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
<&gpi_dma0 1 1 QCOM_GPI_I2C>;
dma-names = "tx",
@ -681,6 +711,7 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
"qup-config",
"qup-memory";
power-domains = <&rpmhpd RPMHPD_CX>;
required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
<&gpi_dma0 1 2 QCOM_GPI_I2C>;
dma-names = "tx",
@ -703,6 +734,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
interconnect-names = "qup-core",
"qup-config";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table>;
dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
<&gpi_dma0 1 2 QCOM_GPI_SPI>;
dma-names = "tx",
@ -728,6 +760,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
interconnect-names = "qup-core",
"qup-config";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
@ -751,6 +784,7 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
"qup-config",
"qup-memory";
power-domains = <&rpmhpd RPMHPD_CX>;
required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
<&gpi_dma0 1 3 QCOM_GPI_I2C>;
dma-names = "tx",
@ -1066,6 +1100,153 @@ mmss_noc: interconnect@1740000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
pcie: pcie@1c08000 {
device_type = "pci";
compatible = "qcom,pcie-qcs615", "qcom,pcie-sm8150";
reg = <0x0 0x01c08000 0x0 0x3000>,
<0x0 0x40000000 0x0 0xf1d>,
<0x0 0x40000f20 0x0 0xa8>,
<0x0 0x40001000 0x0 0x1000>,
<0x0 0x40100000 0x0 0x100000>,
<0x0 0x01c0b000 0x0 0x1000>;
reg-names = "parf",
"dbi",
"elbi",
"atu",
"config",
"mhi";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
bus-range = <0x00 0xff>;
dma-coherent;
linux,pci-domain = <0>;
num-lanes = <1>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
"msi3",
"msi4",
"msi5",
"msi6",
"msi7",
"global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
<&gcc GCC_PCIE_0_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
clock-names = "pipe",
"aux",
"cfg",
"bus_master",
"bus_slave",
"slave_q2a";
assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
assigned-clock-rates = <19200000>;
interconnects = <&aggre1_noc MASTER_PCIE QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "pcie-mem", "cpu-pcie";
iommu-map = <0x0 &apps_smmu 0x400 0x1>,
<0x100 &apps_smmu 0x401 0x1>;
resets = <&gcc GCC_PCIE_0_BCR>;
reset-names = "pci";
power-domains = <&gcc PCIE_0_GDSC>;
phys = <&pcie_phy>;
phy-names = "pciephy";
max-link-speed = <2>;
operating-points-v2 = <&pcie_opp_table>;
status = "disabled";
pcie_opp_table: opp-table {
compatible = "operating-points-v2";
/* GEN 1 x1 */
opp-2500000 {
opp-hz = /bits/ 64 <2500000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <250000 1>;
};
/* GEN 2 x1 */
opp-5000000 {
opp-hz = /bits/ 64 <5000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <500000 1>;
};
};
pcie_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
bus-range = <0x01 0xff>;
};
};
pcie_phy: phy@1c0e000 {
compatible = "qcom,qcs615-qmp-gen3x1-pcie-phy";
reg = <0x0 0x01c0e000 0x0 0x1000>;
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_CLKREF_CLK>,
<&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
<&gcc GCC_PCIE_0_PIPE_CLK>;
clock-names = "aux",
"cfg_ahb",
"ref",
"refgen",
"pipe";
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
reset-names = "phy";
assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
assigned-clock-rates = <100000000>;
#clock-cells = <0>;
clock-output-names = "pcie_0_pipe_clk";
#phy-cells = <0>;
status = "disabled";
};
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,qcs615-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
reg = <0x0 0x01d84000 0x0 0x3000>,
@ -1506,6 +1687,19 @@ data-pins {
};
};
gpucc: clock-controller@5090000 {
compatible = "qcom,qcs615-gpucc";
reg = <0 0x05090000 0 0x9000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GPLL0>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
stm@6002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0x0 0x06002000 0x0 0x1000>,
@ -3166,6 +3360,56 @@ glink-edge {
mboxes = <&apss_shared 4>;
label = "cdsp";
qcom,remote-pid = <5>;
fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "cdsp";
#address-cells = <1>;
#size-cells = <0>;
compute-cb@1 {
compatible = "qcom,fastrpc-compute-cb";
reg = <1>;
iommus = <&apps_smmu 0x1081 0x0>;
dma-coherent;
};
compute-cb@2 {
compatible = "qcom,fastrpc-compute-cb";
reg = <2>;
iommus = <&apps_smmu 0x1082 0x0>;
dma-coherent;
};
compute-cb@3 {
compatible = "qcom,fastrpc-compute-cb";
reg = <3>;
iommus = <&apps_smmu 0x1083 0x0>;
dma-coherent;
};
compute-cb@4 {
compatible = "qcom,fastrpc-compute-cb";
reg = <4>;
iommus = <&apps_smmu 0x1084 0x0>;
dma-coherent;
};
compute-cb@5 {
compatible = "qcom,fastrpc-compute-cb";
reg = <5>;
iommus = <&apps_smmu 0x1085 0x0>;
dma-coherent;
};
compute-cb@6 {
compatible = "qcom,fastrpc-compute-cb";
reg = <6>;
iommus = <&apps_smmu 0x1086 0x0>;
dma-coherent;
};
};
};
};
@ -3317,6 +3561,119 @@ gem_noc: interconnect@9680000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
venus: video-codec@aa00000 {
compatible = "qcom,qcs615-venus", "qcom,sc7180-venus";
reg = <0x0 0x0aa00000 0x0 0x100000>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
<&videocc VIDEO_CC_VENUS_AHB_CLK>,
<&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
<&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
<&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
clock-names = "core",
"iface",
"bus",
"vcodec0_core",
"vcodec0_bus";
power-domains = <&videocc VENUS_GDSC>,
<&videocc VCODEC0_GDSC>,
<&rpmhpd RPMHPD_CX>;
power-domain-names = "venus",
"vcodec0",
"cx";
operating-points-v2 = <&venus_opp_table>;
interconnects = <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "video-mem",
"cpu-cfg";
iommus = <&apps_smmu 0xe60 0x20>;
memory-region = <&pil_video_mem>;
status = "disabled";
venus_opp_table: opp-table {
compatible = "operating-points-v2";
opp-133330000 {
opp-hz = /bits/ 64 <133330000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-240000000 {
opp-hz = /bits/ 64 <240000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
opp-380000000 {
opp-hz = /bits/ 64 <380000000>;
required-opps = <&rpmhpd_opp_nom>;
};
opp-410000000 {
opp-hz = /bits/ 64 <410000000>;
required-opps = <&rpmhpd_opp_nom_l1>;
};
opp-460000000 {
opp-hz = /bits/ 64 <460000000>;
required-opps = <&rpmhpd_opp_turbo>;
};
};
};
videocc: clock-controller@ab00000 {
compatible = "qcom,qcs615-videocc";
reg = <0 0x0ab00000 0 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
camcc: clock-controller@ad00000 {
compatible = "qcom,qcs615-camcc";
reg = <0 0x0ad00000 0 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
dispcc: clock-controller@af00000 {
compatible = "qcom,qcs615-dispcc";
reg = <0 0x0af00000 0 0x20000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
<0>,
<0>,
<0>,
<0>,
<0>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
pdc: interrupt-controller@b220000 {
compatible = "qcom,qcs615-pdc", "qcom,pdc";
reg = <0x0 0x0b220000 0x0 0x30000>,
@ -3456,6 +3813,7 @@ intc: interrupt-controller@17a00000 {
reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
<0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <0>;
#interrupt-cells = <3>;
interrupt-controller;
#redistributor-regions = <1>;
@ -3473,6 +3831,7 @@ watchdog: watchdog@17c10000 {
compatible = "qcom,apss-wdt-qcs615", "qcom,kpss-wdt";
reg = <0x0 0x17c10000 0x0 0x1000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sleep_clk>;
};
timer@17c20000 {
@ -3562,6 +3921,7 @@ apps_bcm_voter: bcm-voter {
rpmhcc: clock-controller {
compatible = "qcom,qcs615-rpmh-clk";
clocks = <&xo_board_clk>;
clock-names = "xo";
#clock-cells = <1>;
@ -3838,8 +4198,58 @@ glink_edge: glink-edge {
mboxes = <&apss_shared 24>;
label = "lpass";
qcom,remote-pid = <2>;
fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "adsp";
#address-cells = <1>;
#size-cells = <0>;
compute-cb@3 {
compatible = "qcom,fastrpc-compute-cb";
reg = <3>;
iommus = <&apps_smmu 0x1723 0x0>;
dma-coherent;
};
compute-cb@4 {
compatible = "qcom,fastrpc-compute-cb";
reg = <4>;
iommus = <&apps_smmu 0x1724 0x0>;
dma-coherent;
};
compute-cb@5 {
compatible = "qcom,fastrpc-compute-cb";
reg = <5>;
iommus = <&apps_smmu 0x1725 0x0>;
dma-coherent;
};
compute-cb@6 {
compatible = "qcom,fastrpc-compute-cb";
reg = <6>;
iommus = <&apps_smmu 0x1726 0x0>;
qcom,nsessions = <5>;
dma-coherent;
};
};
};
};
cpufreq_hw: cpufreq@18323000 {
compatible = "qcom,qcs615-cpufreq-hw", "qcom,cpufreq-hw";
reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
reg-names = "freq-domain0", "freq-domain1";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
clock-names = "xo", "alternate";
#freq-domain-cells = <1>;
#clock-cells = <1>;
};
};
arch_timer: timer {

16
arch/arm64/boot/dts/qcom/sm6350.dtsi
View File

@ -1351,6 +1351,13 @@ q6afecc: clock-controller {
compatible = "qcom,q6afe-clocks";
#clock-cells = <2>;
};
q6usbdai: usbd {
compatible = "qcom,q6usb";
iommus = <&apps_smmu 0x100f 0x0>;
#sound-dai-cells = <1>;
qcom,usb-audio-intr-idx = /bits/ 16 <2>;
};
};
q6asm: service@7 {
@ -1979,6 +1986,7 @@ usb_1_dwc3: usb@a600000 {
reg = <0x0 0x0a600000 0x0 0xcd00>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&apps_smmu 0x540 0x0>;
num-hc-interrupters = /bits/ 16 <3>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,has-lpm-erratum;
@ -2479,6 +2487,11 @@ aoss_qmp: power-management@c300000 {
#clock-cells = <0>;
};
sram@c3f0000 {
compatible = "qcom,rpmh-stats";
reg = <0x0 0x0c3f0000 0x0 0x400>;
};
spmi_bus: spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0 0x0c440000 0x0 0x1100>,
@ -2962,6 +2975,9 @@ wifi: wifi@18800000 {
};
};
sound: sound {
};
thermal-zones {
aoss0-thermal {
thermal-sensors = <&tsens0 0>;

36
arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts
View File

@ -19,6 +19,7 @@
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include <dt-bindings/sound/qcom,q6asm.h>
#include <dt-bindings/usb/pd.h>
#include "sm7225.dtsi"
#include "pm6150l.dtsi"
@ -938,6 +939,12 @@ channel@644 {
};
};
&q6asmdai {
dai@0 {
reg = <MSM_FRONTEND_DAI_MULTIMEDIA1>;
};
};
&qup_uart1_cts {
/*
* Configure a bias-bus-hold on CTS to lower power
@ -1006,6 +1013,35 @@ &sdhc_2 {
status = "okay";
};
&sound {
compatible = "fairphone,fp4-sndcard";
model = "Fairphone 4";
mm1-dai-link {
link-name = "MultiMedia1";
cpu {
sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>;
};
};
usb-dai-link {
link-name = "USB Playback";
codec {
sound-dai = <&q6usbdai USB_RX>;
};
cpu {
sound-dai = <&q6afedai USB_RX>;
};
platform {
sound-dai = <&q6routing>;
};
};
};
&tlmm {
gpio-reserved-ranges = <13 4>, <56 2>;

6
arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts
View File

@ -1425,16 +1425,14 @@ &ufs_mem_phy {
&usb_1 {
/* USB 2.0 only */
qcom,select-utmi-as-pipe-clk;
status = "okay";
};
&usb_1_dwc3 {
dr_mode = "otg";
usb-role-switch;
maximum-speed = "high-speed";
/* Remove USB3 phy */
phys = <&usb_1_hsphy>;
phy-names = "usb2-phy";
status = "okay";
};
&usb_1_dwc3_hs {

24
arch/arm64/boot/dts/qcom/sm8150-hdk.dts
View File

@ -478,15 +478,11 @@ &mdss_dsi0 {
qcom,dual-dsi-mode;
qcom,master-dsi;
};
ports {
port@1 {
endpoint {
remote-endpoint = <&lt9611_a>;
data-lanes = <0 1 2 3>;
};
};
};
&mdss_dsi0_out {
remote-endpoint = <&lt9611_a>;
data-lanes = <0 1 2 3>;
};
&mdss_dsi0_phy {
@ -504,15 +500,11 @@ &mdss_dsi1 {
<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
status = "okay";
};
ports {
port@1 {
endpoint {
remote-endpoint = <&lt9611_b>;
data-lanes = <0 1 2 3>;
};
};
};
&mdss_dsi1_out {
remote-endpoint = <&lt9611_b>;
data-lanes = <0 1 2 3>;
};
&mdss_dsi1_phy {

19
arch/arm64/boot/dts/qcom/sm8150.dtsi
View File

@ -1866,10 +1866,10 @@ pcie0: pcie@1c00000 {
"global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
<&gcc GCC_PCIE_0_AUX_CLK>,
@ -1981,10 +1981,10 @@ pcie1: pcie@1c08000 {
"global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
<&gcc GCC_PCIE_1_AUX_CLK>,
@ -3908,7 +3908,7 @@ mdss_dp: displayport-controller@ae90000 {
#sound-dai-cells = <0>;
operating-points-v2 = <&dp_opp_table>;
power-domains = <&rpmhpd SM8250_MMCX>;
power-domains = <&rpmhpd SM8150_MMCX>;
status = "disabled";
@ -4366,6 +4366,7 @@ compute-cb@5 {
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <3>;
reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
<0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */

204
arch/arm64/boot/dts/qcom/sm8250-samsung-common.dtsi Normal file
View File

@ -0,0 +1,204 @@
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sm8250.dtsi"
#include "pm8150.dtsi"
/ {
chosen {
#address-cells = <2>;
#size-cells = <2>;
ranges;
framebuffer: framebuffer@9c000000 {
compatible = "simple-framebuffer";
reg = <0x0 0x9c000000 0x0 0x2300000>;
width = <1080>;
height = <2400>;
stride = <(1080 * 4)>;
format = "a8r8g8b8";
};
};
gpio_keys: gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&vol_up_n>;
key-vol-up {
label = "Volume Up";
gpios = <&pm8150_gpios 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
debounce-interval = <15>;
linux,can-disable;
wakeup-source;
};
};
reserved-memory {
cont_splash_mem: memory@9c000000 {
reg = <0x0 0x9c000000 0x0 0x2300000>;
no-map;
};
ramoops@9fa00000 {
compatible = "ramoops";
reg = <0x0 0x9fa00000 0x0 0x100000>;
record-size = <0x4000>;
console-size = <0x40000>;
ftrace-size = <0x40000>;
pmsg-size = <0x40000>;
no-map;
};
};
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
};
};
&apps_rsc {
regulators-0 {
compatible = "qcom,pm8150-rpmh-regulators";
qcom,pmic-id = "a";
vdd-s1-supply = <&vph_pwr>;
vdd-s2-supply = <&vph_pwr>;
vdd-s3-supply = <&vph_pwr>;
vdd-s4-supply = <&vph_pwr>;
vdd-s5-supply = <&vph_pwr>;
vdd-s6-supply = <&vph_pwr>;
vdd-s7-supply = <&vph_pwr>;
vdd-s8-supply = <&vph_pwr>;
vdd-s9-supply = <&vph_pwr>;
vdd-s10-supply = <&vph_pwr>;
vreg_s4a_1p8: smps4 {
regulator-name = "vreg_s4a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1920000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2a_3p1: ldo2 {
regulator-name = "vreg_l2a_3p1";
regulator-min-microvolt = <3072000>;
regulator-max-microvolt = <3072000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l5a_0p88: ldo5 {
regulator-name = "vreg_l5a_0p88";
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <880000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6a_1p2: ldo6 {
regulator-name = "vreg_l6a_1p2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9a_1p2: ldo9 {
regulator-name = "vreg_l9a_1p2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l12a_1p8: ldo12 {
regulator-name = "vreg_l12a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l17a_3p0: ldo17 {
regulator-name = "vreg_l17a_3p0";
regulator-min-microvolt = <2496000>;
regulator-max-microvolt = <3008000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
};
};
&pm8150_gpios {
vol_up_n: vol-up-n-state {
pins = "gpio3";
function = "normal";
power-source = <0>;
input-enable;
bias-pull-up;
};
};
&pon_pwrkey {
status = "okay";
};
&pon_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
};
&tlmm {
gpio-reserved-ranges = <40 4>; /* I2C (Unused) */
};
&usb_1 {
/* Limit to USB 2.0 for now */
qcom,select-utmi-as-pipe-clk;
status = "okay";
};
&usb_1_dwc3 {
dr_mode = "peripheral";
maximum-speed = "high-speed";
/* Remove USB3 phy */
phys = <&usb_1_hsphy>;
phy-names = "usb2-phy";
};
&usb_1_hsphy {
vdda-pll-supply = <&vreg_l5a_0p88>;
vdda18-supply = <&vreg_l12a_1p8>;
vdda33-supply = <&vreg_l2a_3p1>;
status = "okay";
};
&ufs_mem_hc {
vcc-supply = <&vreg_l17a_3p0>;
vcc-max-microamp = <800000>;
vccq-supply = <&vreg_l6a_1p2>;
vccq-max-microamp = <800000>;
vccq2-supply = <&vreg_s4a_1p8>;
vccq2-max-microamp = <800000>;
status = "okay";
};
&ufs_mem_phy {
vdda-phy-supply = <&vreg_l5a_0p88>;
vdda-pll-supply = <&vreg_l9a_1p2>;
status = "okay";
};

26
arch/arm64/boot/dts/qcom/sm8250-samsung-r8q.dts Normal file
View File

@ -0,0 +1,26 @@
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
#include "sm8250-samsung-common.dtsi"
/ {
model = "Samsung Galaxy S20 FE";
compatible = "samsung,r8q", "qcom,sm8250";
chassis-type = "handset";
};
&adsp {
firmware-name = "qcom/sm8250/Samsung/r8q/adsp.mbn";
status = "okay";
};
&cdsp {
firmware-name = "qcom/sm8250/Samsung/r8q/cdsp.mbn";
status = "okay";
};
&slpi {
firmware-name = "qcom/sm8250/Samsung/r8q/slpi.mbn";
status = "okay";
};

26
arch/arm64/boot/dts/qcom/sm8250-samsung-x1q.dts Normal file
View File

@ -0,0 +1,26 @@
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
#include "sm8250-samsung-common.dtsi"
/ {
model = "Samsung Galaxy S20";
compatible = "samsung,x1q", "qcom,sm8250";
chassis-type = "handset";
};
&adsp {
firmware-name = "qcom/sm8250/Samsung/x1q/adsp.mbn";
status = "okay";
};
&cdsp {
firmware-name = "qcom/sm8250/Samsung/x1q/cdsp.mbn";
status = "okay";
};
&slpi {
firmware-name = "qcom/sm8250/Samsung/x1q/slpi.mbn";
status = "okay";
};

96
arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts
View File

@ -12,7 +12,6 @@
#include "pm8150.dtsi"
#include "pm8150b.dtsi"
#include "pm8150l.dtsi"
#include "pm8009.dtsi"
/*
* Delete following upstream (sm8250.dtsi) reserved
@ -50,18 +49,12 @@ framebuffer: framebuffer@9c000000 {
};
};
battery_l: battery-l {
battery: battery {
compatible = "simple-battery";
voltage-min-design-microvolt = <3870000>;
energy-full-design-microwatt-hours = <16700000>;
charge-full-design-microamp-hours = <4420000>;
};
battery_r: battery-r {
compatible = "simple-battery";
voltage-min-design-microvolt = <3870000>;
energy-full-design-microwatt-hours = <16700000>;
charge-full-design-microamp-hours = <4420000>;
charge-full-design-microamp-hours = <8840000>;
energy-full-design-microwatt-hours = <34300000>;
voltage-min-design-microvolt = <3400000>;
voltage-max-design-microvolt = <4370000>;
};
bl_vddpos_5p5: bl-vddpos-regulator {
@ -406,63 +399,6 @@ vreg_l11c_3p0: ldo11 {
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
regulators-2 {
compatible = "qcom,pm8009-rpmh-regulators";
qcom,pmic-id = "f";
vdd-s1-supply = <&vph_pwr>;
vdd-s2-supply = <&vreg_bob>;
vdd-l2-supply = <&vreg_s8c_1p35>;
vdd-l5-l6-supply = <&vreg_bob>;
vdd-l7-supply = <&vreg_s4a_1p8>;
vreg_s1f_1p2: smps1 {
regulator-name = "vreg_s1f_1p2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1300000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s2f_0p5: smps2 {
regulator-name = "vreg_s2f_0p5";
regulator-min-microvolt = <512000>;
regulator-max-microvolt = <1100000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
/* L1 is unused. */
vreg_l2f_1p3: ldo2 {
regulator-name = "vreg_l2f_1p3";
regulator-min-microvolt = <1056000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
/* L3 & L4 are unused. */
vreg_l5f_2p8: ldo5 {
regulator-name = "vreg_l5f_2p85";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <3000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6f_2p8: ldo6 {
regulator-name = "vreg_l6f_2p8";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <3000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7f_1p8: ldo7 {
regulator-name = "vreg_l7f_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
};
&cdsp {
@ -495,17 +431,6 @@ zap-shader {
};
};
&i2c0 {
clock-frequency = <400000>;
status = "okay";
fuel-gauge@55 {
compatible = "ti,bq27z561";
reg = <0x55>;
monitored-battery = <&battery_r>;
};
};
&i2c11 {
clock-frequency = <400000>;
status = "okay";
@ -523,17 +448,6 @@ backlight: backlight@11 {
};
};
&i2c13 {
clock-frequency = <400000>;
status = "okay";
fuel-gauge@55 {
compatible = "ti,bq27z561";
reg = <0x55>;
monitored-battery = <&battery_l>;
};
};
&pcie0 {
status = "okay";
};

75
arch/arm64/boot/dts/qcom/sm8250.dtsi
View File

@ -1030,7 +1030,7 @@ i2c14: i2c@880000 {
dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
<&gpi_dma2 1 0 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
power-domains = <&rpmhpd RPMHPD_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
@ -1075,7 +1075,7 @@ i2c15: i2c@884000 {
dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
<&gpi_dma2 1 1 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
power-domains = <&rpmhpd RPMHPD_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
@ -1120,7 +1120,7 @@ i2c16: i2c@888000 {
dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
<&gpi_dma2 1 2 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
power-domains = <&rpmhpd RPMHPD_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
@ -1165,7 +1165,7 @@ i2c17: i2c@88c000 {
dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
<&gpi_dma2 1 3 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
power-domains = <&rpmhpd RPMHPD_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
@ -1227,7 +1227,7 @@ i2c18: i2c@890000 {
dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
<&gpi_dma2 1 4 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
power-domains = <&rpmhpd RPMHPD_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
@ -1289,7 +1289,7 @@ i2c19: i2c@894000 {
dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
<&gpi_dma2 1 5 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
power-domains = <&rpmhpd RPMHPD_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
<&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
@ -1370,7 +1370,7 @@ i2c0: i2c@980000 {
dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
<&gpi_dma0 1 0 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
power-domains = <&rpmhpd RPMHPD_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
@ -1415,7 +1415,7 @@ i2c1: i2c@984000 {
dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
<&gpi_dma0 1 1 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
power-domains = <&rpmhpd RPMHPD_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
@ -1460,7 +1460,7 @@ i2c2: i2c@988000 {
dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
<&gpi_dma0 1 2 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
power-domains = <&rpmhpd RPMHPD_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
@ -1522,7 +1522,7 @@ i2c3: i2c@98c000 {
dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
<&gpi_dma0 1 3 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
power-domains = <&rpmhpd RPMHPD_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
@ -1567,7 +1567,7 @@ i2c4: i2c@990000 {
dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
<&gpi_dma0 1 4 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
power-domains = <&rpmhpd RPMHPD_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
@ -1612,7 +1612,7 @@ i2c5: i2c@994000 {
dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
<&gpi_dma0 1 5 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
power-domains = <&rpmhpd RPMHPD_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
@ -1657,7 +1657,7 @@ i2c6: i2c@998000 {
dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
<&gpi_dma0 1 6 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
power-domains = <&rpmhpd RPMHPD_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
@ -1719,7 +1719,7 @@ i2c7: i2c@99c000 {
dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
<&gpi_dma0 1 7 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
power-domains = <&rpmhpd RPMHPD_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
@ -1797,7 +1797,7 @@ i2c8: i2c@a80000 {
dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
<&gpi_dma1 1 0 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
power-domains = <&rpmhpd RPMHPD_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
@ -1842,7 +1842,7 @@ i2c9: i2c@a84000 {
dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
<&gpi_dma1 1 1 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
power-domains = <&rpmhpd RPMHPD_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
@ -1887,7 +1887,7 @@ i2c10: i2c@a88000 {
dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
<&gpi_dma1 1 2 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
power-domains = <&rpmhpd RPMHPD_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
@ -1932,7 +1932,7 @@ i2c11: i2c@a8c000 {
dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
<&gpi_dma1 1 3 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
power-domains = <&rpmhpd RPMHPD_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
@ -1977,7 +1977,7 @@ i2c12: i2c@a90000 {
dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
<&gpi_dma1 1 4 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
power-domains = <&rpmhpd RPMHPD_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
@ -2039,7 +2039,7 @@ i2c13: i2c@a94000 {
dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
<&gpi_dma1 1 5 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
power-domains = <&rpmhpd RPMHPD_CX>;
interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
@ -2163,10 +2163,10 @@ pcie0: pcie@1c00000 {
"global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
<&gcc GCC_PCIE_0_AUX_CLK>,
@ -2285,10 +2285,10 @@ pcie1: pcie@1c08000 {
"global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
<&gcc GCC_PCIE_1_AUX_CLK>,
@ -2412,10 +2412,10 @@ pcie2: pcie@1c10000 {
"global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
interrupt-map = <0 0 0 1 &intc GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
<&gcc GCC_PCIE_2_AUX_CLK>,
@ -4338,14 +4338,6 @@ venus: video-codec@aa00000 {
status = "disabled";
video-decoder {
compatible = "venus-decoder";
};
video-encoder {
compatible = "venus-encoder";
};
venus_opp_table: opp-table {
compatible = "operating-points-v2";
@ -4797,7 +4789,7 @@ mdss_dp: displayport-controller@ae90000 {
#sound-dai-cells = <0>;
operating-points-v2 = <&dp_opp_table>;
power-domains = <&rpmhpd SM8250_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
status = "disabled";
@ -6092,6 +6084,7 @@ compute-cb@5 {
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
#address-cells = <0>;
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */

12
arch/arm64/boot/dts/qcom/sm8350-hdk.dts
View File

@ -385,15 +385,11 @@ &cdsp {
&mdss_dsi0 {
vdda-supply = <&vreg_l6b_1p2>;
status = "okay";
};
ports {
port@1 {
endpoint {
remote-endpoint = <&lt9611_a>;
data-lanes = <0 1 2 3>;
};
};
};
&mdss_dsi0_out {
remote-endpoint = <&lt9611_a>;
data-lanes = <0 1 2 3>;
};
&mdss_dsi0_phy {

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