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https://github.com/torvalds/linux.git
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Merge branch 'net-bcmgenet-revise-suspend-resume'
Doug Berger says: ==================== net: bcmgenet: revise suspend/resume This commit set updates the GENET driver to reduce the delay to resume the ethernet link when the Wake on Lan features are used. In addition, the encoding of hardware versioning and features is revised to avoid some redundancy and improve readability as well as remove a warning that occurred for the BCM7712 device which updated the device major version while maintaining compatibility with the driver. The assignment of hardware descriptor rings was modified to simplify programming and to allow support for the hardware RX_CLS_FLOW_DISC filter action. ==================== Link: https://patch.msgid.link/20250306192643.2383632-1-opendmb@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski
commit
a3cc3f424d
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2014-2024 Broadcom
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* Copyright (c) 2014-2025 Broadcom
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*/
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#ifndef __BCMGENET_H__
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@ -18,6 +18,9 @@
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#include "../unimac.h"
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/* Maximum number of hardware queues, downsized if needed */
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#define GENET_MAX_MQ_CNT 4
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/* total number of Buffer Descriptors, same for Rx/Tx */
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#define TOTAL_DESC 256
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@ -271,6 +274,8 @@ struct bcmgenet_mib_counters {
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/* Only valid for GENETv3+ */
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#define UMAC_IRQ_MDIO_DONE (1 << 23)
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#define UMAC_IRQ_MDIO_ERROR (1 << 24)
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#define UMAC_IRQ_MDIO_EVENT (UMAC_IRQ_MDIO_DONE | \
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UMAC_IRQ_MDIO_ERROR)
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/* INTRL2 instance 1 definitions */
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#define UMAC_IRQ1_TX_INTR_MASK 0xFFFF
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@ -476,6 +481,7 @@ enum bcmgenet_version {
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#define GENET_HAS_EXT (1 << 1)
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#define GENET_HAS_MDIO_INTR (1 << 2)
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#define GENET_HAS_MOCA_LINK_DET (1 << 3)
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#define GENET_HAS_EPHY_16NM (1 << 4)
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/* BCMGENET hardware parameters, keep this structure nicely aligned
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* since it is going to be used in hot paths
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@ -496,7 +502,6 @@ struct bcmgenet_hw_params {
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u32 rdma_offset;
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u32 tdma_offset;
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u32 words_per_bd;
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u32 flags;
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};
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struct bcmgenet_skb_cb {
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@ -513,7 +518,6 @@ struct bcmgenet_tx_ring {
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unsigned long packets;
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unsigned long bytes;
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unsigned int index; /* ring index */
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unsigned int queue; /* queue index */
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struct enet_cb *cbs; /* tx ring buffer control block*/
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unsigned int size; /* size of each tx ring */
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unsigned int clean_ptr; /* Tx ring clean pointer */
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@ -523,8 +527,6 @@ struct bcmgenet_tx_ring {
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unsigned int prod_index; /* Tx ring producer index SW copy */
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unsigned int cb_ptr; /* Tx ring initial CB ptr */
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unsigned int end_ptr; /* Tx ring end CB ptr */
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void (*int_enable)(struct bcmgenet_tx_ring *);
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void (*int_disable)(struct bcmgenet_tx_ring *);
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struct bcmgenet_priv *priv;
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};
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@ -553,8 +555,6 @@ struct bcmgenet_rx_ring {
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struct bcmgenet_net_dim dim;
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u32 rx_max_coalesced_frames;
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u32 rx_coalesce_usecs;
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void (*int_enable)(struct bcmgenet_rx_ring *);
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void (*int_disable)(struct bcmgenet_rx_ring *);
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struct bcmgenet_priv *priv;
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};
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@ -583,7 +583,7 @@ struct bcmgenet_priv {
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struct enet_cb *tx_cbs;
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unsigned int num_tx_bds;
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struct bcmgenet_tx_ring tx_rings[DESC_INDEX + 1];
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struct bcmgenet_tx_ring tx_rings[GENET_MAX_MQ_CNT + 1];
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/* receive variables */
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void __iomem *rx_bds;
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@ -593,10 +593,11 @@ struct bcmgenet_priv {
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struct bcmgenet_rxnfc_rule rxnfc_rules[MAX_NUM_OF_FS_RULES];
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struct list_head rxnfc_list;
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struct bcmgenet_rx_ring rx_rings[DESC_INDEX + 1];
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struct bcmgenet_rx_ring rx_rings[GENET_MAX_MQ_CNT + 1];
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/* other misc variables */
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struct bcmgenet_hw_params *hw_params;
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const struct bcmgenet_hw_params *hw_params;
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u32 flags;
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unsigned autoneg_pause:1;
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unsigned tx_pause:1;
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unsigned rx_pause:1;
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@ -615,7 +616,6 @@ struct bcmgenet_priv {
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phy_interface_t phy_interface;
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int phy_addr;
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int ext_phy;
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bool ephy_16nm;
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/* Interrupt variables */
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struct work_struct bcmgenet_irq_work;
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@ -643,13 +643,37 @@ struct bcmgenet_priv {
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struct clk *clk_wol;
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u32 wolopts;
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u8 sopass[SOPASS_MAX];
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bool wol_active;
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struct bcmgenet_mib_counters mib;
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struct ethtool_keee eee;
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};
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static inline bool bcmgenet_has_40bits(struct bcmgenet_priv *priv)
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{
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return !!(priv->flags & GENET_HAS_40BITS);
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}
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static inline bool bcmgenet_has_ext(struct bcmgenet_priv *priv)
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{
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return !!(priv->flags & GENET_HAS_EXT);
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}
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static inline bool bcmgenet_has_mdio_intr(struct bcmgenet_priv *priv)
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{
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return !!(priv->flags & GENET_HAS_MDIO_INTR);
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}
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static inline bool bcmgenet_has_moca_link_det(struct bcmgenet_priv *priv)
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{
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return !!(priv->flags & GENET_HAS_MOCA_LINK_DET);
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}
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static inline bool bcmgenet_has_ephy_16nm(struct bcmgenet_priv *priv)
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{
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return !!(priv->flags & GENET_HAS_EPHY_16NM);
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}
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#define GENET_IO_MACRO(name, offset) \
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static inline u32 bcmgenet_##name##_readl(struct bcmgenet_priv *priv, \
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u32 off) \
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@ -702,8 +726,8 @@ void bcmgenet_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol);
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int bcmgenet_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol);
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int bcmgenet_wol_power_down_cfg(struct bcmgenet_priv *priv,
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enum bcmgenet_power_mode mode);
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void bcmgenet_wol_power_up_cfg(struct bcmgenet_priv *priv,
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enum bcmgenet_power_mode mode);
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int bcmgenet_wol_power_up_cfg(struct bcmgenet_priv *priv,
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enum bcmgenet_power_mode mode);
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void bcmgenet_eee_enable_set(struct net_device *dev, bool enable,
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bool tx_lpi_enabled);
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@ -2,7 +2,7 @@
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/*
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* Broadcom GENET (Gigabit Ethernet) Wake-on-LAN support
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*
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* Copyright (c) 2014-2024 Broadcom
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* Copyright (c) 2014-2025 Broadcom
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*/
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#define pr_fmt(fmt) "bcmgenet_wol: " fmt
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@ -145,8 +145,7 @@ int bcmgenet_wol_power_down_cfg(struct bcmgenet_priv *priv,
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enum bcmgenet_power_mode mode)
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{
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struct net_device *dev = priv->dev;
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struct bcmgenet_rxnfc_rule *rule;
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u32 reg, hfb_ctrl_reg, hfb_enable = 0;
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u32 reg, hfb_ctrl_reg;
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int retries = 0;
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if (mode != GENET_POWER_WOL_MAGIC) {
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@ -154,18 +153,6 @@ int bcmgenet_wol_power_down_cfg(struct bcmgenet_priv *priv,
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return -EINVAL;
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}
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/* Can't suspend with WoL if MAC is still in reset */
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spin_lock_bh(&priv->reg_lock);
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reg = bcmgenet_umac_readl(priv, UMAC_CMD);
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if (reg & CMD_SW_RESET)
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reg &= ~CMD_SW_RESET;
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/* disable RX */
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reg &= ~CMD_RX_EN;
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bcmgenet_umac_writel(priv, reg, UMAC_CMD);
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spin_unlock_bh(&priv->reg_lock);
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mdelay(10);
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if (priv->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) {
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reg = bcmgenet_umac_readl(priv, UMAC_MPD_CTRL);
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reg |= MPD_EN;
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@ -177,13 +164,8 @@ int bcmgenet_wol_power_down_cfg(struct bcmgenet_priv *priv,
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}
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hfb_ctrl_reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL);
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if (priv->wolopts & WAKE_FILTER) {
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list_for_each_entry(rule, &priv->rxnfc_list, list)
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if (rule->fs.ring_cookie == RX_CLS_FLOW_WAKE)
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hfb_enable |= (1 << rule->fs.location);
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reg = (hfb_ctrl_reg & ~RBUF_HFB_EN) | RBUF_ACPI_EN;
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bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL);
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}
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reg = hfb_ctrl_reg | RBUF_ACPI_EN;
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bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL);
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/* Do not leave UniMAC in MPD mode only */
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retries = bcmgenet_poll_wol_status(priv);
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@ -198,15 +180,12 @@ int bcmgenet_wol_power_down_cfg(struct bcmgenet_priv *priv,
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netif_dbg(priv, wol, dev, "MPD WOL-ready status set after %d msec\n",
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retries);
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clk_prepare_enable(priv->clk_wol);
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priv->wol_active = 1;
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/* Disable phy status updates while suspending */
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mutex_lock(&dev->phydev->lock);
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dev->phydev->state = PHY_READY;
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mutex_unlock(&dev->phydev->lock);
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if (hfb_enable) {
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bcmgenet_hfb_reg_writel(priv, hfb_enable,
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HFB_FLT_ENABLE_V3PLUS + 4);
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hfb_ctrl_reg = RBUF_HFB_EN | RBUF_ACPI_EN;
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bcmgenet_hfb_reg_writel(priv, hfb_ctrl_reg, HFB_CTRL);
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}
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clk_prepare_enable(priv->clk_wol);
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/* Enable CRC forward */
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spin_lock_bh(&priv->reg_lock);
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@ -214,13 +193,17 @@ int bcmgenet_wol_power_down_cfg(struct bcmgenet_priv *priv,
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priv->crc_fwd_en = 1;
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reg |= CMD_CRC_FWD;
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/* Can't suspend with WoL if MAC is still in reset */
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if (reg & CMD_SW_RESET)
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reg &= ~CMD_SW_RESET;
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/* Receiver must be enabled for WOL MP detection */
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reg |= CMD_RX_EN;
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bcmgenet_umac_writel(priv, reg, UMAC_CMD);
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spin_unlock_bh(&priv->reg_lock);
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reg = UMAC_IRQ_MPD_R;
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if (hfb_enable)
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if (hfb_ctrl_reg & RBUF_HFB_EN)
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reg |= UMAC_IRQ_HFB_SM | UMAC_IRQ_HFB_MM;
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bcmgenet_intrl2_0_writel(priv, reg, INTRL2_CPU_MASK_CLEAR);
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@ -228,40 +211,42 @@ int bcmgenet_wol_power_down_cfg(struct bcmgenet_priv *priv,
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return 0;
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}
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void bcmgenet_wol_power_up_cfg(struct bcmgenet_priv *priv,
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enum bcmgenet_power_mode mode)
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int bcmgenet_wol_power_up_cfg(struct bcmgenet_priv *priv,
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enum bcmgenet_power_mode mode)
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{
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struct net_device *dev = priv->dev;
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u32 reg;
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if (mode != GENET_POWER_WOL_MAGIC) {
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netif_err(priv, wol, priv->dev, "invalid mode: %d\n", mode);
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return;
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return -EINVAL;
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}
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if (!priv->wol_active)
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return; /* failed to suspend so skip the rest */
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priv->wol_active = 0;
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clk_disable_unprepare(priv->clk_wol);
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priv->crc_fwd_en = 0;
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bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_WAKE_EVENT,
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INTRL2_CPU_MASK_SET);
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if (bcmgenet_has_mdio_intr(priv))
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bcmgenet_intrl2_0_writel(priv,
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UMAC_IRQ_MDIO_EVENT,
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INTRL2_CPU_MASK_CLEAR);
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/* Disable Magic Packet Detection */
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if (priv->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) {
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reg = bcmgenet_umac_readl(priv, UMAC_MPD_CTRL);
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if (!(reg & MPD_EN))
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return; /* already reset so skip the rest */
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return -EPERM; /* already reset so skip the rest */
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reg &= ~(MPD_EN | MPD_PW_EN);
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bcmgenet_umac_writel(priv, reg, UMAC_MPD_CTRL);
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}
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/* Disable WAKE_FILTER Detection */
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if (priv->wolopts & WAKE_FILTER) {
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reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL);
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if (!(reg & RBUF_ACPI_EN))
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return; /* already reset so skip the rest */
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reg &= ~(RBUF_HFB_EN | RBUF_ACPI_EN);
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bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL);
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}
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/* Disable ACPI mode */
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reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL);
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if (!(reg & RBUF_ACPI_EN))
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return -EPERM; /* already reset so skip the rest */
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reg &= ~RBUF_ACPI_EN;
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bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL);
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/* Disable CRC Forward */
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spin_lock_bh(&priv->reg_lock);
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@ -269,4 +254,14 @@ void bcmgenet_wol_power_up_cfg(struct bcmgenet_priv *priv,
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reg &= ~CMD_CRC_FWD;
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bcmgenet_umac_writel(priv, reg, UMAC_CMD);
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spin_unlock_bh(&priv->reg_lock);
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/* Resume link status tracking */
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mutex_lock(&dev->phydev->lock);
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if (dev->phydev->link)
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dev->phydev->state = PHY_RUNNING;
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else
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dev->phydev->state = PHY_NOLINK;
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mutex_unlock(&dev->phydev->lock);
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return 0;
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}
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@ -2,7 +2,7 @@
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/*
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* Broadcom GENET MDIO routines
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*
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* Copyright (c) 2014-2024 Broadcom
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* Copyright (c) 2014-2025 Broadcom
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*/
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#include <linux/acpi.h>
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@ -154,7 +154,7 @@ void bcmgenet_phy_power_set(struct net_device *dev, bool enable)
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u32 reg = 0;
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/* EXT_GPHY_CTRL is only valid for GENETv4 and onward */
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if (GENET_IS_V4(priv) || priv->ephy_16nm) {
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if (GENET_IS_V4(priv) || bcmgenet_has_ephy_16nm(priv)) {
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reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL);
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if (enable) {
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reg &= ~EXT_CK25_DIS;
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@ -184,7 +184,7 @@ void bcmgenet_phy_power_set(struct net_device *dev, bool enable)
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static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv)
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{
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if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
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if (bcmgenet_has_moca_link_det(priv))
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fixed_phy_set_link_update(priv->dev->phydev,
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bcmgenet_fixed_phy_link_update);
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}
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