drm/amd/display: export get_power_profile interface for later use

[why]
export dcn401 get_power_profile for later asic.

Reviewed-by: Roman Li <roman.li@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Charlene Liu 2026-03-06 10:40:07 -05:00 committed by Alex Deucher
parent fc25911755
commit a3c7ab163b
4 changed files with 4 additions and 1 deletions

View File

@ -1790,7 +1790,7 @@ static void dcn401_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx)
}
}
static int dcn401_get_power_profile(const struct dc_state *context)
int dcn401_get_power_profile(const struct dc_state *context)
{
int uclk_mhz = context->bw_ctx.bw.dcn.clk.dramclk_khz / 1000;
int dpm_level = 0;

View File

@ -32,6 +32,7 @@ void dcn401_get_default_tiling_info(struct dc_tiling_info *tiling_info);
unsigned int dcn401_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx);
int dcn401_get_power_profile(const struct dc_state *context);
/* Following are definitions for run time init of reg offsets */
/* HUBP */

View File

@ -1791,6 +1791,7 @@ static struct resource_funcs dcn42_res_pool_funcs = {
.calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes,
.prepare_mcache_programming = dcn42_prepare_mcache_programming,
.build_pipe_pix_clk_params = dcn42_build_pipe_pix_clk_params,
.get_power_profile = dcn401_get_power_profile,
.get_vstartup_for_pipe = dcn401_get_vstartup_for_pipe,
.get_max_hw_cursor_size = dcn42_get_max_hw_cursor_size,
.get_default_tiling_info = dcn10_get_default_tiling_info

View File

@ -586,5 +586,6 @@ enum dc_status dcn42_validate_bandwidth(struct dc *dc,
enum dc_validate_mode validate_mode);
void dcn42_prepare_mcache_programming(struct dc *dc, struct dc_state *context);
int dcn42_get_power_profile(const struct dc_state *context);
#endif /* _DCN42_RESOURCE_H_ */